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1-88
®
HC-5560
July 2003
FN2887.3
PCM Transcoder
Features
The HC-5560 digital line transcoder provides encoding and
decoding of pseudo ternary line code substitution schemes.
Unlike other industry standard transcoders, the HC-5560
provides four worldwide compatible mode selectable code
substitution schemes, including HDB3 (High Density Bipolar
3), B6ZS, B8ZS (Bipolar with 6 or 8 Zero Substitution) and
AMI (Alternate Mark Inversion).
• Single 5V Supply . . . . . . . . . . . . . . . . . . . . . . 10mA (Typ)
The HC-5560 is fabricated in CMOS and operates from a
single 5V supply. All inputs and outputs are TTL compatible.
• Simultaneous Encoding and Decoding
Application Note #573, “The HC-5560 Digital Line
Transcoder,” by D.J. Donovan is available.
• Mode Selectable Coding Including:
- AMI (T1, T1C)
- B8ZS (T1)
- HDB3 (PCM30)
• North American and European Compatibility
• Asynchronous Operation
• Loop Back Control
• Transmission Error Detection
Part Number Information
PART
NUMBER
HC3-5560-5
TEMP. RANGE
(oC)
0 to 70
• Alarm Indication Signal
PACKAGE
20 Ld PDIP
PKG. DWG. #
Applications
E20.3
• North American and European PCM Transmission Lines
where Pseudo Ternary Line Code Substitution Schemes
are Desired
Pinout
HC-5560
(PDIP)
TOP VIEW
FORCE AIS
1
20 VDD
MODE SELECT 1
2
19 OUTPUT ENABLE
NRZ DATA IN 3
• Any Equipment that Interfaces T1, T1C, T2 or PCM30
Lines Including Multiplexers, Channel Service Units,
(CSUs) Echo Cancellors, Digital Cross-Connects (DSXs),
T1 Compressors, etc.
• Related Literature
- AN573, The HC-5560 Digital Line Transcoder
18 RESET
CLK ENC
4
17 OUT1
MODE SELECT 2
5
16 OUT2
NRZ DATA OUT 6
• Replaces MJ1440, MJ1471 and TCM2201 Transcoders
Functional Diagram
15 BIN
CLK DEC
7
14 LOOP TEST ENABLE
RESET AIS
8
13 AIN
AIS
9
12 CLOCK
VSS 10
11 ERROR
MODE 1
SELECT 2
NRZ DATA IN
CLK ENC
VDD
VSS
TRANSMITTER/
ENCODER
CLOCK
OUTPUT
ENABLE
OUT 1
OUT 2
LOOP TEST
ENABLE
SWITCH
RECEIVER/
DECODER
NRZ DATA
OUT
AIN
BIN
FORCE AIS
RESET
CLK DEC
RESET AIS
1
ERROR
DETECT
AIS
DETECT
ERROR
AIS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
HC-5560
Absolute Maximum Ratings
Thermal Information
Voltage at Any Pin . . . . . . . . . . . . . . . . . . . . GND -0.3V to VDD 0.3V
Maximum VDD Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
67
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Storage Temperature Range . . . . . . . . . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . 300o
Operating Conditions
Operating Temperature Range . . . . . . . . . . . . . . . . . . . 0oC to 70oC
Operating VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±5%
Die Characteristics
Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4322
Die Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . .119 mils x 133 mils
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+V
Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SAJI CMOS
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Unless Otherwise Specified, Typical parameters at 25oC, Min-Max parameters are over operating
temperature range. VDD = 5V.
Electrical Specifications
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
lDD
-
-
100
µA
-
10
-
mA
STATIC SPECIFICATIONS
Quiescent Device Current
Operating Device Current
OUT1, OUT2 Low (Sink) Current
(VOL = 0.4V)
IOL1
3.2
-
-
mA
All Other Outputs Low (Sink) Current
(VOL = 0.8V)
IOL2
2
-
-
mA
All Outputs High (Source) Current
(VOH = 4V)
IOH
2
-
-
mA
Input Low Current
IIL
-
-
10
µA
Input High Current
IIH
-
-
10
µA
Input Low Voltage
VlL
-
-
0.8
V
Input High Voltage
VlH
2.4
-
-
V
Input Capacitance
ClN
-
-
8
pF
Unless Otherwise Specified, Typical parameters at 25oC, Min-Max parameters are over operating
temperature range. VDD = 5V.
Electrical Specifications
PARAMETER
SYMBOL
FIGURE
MIN
TYP
MAX
UNITS
-
-
8.5
MHz
DYNAMIC SPECIFICATIONS
CLK ENC, CLK DEC Input Frequency
CLK ENC, CLK DEC Rise Time (1.544MHz)
fCL
tRCL
1, 2
-
10
60
ns
Fall Time
tFCL
1, 2
-
10
60
ns
Rise Time (2.048MHz)
tRCL
1, 2
-
10
40
ns
Fall Time
tFCL
1, 2
-
10
40
ns
Rise Time (6.3212MHz)
tRCL
1, 2
-
10
30
ns
Fall Time
tFCL
1, 2
-
10
30
ns
Rise Time (8.448MHz)
tRCL
1, 2
-
5
10
ns
Fall Time
tFCL
1, 2
-
5
10
ns
2
HC-5560
Unless Otherwise Specified, Typical parameters at 25oC, Min-Max parameters are over operating
temperature range. VDD = 5V. (Continued)
Electrical Specifications
PARAMETER
SYMBOL
FIGURE
MIN
TYP
MAX
UNITS
tS
1
20
-
-
ns
tH
1
20
-
-
ns
tS
2
15
-
-
ns
tH
2
5
-
-
ns
tDD
1
-
23
80
ns
fCL = 1.544MHz
tW
1
-
324
-
ns
fCL = 2.048MHz
tW
1
-
224
-
ns
fCL = 6.3212MHz
tW
1
-
79
-
ns
fCL = 8.448MHz
tW
1
-
58
-
ns
CLK DEC to NRZ-Data Out
tDD
2
-
25
54
ns
Setup Time CLK DEC to Reset AlS
tS2
3
35
-
-
ns
Hold Time of Reset AlS = ‘0’
tH2
3
20
-
-
ns
Setup Time Reset AlS = ‘1’ to CLK DEC
tS2
3
0
-
-
ns
Reset AlS to AIS Output
tPD5
3
-
-
42
ns
CLK DEC to Error Output
tPD4
3
-
-
62
ns
NRZ-Data In to CLK ENC Data Setup Time
Data Hold Time
AIN, BIN to CLK DEC Data Setup Time
Data Hold Time
CLK ENC to OUT1, OUT2
OUT1, OUT2 Pulse Width (CLK ENC Duty Cycle = 50%)
Pin Descriptions
PIN NUMBER
FUNCTION
DESCRIPTION
1
Force AIS
Pin 19 must be at logic ‘0’ to enable this pin. A logic ‘1’ on this pin forces OUT1 and OUT2 to all ‘1’s. A logic
‘0’ on this pin allows normal operation.
2, 5
Mode Select 1,
Mode Select 2
3
NRZ Data In
4
CLK ENC
6
NRZ Data Out
7
CLK DEC
8, 9
Reset AIS, AlS
10
VSS
Ground reference.
11
Error
A logic ‘1’ indicates that a violation of the line coding scheme has been decoded.
12
Clock
“OR” function of AIN and BIN for clock regeneration when pin 14 is at logic ‘0’, “OR” function of OUT1 and
OUT2 when pin 14 is at logic ‘1’.
13, 15
AIN, BIN
Inputs representing the received PCM signal. AIN = ‘1’ represents a positive going ‘1’ and BIN = ‘1’ represents
a negative going ‘1’. AIN and BIN are sampled by the positive going edge of CLK DEC. AIN and BIN may be
interchanged.
MS1
0
0
1
1
MS2
0
1
0
1
Functions As
AMI
B8ZS
B6ZS
HDB3
Input data to be encoded into ternary form. The data is clocked by the negative going edge of CLK ENC.
Clock encoder, clock for encoding data at NRZ Data In.
Decoded data from ternary inputs AIN and BIN.
Clock decoder, clock for decoding ternary data on inputs AIN and BIN.
3
Logic ‘0’ on Reset AIS resets a decoded zero counter and either resets AIS output to zero provided 3 or more
zeros have been decoded in the preceding Reset AIS period or sets AlS to ‘1’ if less than 3 zeros have been
decoded in the preceding two Reset AlS periods. A period of Reset AlS is defined from the bit following the
bit during which Reset AlS makes a high to low transition to the bit during which Reset AIS makes the next
high to low transition.
HC-5560
Pin Descriptions
(Continued)
PIN NUMBER
FUNCTION
DESCRIPTION
14
LTE
Loop Test Enable, this pin selects between normal and loop back operation. A logic ‘0’ selects normal
operation where encode and decode are independent and asynchronous. A logic ‘1’ selects a loop back
condition where OUT1 is internally connected to AIN and OUT2 is internally connected to BIN. A decode clock
must be supplied.
16, 17
OUT1, OUT2
Outputs representing the ternary encoded NRZ Data In signal for line transmission. OUT1 and OUT2 are in
return to zero form and are clocked out on the positive going edge of CLK ENC. The length of OUT1 and
OUT2 is set by the length of the positive clock pulse.
18
Reset
19
Output Enable
20
VDD
A logic ‘0’ on this pin resets all internal registers to zero. A logic ‘1’ allows normal operation of all internal
registers.
A logic ‘1’ on this pin forces outputs OUT1 and OUT2 to zero. A logic ‘0’ allows normal operation.
Power to chip.
Functional Description
The HC-5560 TRANSCODER can be divided into six sections:
transmission (coding), reception (decoding), error detection, all
ones detection, testing functions, and output controls.
The transmitter codes a non-return to zero (NRZ) binary
unipolar input signal (NRZ Data In) into two binary unipolar
return to zero (RZ) output signals (OUT1, OUT2). These
output signals represent the NRZ data stream modified
according to the selected encoding scheme (i.e., AMl, B8ZS,
B6ZS, HDB3) and are externally mixed together (usually via
a transistor or transformer network) to create a ternary
bipolar signal for driving transmission lines.
The receiver accepts as its input the ternary data from the
transmission line that has been externally split into two binary
unipolar return to zero signals (AIN and BIN). These signals are
decoded, according to the rules of the selected line code into
one binary unipolar NRZ output signal (NRz Data Out).
The encoder and decoder sections of the chip perform
independently (excluding loopback condition) and may
operate simultaneously.
The Error output signal is active high for one cycle of CLK
DEC upon the detection of any bipolar violation in the
received AIN and BIN signals that is not part of the selected
line coding scheme. The bipolar violation is not removed,
however, and shows up as a pulse in the NRZ Data Out
signal. In addition, the Error output signal monitors the
received AIN and BIN signals for a string of zeros that
violates the maximum consecutive zeros allowed for the
selected line coding scheme (i.e., 15 for AMI, 8 for B8ZS, 6
for B6ZS, and 4 for HDB3). ln the event that an excessive
amount of zeros is detected, the Error output signal will be
active high for one cycle of CLK DEC during the zero that
exceeds the maximum number. In the case that a high level
should simultaneously appear on both received input signals
AIN and BIN a logical one is assumed and appears on the
NRZ Data Out stream with the Error output active.
An input signal received at inputs AIN and BIN that consists
of all ones (or marks) is detected and signaled by a high
4
level at the Alarm Indication Signal (AlS) output. This is also
known as Blue Code. The AlS output is set to a high level
when less than three zeros are received during one period of
Reset AIS immediately followed by another period of Reset
AlS containing less than three zeros. The AIS output is reset
to a low level upon the first period of Reset AlS containing 3
or more zeros.
A logic high level on LTE enables a loopback condition
where OUT1 is internally connected to AIN and OUT2 is
internally connected to BIN (this disables inputs AIN and BIN
to external signals). In this condition, NRZ Data In appears
at NRZ Data Out (delayed by the amount of clock cycles it
takes to encode and decode the selected line code). A
decode clock must be supplied for this operation.
The output controls are Output Enable and Force AlS. These
pins allow normal operation, force OUT1 and OUT2 to zero,
or force OUT1 and OUT2 to output all ones (AIS condition).
Line Code Descriptions
AMl, Alternate Mark Inversion, is used primarily in North
American T1 (1.544MHz) and T1C (3.152MHz) carriers.
Zeros are coded as the absence of a pulse and ones are
coded alternately as positive or negative pulses. This type of
coding reduces the average voltage level to zero to eliminate
DC spectral components, thereby eliminating DC wander. To
simplify timing recovery, logic 1’s are encoded with 50% duty
cycle pulses.
e.g.,
PCM CODE
0
0
0
1
0 1
1
1
0 1
0
0
0 0
0 1
AMI CODE
To facilitate timing maintenance at regenerative repeaters
along a transmission path, a minimum pulse density of logic
1’s is required. Using AMl, there is a possibility of long
strings of zeros and the required density may not always
exist, leading to timing jitter and therefore higher error rates.
HC-5560
A method for insuring minimum logic 1 density by substituting
bipolar code in place of strings of 0’s is called BNZS or Bipolar
with N Zero Substitution. B6ZS is used commonly in North
American T2 (6.3212MHz) carriers. For every string of 6
zeros, bipolar code is substituted according to the following
rule:
• If the immediate preceding pulse is of (-) polarity, then
code each group of 6 zeros as 0+- 0+-, and if the
immediate preceding pulse is of (+) polarity, code each
group of 6 zeros as 0+- 0-+.
One can see the consecutive logic 1 pulses of the same
polarity violate the AMI coding scheme.
Another coding scheme is HDB3, high density bipolar 3, used
primarily in Europe for 2.048MHz and 8.448MHz carriers. This
code is similar to BNZS in that it substitutes bipolar code for 4
consecutive zeros according to the following rule:
1. If the polarity of the immediate preceding pulse is (-) and
there have been an odd (even) number of logic 1 pulses
since the last substitution, each group of 4 consecutive
zeros is coded as 000-(+00+).
2. If the polarity of the immediate preceding pulse is (+) then
the substitution is 000+(-00-) for odd (even) number of
logic 1 pulses since the last substitution.
e.g.,
4
e.g.,
PCM CODE
6
PCM CODE
0
0
0
1
0
1 1 1 0 0
0
-
0
0
+ 0
0
+
0
-
0 0 0 0 1 0 1
0 0
1
4
0
-
1 1
0 0
+
0 0
0
0 1
0 0 +
V
HDB3 (-)
V
B6ZS (-)
V
V
0
+
0
-
0
-
+
0
0
+
-
0
0
V
HDB3 (+)
V
B6ZS (+)
V = VIOLATION
V
V
V = VIOLATION
B8ZS is used commonly in North American T1 (1.544MHz)
and T1C (3.152MHz) carriers. For every string of 8 zeros,
bipolar code is substituted according to the following rules:
1. If the immediate preceding pulse is of (-) polarity, then
code each group of 8 zeros as 000-+ 0+-.
2. If the immediate preceding pulse is of (+) polarity then
code each group of 8 zeros as 000+-0-+.
e.g.,
8
PCM CODE
1 0 1 0
0
0
0
0
0
0
0
0
0
0
-
+ 0
+
-
1
1
0
V
B8ZS (-)
V
0
0
0
+
-
0
-
+
B8ZS (+)
V
V = VIOLATION
The BNZS coding schemes, in addition to eliminating DC
wander, minimize timing jitter and allow a line error
monitoring capability.
5
The 3 in HDB3 refers to the coding format that precludes
strings of zeros greater than 3. Note that violations are
produced only in the fourth bit location of the substitution
code and that successive substitutions produce alternate
polarity violations.
HC-5560
Application Diagram
5V
VDD
FROM CODEC OR
TRANSCODER
NRZ DATA IN
ENCODER CLOCK
CLK ENC
OUT1
T1, T2, T1C,
PCM 30
LINE OUTPUT
V+
ENCODER
OUT2
FORCE AIS
MS1
LTE
MS2
CONTROL
DIFF
AMP
±
AIN
±
BIN
CLOCK RECOVERY
CLOCK
RESET
OUTPUT
ENABLE
LINE
INPUT
MODE SELECT
LOGIC INPUTS
RESET AIS
ALARM CLOCK
AIS
ALARM
ERROR
ERROR
DECODER
TO CODED OR TRANSCODER
NRZ DATA OUT
V+
CLK DEC
VSS
DECODER CLOCK
Timing Waveforms
1
fCL
tFCL
tRCL
90%
50%
CLK ENC
10%
tS
NRZ DATA IN
tH
50%
50%
tDD
50%
50%
OUT 1, OUT 2
tW
FIGURE 1. TRANSMITTER (CODER) TIMING WAVEFORMS
6
ERROR
MONITORS
MS1
MS2
SELECTS
0
0
1
1
0
1
0
1
AMI
B8ZS
B6ZS
HDB3
HC-5560
Timing Waveforms
(Continued)
1
fCL
tRCL
tFCL
CLK DEC
90%
50%
10%
tH
tS
50%
AIN, BIN
50%
CLOCK
tDD
50%
NRZ DATA OUT
FIGURE 2. RECEIVER (DECODER) TIMING WAVEFORMS
50%
50%
CLK DEC
tS2
tH2
RESET AIS
50%
tS2
50%
tPD5
AIS OUTPUT
50%
tPD4
ERROR OUTPUT
50%
FIGURE 3. RESET AIS INPUT, AIS OUTPUT, ERROR OUTPUT
CLK DEC
RESET AIS
NRZ DATA OUT
AIS
FIGURE 4.
Two consecutive periods of Reset AIS, each containing less than three zeros, sets AIS to a logic ‘1’ and remains in a logic ‘1’ state
until a period of Reset AIS contains three or more zeros.
7
HC-5560
Timing Waveforms
(Continued)
CLK DEC
RESET AIS
NRZ DATA OUT
AIS
FIGURE 5.
Zeros which occur during a high to low transition of Reset AIS are counted with the zeros that occurred before the high to low
transition.
NRZ DATA IN
CLK ENC
OUT 1
AMI
OUT 2
OUT 1
S
S
HDB3
S
OUT 2
S
S
S
OUT 1
S
B6ZS
S
OUT 2
S
S
OUT 1
S
B8ZS
S
OUT 2
3 1/2 CYCLES
5 1/2 CYCLES
FIGURE 6. ENCODE TIMING AND DELAY
Data is clocked on the negative edge of CLK ENC and appears on OUT1 and OUT2. OUT1 and OUT2 are interchangeable.
Bipolar violations and all other pulses inserted by the line coding scheme to encode strings of zeros are labeled with an “S”.
8
HC-5560
Timing Waveforms
(Continued)
CLK DEC
AMI
AIN
BIN
NRZ DATA OUT
HDB3
S
AIN
S
S
S
BIN
S
S
S
S
NRZ DATA OUT
B6ZS
S
AIN
BIN
S
S
S
S
S
S
S
S
S
NRZ DATA OUT
B8ZS
S
AIN
S
S
BIN
NRZ DATA OUT
S
S
S
S
S
4 CYCLES
6 CYCLES
8 CYCLES
FIGURE 7. DECODE TIMING AND DELAY
Data that appears on AIN and BIN is clocked by the positive edge of CLK DEC, decoded, and zeros are inserted for all valid line
code substitutions. The data then appears in non-return to zero to zero form at output NRZ Data Out. AIN and BIN are
interchangeable.
CLK DEC
S
E
AIN
E
BIN
E
NRZ DATA
OUT
ERROR
FIGURE 8.
The ERROR signal indicates bipolar violations that are not part of a valid substitution.
9
S
S
S
HC-5560
Dual-In-Line Plastic Packages (PDIP)
E20.3 (JEDEC MS-001-AD ISSUE D)
N
20 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2 3
INCHES
N/2
-B-
-AD
E
BASE
PLANE
-C-
A2
SEATING
PLANE
A
L
D1
e
B1
D1
A1
eC
B
0.010 (0.25) M
C A B S
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.045
0.070
1.55
1.77
8
eA
C
0.008
0.014
C
D
0.980
1.060
eB
NOTES:
0.204
0.355
24.89
-
26.9
5
D1
0.005
-
0.13
-
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
e
0.100 BSC
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
eA
0.300 BSC
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
eB
-
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication No. 95.
L
0.115
N
2.54 BSC
7.62 BSC
0.430
-
0.150
2.93
20
6
10.92
7
3.81
4
20
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
9
Rev. 0 12/93
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
10
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