DATASHEET

HM-6516
TM
2K x 8 CMOS RAM
March 1997
Features
Description
• Low Power Standby. . . . . . . . . . . . . . . . . . . 275µW Max
The HM-6516 is a CMOS 2048 x 8 Static Random Access
Memory. Extremely low power operation is achieved by the
use of complementary MOS design techniques. This low
power is further enhanced by the use of synchronous circuit
techniques that keep the active (operating) power low, which
also gives fast access times. The pinout of the HM-6516 is
the popular 24 pin, 8-bit wide JEDEC standard, which allows
easy memory board layouts, flexible enough to accommodate a variety of PROMs, RAMS, EPROMs, and ROMs.
• Low Power Operation . . . . . . . . . . . . . .55mW/MHz Max
• Fast Access Time . . . . . . . . . . . . . . . . . 120/200ns Max
• Industry Standard Pinout
• Single Supply . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0V VCC
• TTL Compatible
• Static Memory Cells
The HM-6516 is ideally suited for use in microprocessor
based systems. The byte wide organization simplifies the
memory array design, and keeps operating power down to a
minimum, because only one device is enabled at a time. The
address latches allow very simple interfacing to recent generation microprocessors which employ a multiplexed
address/data bus. The convenient output enable control also
simplifies multiplexed bus interfacing by allowing the data
outputs to be controlled independent of the chip enable.
• High Output Drive
• On-Chip Address Latches
• Easy Microprocessor Interfacing
Ordering Information
120ns
HM1-6516B-9
8403607JA
200ns
TEMP. RANGE
HM1-6516-9
29102BJA
HM4-6516-9
-55oC to +125oC
-40oC to +85oC
8403601ZA
-55oC to +125oC
8403601JA
-
8403607ZA
PACKAGE
-40oC to +85oC
-55oC to +125oC
CERDIP
PKG. NO.
F24.6
JAN#
F24.6
SMD#
F24.6
CLCC
J32.A
SMD#
J32.A
Pinouts
HM-6516
(CLCC)
TOP VIEW
NC
VCC
2
1
32 31 30
NC
NC
3
NC
NC
4
PIN
A5 3
24 VCC
23 A8
22 A9
A4 4
A3 5
21 W
20 G
A2 6
A1 7
19 A10
18 E
A0 8
DQ0 9
17 DQ7
A1 10
24 A10
16 DQ6
15 DQ5
A0 11
23 E
NC 12
22 DQ7
A0 - A10
A4 7
27 NC
A3 8
26 W
A2 9
25 G
DQ0 13
21 DQ6
DQ5
DQ4
DQ3
14 15 16 17 18 19 20
NC
14 DQ4
13 DQ3
NC
28 A9
DQ1
GND 12
29 A8
A5 6
DQ2
DQ1 10
DQ2 11
A6 5
GND
A7 1
A6 2
A7
HM-6516
(CERDIP)
TOP VIEW
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Copyright © Intersil Americas Inc. 2001. All Rights Reserved
1
E
V SS/GND
DESCRIPTION
No Connect
Address Inputs
Chip Enable/Power Down
Ground
DQ0 - DQ7 Data In/Data Out
VCC
Power (+5V)
W
Write Enable
G
Output Enable
File Number
2998.1
HM-6516
Functional Diagram
A10
A9
A8
A7
A6
A5
A4
A
7
GATED
ROW
DECODER
LATCHED
ADDRESS
REGISTER
128 x 128
MATRIX
128
A
7
L
1 OF 8
G
16
16
G
16
16
16
16
16
G
16
A
GATED COLUMN
DECODER
8
8
A
4
W
A
L
4
A
LATCHED ADDRESS
REGISTER
E
A3
A2
2
A1
A0
DQ0
THRU
DQ7
HM-6516
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
Input or Output Voltage Applied for all Grades. . . . . . . GND -0.3V to
V CC +0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance
θJA
θJC
CERDIP Package . . . . . . . . . . . . . . . . 48oC/W
8oC/W
CLCC Package . . . . . . . . . . . . . . . . . . 66oC/W
12oC/W
Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300oC
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Ranges:
HM-6516B-9, HM-6516-9 . . . . . . . . . . . . . . . . . . . -40oC to +85oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25953 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications VCC = 5V ±10%; TA = -40oC to +85oC (HM-6516B-9, HM-6516-9)
LIMITS
SYMBOL
ICCSB
PARAMETER
Standby Supply Current
MIN
MAX
UNITS
TEST CONDITIONS
-
50
µA
IO = 0mA, VI = VCC or GND,
VCC = 5.5V, HM-6516B-9
-
100
µA
IO = 0mA, VI = VCC or GND,
HM-6516-9
ICCOP
Operating Supply Current (Note 1)
-
10
mA
f = 1MHz, IO = 0mA, G = VCC, VCC =
5.5V, VI = VCC or GND
ICCDR
Data Retention Supply Current
-
25
µA
VCC = 2.0V, IO = 0mA, VI = VCC or
GND, E = VCC, HM-6516B-9
-
50
µA
VCC = 2.0V, IO = 0mA, VI = VCC or
GND, E = VCC, HM-6516-9
Data Retention Supply Voltage
2.0
-
V
Input Leakage Current
-1.0
+1.0
µA
VI = VCC or GND, VCC = 5.5V
IIOZ
Input/Output Leakage Current
-1.0
+1.0
µA
VIO = VCC or GND, VCC = 5.5V
VIL
Input Low Voltage
-0.3
0.8
V
VCC = 4.5V
VIH
Input High Voltage
2.4
VCC +0.3
V
VCC = 5.5V
VOL
Output Low Voltage
-
0.4
V
IO = 3.2mA, VCC = 4.5V
VOH1
Output High Voltage
2.4
-
V
IO = -1.0mA, VCC = 4.5V
VOH2
Output High Voltage (Note 2)
VCC -0.4
-
V
IO = -100µA, V CC = 4.5V
VCCDR
II
Capacitance TA = +25oC
SYMBOL
CI
CIO
PARAMETER
MAX
UNITS
Input Capacitance (Note 2)
8
pF
Input/Output Capacitance (Note 2)
10
pF
NOTES:
1. Typical derating 5mA/MHz increase in ICCOP.
2. Tested at initial design and after major design changes.
3
TEST CONDITIONS
f = 1MHz, All measurements are
referenced to device GND
HM-6516
AC Electrical Specifications VCC = 5V ±10%; TA = -40oC to +85oC (HM-6516B-9, HM-6516-9)
LIMITS
HM-6516B-9
SYMBOL
PARAMETER
HM-6516-9
MIN
MAX
MIN
MAX
UNITS
TEST
CONDITIONS
(1) TELQV
Chip Enable Access Time
-
120
-
200
ns
(Notes 1, 3)
(2) TAVQV
Address Access Time
-
120
-
200
ns
(Notes 1, 3, 4)
(3) TELQX
Chip Enable Output Enable Time
10
-
10
-
ns
(Notes 2, 3)
(4) TWLQZ
Write Enable Output Disable Time
-
50
-
80
ns
(Notes 2, 3)
(5) TEHQZ
Chip Enable Output Disable Time
-
50
-
80
ns
(Notes 2, 3)
(6) TGLQV
Output Enable Output Valid Time
-
80
-
80
ns
(Notes 1, 3)
(7) TGLQX
Output Enable Output Enable Time
10
-
10
-
ns
(Notes 2, 3)
(8) TGHQZ
Output Enable Output DisableTime
-
50
-
80
ns
(Notes 2, 3)
(9) TELEH
Chip Enable Pulse Negative Width
120
-
200
-
ns
(Notes 1, 3)
(10) TEHEL
Chip Enable Pulse Positive Width
50
-
80
-
ns
(Notes 1, 3)
(11) TAVEL
Address Setup Time
0
-
0
-
ns
(Notes 1, 3)
(12) TELAX
Address Hold Time
30
-
50
-
ns
(Notes 1, 3)
(13) TWLWH
Write Enable Pulse Width
120
-
200
-
ns
(Notes 1, 3)
(14) TWLEH
Write Enable Pulse Setup Time
120
-
200
-
ns
(Notes 1, 3)
(15) TELWH
Write Enable Pulse Hold Time
120
-
200
-
ns
(Notes 1, 3)
(16) TDVWH
Data Setup Time
50
-
80
-
ns
(Notes 1, 3)
(17) TWHDX
Data Hold Time
10
-
10
-
ns
(Notes 1, 3)
(18) TELEL
Read or Write Cycle Time
170
-
280
-
ns
(Notes 1, 3)
NOTES:
1. Input pulse levels: 0.8V to VCC - 2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load:
1 TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.
2. Tested at initial design and after major design changes.
3. V CC = 4.5V and 5.5V.
4. TAVQV = TELQV + TAVEL.
4
HM-6516
Timing Waveforms
(2)
TAVQV
(12)
TELAX
(11)
(11)
TAVEL
TAVEL
VALID ADD
A
NEXT
(10)
TEHEL
(18)
TELEL
(9)
TELEH
ADD
(10)
TEHEL
E
HIGH
W
(5)
TEHQZ
(3)
TELQX
(1)
TELQV
(5)
TEHQZ
DQ
VALID DATA OUT
(6)
TGLQV
TGHQZ
(8)
G
(7)
TGLQX
TIME
REFERENCE
-1
0
1
2
3
4
5
FIGURE 1. READ CYCLE
remain high throughout the read cycle. After the data has
been read, E may return high (T = 3). This will force the output buffers into a high impedance mode at time (T = 4). G is
used to disable the output buffers when in a logical “1” state
(T = -1, 0, 3, 4, 5). After (T = 4) time, the memory is ready for
the next cycle.
The address information is latched in the on-chip registers
on the falling edge of E (T = 0), minimum address setup and
hold time requirements must be met. After the required hold
time, the addresses may change state without affecting
device operation. During time (T = 1), the outputs become
enabled but data is not valid until time (T = 2), W must
Timing Waveforms (Continued)
(12)
TELAX
(11)
TAVEL
A
(11)
TAVEL
NEXT ADD
VALID ADD
(9)
TELEH
(10)
TEHEL
(18)
TELEL
(10)
TEHEL
E
(14)
TWLEH
(13)
TWLWH
W
(15)
TELWH
(17)
TWHDX
VALID DATA IN
DQ
G
(16)
TDVWH
HIGH
TIME
REFERENCE
-1
0
1
FIGURE 2. WRITE CYCLE
5
2
3
4
5
HM-6516
The write cycle is initiated on the falling edge of E (T = 0),
which latches the address information in the on-chip
registers. If a write cycle is to be performed where the output
is not to become active, G can be held high (inactive).
TDVWH and TWHDX must be met for proper device operation regardless of G. If E and G fall before W falls (read
mode), a possible bus conflict may exist. If E rises before W
rises, reference data setup and hold times to the E rising
edge. The write operation is terminated by the first rising edge
of W (T = 2) or E (T = 3). After the minimum E high time
(TEHEL), the next cycle may begin. If a series of consecutive
write cycles are to be performed, the W line may be held low
until all desired locations have been written. In this case, data
setup and hold times must be referenced to the rising of E.
Typical Performance Curve
VCC = 2.0V
-3
-4
LOG (ICC/(1A))
-5
-6
-7
-8
-9
-10
-11
-12
-55
-35
-15
5
25
45
65
85
105
125
FIGURE 3. TYPICAL ICCDR vs TA
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