UCC1895 UCC2895 UCC3895 application INFO available BiCMOS Advanced Phase Shift PWM Controller FEATURES DESCRIPTION • Programmable Output Turn-on Delay • • • • • • • The UCC3895 is a phase shift PWM controller that implements control of a full-bridge power stage by phase shifting the switching of one half-bridge Adaptive Delay Set with respect to the other. It allows constant frequency pulse-width modulaBidirectional Oscillator Synchronization tion in conjunction with resonant zero-voltage switching to provide high efficiency at high frequencies. The part can be used either as a voltage mode Capability for Voltage Mode or Current or current mode controller. Mode Control While the UCC3895 maintains the functionality of the UC3875/6/7/8 family Programmable Soft Start/Soft Stop and UC3879, it improves on that controller family with additional features and Chip Disable via a Single Pin such as enhanced control logic, adaptive delay set, and shutdown capability. Since it is built in BCDMOS, it operates with dramatically less supply 0% to 100% Duty Cycle Control current than it’s bipolar counterparts. The UCC3895 can operate with a 7MHz Error Amplifier maximum clock frequency of 1MHz. Operation to 1MHz The UCC3895 and UCC2895 are offered in the 20 pin SOIC (DW) pack- • Low Active Current Consumption (5mA Typical @ 500kHz) • Very Low Current Consumption During Undervoltage Lock-out (150µA typical) age, 20 pin PDIP (N) package, 20 pin TSSOP (PW) package, and 20 pin PLCC (Q). The UCC1895 is offered in the 20 pin CDIP (J) package, and 20 pin CLCC package (L). SIMPLIFIED APPLICATION DIAGRAM UCC3895 1 EAN 2 EAOUT 3 Q1 EAP 20 7 SS/DISB 19 RAMP OUTA 18 4 REF OUTB 17 5 GND PGND 16 6 SYNC VCC 15 7 CT OUTC 14 VOUT A VIN VBIAS B 8 RT OUTD 13 9 DELAB CS 12 10 DELCD ADS 11 C D UDG-98139 SLUS157A - DECEMBER 1999 UCC1895 UCC2895 UCC3895 CONNECTION DIAGRAMS ABSOLUTE MAXIMUM RATINGS Supply Voltage (IDD < 10mA) . . . . . . . . . . . . . . . . . . . . . . . 17V Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA REF current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15mA OUT Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA Analog inputs (EAP, EAN, EAOUT, RAMP, SYNC, ADS, CS, SS/DISB) . . . . . . . . . . . –0.3V to REF+0.3V Power Dissipation at TA=+25°C (N Package). . . . . . . . . . . . 1W Power Dissipation at TA=+25°C (D Package) . . . . . . . . 650mW Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . –55°C to +125°C Lead Temperature (soldering, 10 sec). . . . . . . . . . . . . . +300°C DIL-20,c SOIC-20, TSSOP-20 (TOP VIEW) J or N Package, DW Package, PW Package Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of package. TEMPERATURE & PACKAGE SELECTION TABLE TEMPERATURE RANGE –55°C to +125°C –40°C to +85°C 0°C to +70°C UCC1895 UCC2895 UCC3895 PACKAGE SUFFIX J, L DW, N, PW, Q DW, N, PW, Q 1 20 EAP EAOUT 2 19 SS/DISB RAMP 3 18 OUTA REF 4 17 OUTB GND 5 16 PGND SYNC 6 15 VDD CT 7 14 OUTC RT 8 13 OUTD DELAB 9 12 CS DELCD 10 11 ADS PLCC-20, CLCC-20 (TOP VIEW) Q Package, L Package EAN EAOUT RAMP ORDERING INFORMATION UCC EAN 895 EAP SS/DISB 3 2 1 20 19 REF 4 18 OUTA GND 5 17 OUTB SYNC 6 16 PGND CT 7 15 VDD RT 8 14 OUTC 9 10 11 12 13 OUTD DELAB DELCD CS ADS ELECTRICAL CHARACTERISTICS: Unless otherwise specified, VDD=12V, RT=82kΩ, CT=220pF, RDELAB=10kΩ, RDELCD=10kΩ, CREF=0.1µF, CVDD=1.0µF, no load at outputs. TA = TJ. TA = 0°C to 70°C for UCC3895x, –40°C to +85°C for UCC2895x, and –55°C to +125°C for UCC1895x. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Start Threshold 10.2 11 11.8 Stop Threshold 8.2 9 9.8 V Hysteresis 1.0 2.0 3.0 V 150 250 µA 5 6 mA 17.5 18.5 V UVLO Section V Supply Current Start-up Current VDD = 8V IDD Active VDD Clamp Voltage IDD = 10mA 16.5 2 UCC1895 UCC2895 UCC3895 ELECTRICAL CHARACTERISTICS: Unless otherwise specified, VDD=12V, RT=82kΩ, CT=220pF, RDELAB=10kΩ, RDELCD=10kΩ, CREF=0.1µF, CVDD=1.0µF, no load at outputs. TA = TJ. TA = 0°C to 70°C for UCC3895x, –40°C to +85°C for UCC2895x, and –55°C to +125°C for UCC1895x. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS TJ = 25°C 4.94 5.00 5.06 V 10V < VDD < 17.5V, 0mA < IREF < 5mA, Temperature 4.85 5 5.15 V 10 20 Voltage Reference Section Output Voltage Short Circuit Current REF = 0V, TJ = 25°C mA Error Amplifier Section Common Mode Input Voltage Range Offset Voltage Input Bias Current (EAP, EAN) –0.1 3.6 V –7 7 mV 1 µA 4.0 4.5 5.0 V 0 0.2 0.4 1.0 1.5 mA 2.5 4.5 mA 75 85 dB –1 EAOUT VOH EAP–EAN = 500mV, IEAOUT= –0.5mA EAOUT VOL EAP–EAN = –500mV, IEAOUT= 0.5mA EAOUT Source Current EAP–EAN = 500mV, EAOUT= 2.5V EAOUT Sink Current EAP–EAN = –500mV, EAOUT= 2.5V Open Loop DC Gain V Unity Gain Bandwidth (Note 3) 5.0 7.0 MHz Slew Rate EAN from 1V to 0V, EAP = 500mV, EAOUT from 0.5V to 3.0V 1.5 2.2 V/µs 0.45 0.50 No Load Comparator Turn-Off Threshold 0.55 V No Load Comparator Turn-On Threshold 0.55 0.60 0.69 V No Load Comparator Hysteresis 0.035 0.100 0.165 V 473 500 527 kHz 2.5 5 % SYNC VIH 2.05 2.10 2.25 V SYNC VIL 1.85 1.90 1.95 V Oscillator Section Frequency TJ = 25°C Total Variation Line, Temperature (Note 3) SYNC VOH ISYNC = –400µA, CT = 2.6V 4.1 4.5 5.0 V SYNC VOL ISYNC = 100µA, CT = 2.6V 0.0 0.5 1.0 V SYNC Output Pulse Width SYNC Load = 3.9kΩ and 30pF in parallel 85 135 ns RT Voltage 2.9 3 3.1 V CT Peak Voltage 2.25 2.35 2.50 V CT Valley Voltage 0.0 0.2 0.4 V PWM Comparator Section EAOUT to RAMP Input Offset Voltage RAMP = 0V, DELAB = DELCD = REF 0.72 0.85 1.05 V Minimum Phase Shift (OUTA to OUTC, OUTB to OUTD) RAMP = 0V, EAOUT = 650mV (Note 1) 0.00 0.85 1.40 % RAMP to OUTC/OUTD Delay RAMP from 0V to 2.5V, EAOUT = 1.2V, DELAB = DELCD = REF (Note 2) 70 120 ns RAMP Bias Current RAMP < 5V, CT < 2.2V –5 5 µA RAMP Sink Current RAMP = 5V, CT < 2.6V 12 19 mA Current Sense Section CS Bias Current 0 < CS , 2.5V, 0 < ADS < 2.5V Peak Current Threshold Overcurrent Threshold CS to Output Delay CS from 0 to 2.3V, DELAB = DELCD = REF 3 –4.5 20 µA 2.10 V 1.90 2.00 2.4 2.5 2.6 V 75 110 ns UCC1895 UCC2895 UCC3895 ELECTRICAL CHARACTERISTICS: Unless otherwise specified, VDD=12V, RT=82kΩ, CT=220pF, RDELAB=10kΩ, RDELCD=10kΩ, CREF=0.1µF, CVDD=1.0µF, no load at outputs. TA = TJ. TA = 0°C to 70°C for UCC3895x, –40°C to +85°C for UCC2895x, and –55°C to +125°C for UCC1895x. PARAMETER TEST CONDITIONS MIN TYP –40 –35 MAX UNITS Soft Start/Shutdown Section Soft Start Source Current SS/DISB = 3.0V, CS < 1.9V Soft Start Sink Current SS/DISB = 3.0V, CS > 2.6V Soft Start/Disable Comparator Threshold 325 350 375 µA µA 0.44 0.50 0.56 V –30 Delay Set Section DELAB/DELCD Output Voltage ADS = CS = 0V 0.45 0.50 0.55 V ADS = 0V, CS = 2.0V 1.9 2.0 2.1 V Output Delay ADS = CS = 0V (Note 2) 450 525 600 ns ADS Bias Current 0V < ADS < 2.5V, 0V < CS < 2.5V –20 20 µA Output Section VOH (all outputs) IOUT = –10mA, VDD to Output 250 400 mV VOL (all outputs) IOUT = 10mA 150 250 mV Rise TIme CLOAD = 100pF 20 35 ns Fall Time CLOAD = 100pF 20 35 ns Note 1: Minimum phase shift is defined as followed: Φ = 200 • Φ = 200 • tf ( OUTA ) − tf ( OUTC ) tPERIOD tf ( OUTB ) − tf ( OUTD ) tPERIOD tPERIOD Or OUTA where tDELAY = t f(OUTA) – t f(OUTC) tf(OUTA) = falling edge of OUTA signal tf(OUTB) = falling edge of OUTB signal tf(OUTC) = falling edge of OUTC signal tf(OUTD) = falling edge of OUTD signal t(PERIOD) = period of OUTA or OUTB signal OUTC Same applies to OUTB and OUTD Note 2. Output delay is measured between OUTA/OUTB or OUTC/OUTD. Output delay is defined as shown below, where: tf(OUTA) = falling edge of OUTA signal tr(OUTB) = rising edge of OUTB signal OUTA tDELAY = tf(OUTA) – tr(OUTB) Note 3: Guaranteed by design. Not 100% tested in production. OUTB Same applies to OUTC and OUTD 4 UCC1895 UCC2895 UCC3895 PIN DESCRIPTIONS ADS: Adaptive Delay Set. This function sets the ratio between the maximum and minimum programmed output delay dead time. When the ADS pin is directly connected to the CS pin, no delay modulation occurs. The maximum delay modulation occurs when ADS is grounded. In this case, delay time is four times longer when CS = 0 than when CS = 2.0V (the Peak Current threshold), ADS changes the output voltage on the delay pins DELAB and DELCD by the following formula: DELAB, DELCD: Delay Programming Between Complementary Outputs. DELAB programs the dead time between switching of OUTA and OUTB, and DELCD programs the dead time between OUTC and OUTD. This delay is introduced between complementary outputs in the same leg of the external bridge. The UCC3895 allows the user to select the delay, in which the resonant switching of the external power stages takes place. Separate delays are provided for the two half-bridges to accommodate differences in resonant capacitor charging currents. The delay in each stage is set according to the following formula: V DEL = [0 . 75 • (VCS − V ADS )] + 0 . 5V where VCS and VADS are in Volts. ADS must be limited to between 0V and 2.5V and must be less than or equal to CS. DELAB and DELCD also will be clamped to a minimum of 0.5V. (25 • 10 ) • R −12 t DELAY = V DEL DEL + 25 ns EAOUT: Error Amplifier Output. It is also connected internally to the non-inverting input of the PWM comparator and the no-load comparator. EAOUT is internally clamped to the soft start voltage. The no-load comparator shuts down the output stages when EAOUT falls below 500mV, and allows the outputs to turn-on again when EAOUT rises above 600mV. where VDEL is in Volts, and RDEL is in Ohms and tDELAY is in seconds. DELAB and DELCD can source about 1mA maximum. Choose the delay resistors so that this maximum is not exceeded. Programmable output delay can be defeated by tying DELAB and/or DELCD to REF. For an optimum performance keep stray capacitance on these pins at <10pF. CT: Oscillator Timing Capacitor. (Refer to Fig. 1, Oscillator Block Diagram) The UCC3895’s oscillator charges CT via a programmed current. The waveform on CT is a sawtooth, with a peak voltage of 2.35V. The approximate oscillator period is calculated by the following formula: EAP: The non-inverting input to the error amplifier. t OSC = EAN: The inverting input to the error amplifier. GND: Chip ground for all circuits except the output stages. 5 • RT • CT + 120 ns 48 OUTA, OUTB, OUTC, OUTD: The 4 outputs are 100mA complementary MOS drivers, and are optimized to drive FET driver circuits. OUTA and OUTB are fully complementary, (assuming no programmed delay). They operate near 50% duty cycle and one-half the oscillating frequency. OUTA and OUTB are intended to drive one half-bridge circuit in an external power stage. OUTC and OUTD will drive the other half-bridge and will have the same characteristics as OUTA and OUTB. OUTC is phase shifted with respect to OUTA, and OUTD is phase shifted with respect to OUTB. Note that changing the phase relationship of OUTC and OUTD with respect to OUTA and OUTB requires other than the nominal 50% duty ratio on OUTC and OUTD during those transients. where CT is in Farads, and RT is in Ohms and tOSC is in seconds. CT can range from 100pF to 880pF. Please note that a large CT and a small RT combination will result in extended fall times on the CT waveform. The increased fall time will increase the SYNC pulse width, hence limiting the maximum phase shift between OUTA, OUTB and OUTC, OUTD outputs, which limits the maximum duty cycle of the converter. CS: Current Sense. This is the inverting input of the Current Sense comparator and the non-inverting input of the Over-current comparator, and the ADS amplifier. The current sense signal is used for cycle-by-cycle current limiting in peak current mode control, and for overcurrent protection in all cases with a secondary threshold for output shutdown. An output disable initiated by an overcurrent fault also results in a restart cycle, called “soft stop”, with full soft start. PGND: Output Stage Ground. To keep output switching noise from critical analog circuits, the UCC3895 has 2 different ground connections. PGND is the ground connection for the high-current output stages. Both GND and PGND must be electrically tied together closely near the IC. Also, since PGND carries high current, board traces must be low impedance. 5 UCC1895 UCC2895 UCC3895 PIN DESCRIPTIONS (cont.) Soft Start Mode: After a fault or disable condition has passed, VDD is above the start threshold, and/or SS/DISB falls below 0.5V during a soft stop, SS/DISB will switch to a soft start mode. The pin will now source current, equal to IRT. A user-selected capacitor on SS/DISB determines the soft start (and soft-start) time. In addition, a resistor in parallel with the capacitor may be used, limiting the maximum voltage on SS/DISB. Note that SS/DISB will actively clamp the EAOUT pin voltage to approximately the SS/DISB pin voltage during both soft start, soft stop, and disable conditions. RAMP: The Inverting Input of the PWM Comparator. This pin receives either the CT waveform in voltage and average current mode controls, or the current signal (plus slope compensation) in peak current mode control. An internal discharge transistor is provided on RAMP, which is triggered during the oscillator dead time. RT: Oscillator Timing Resistor. (Refer to Fig. 1, Oscillator Block Diagram) The oscillator in the UCC3895 operates by charging an external timing capacitor, CT, with a fixed current programmed by RT. RT current is calculated as follows: I RT = SYNC: Oscillator Synchronization. (Refer to Fig. 1, Oscillator Block Diagram) This pin is bidirectional. When used as an output, SYNC can be used as a clock, which is the same as the chip’s internal clock. When used as an input, SYNC will override the chip’s internal oscillator and act as it’s clock signal. This bidirectional feature allows synchronization of multiple power supplies. The SYNC signal will also internally discharge the CT capacitor and any filter capacitors that are present on the RAMP pin. The internal SYNC circuitry is level sensitive, with an input low threshold of 1.9V, and an input high threshold of 2.1V. A resistor as small as 3.9kΩ may be tied between SYNC and GND to reduce the sync pulse width. 3. 0V RT where RT is in Ohms and IRT is in Amperes. RT can range from 40kΩ to 120kΩ Soft start charging and discharging current are also programmed by IRT . SS/DISB: Soft Start/Disable. This pin combines the two independent functions. Disable Mode: A rapid shutdown of the chip is accomplished by any one of the following: externally forcing SS/DISB below 0.5V, externally forcing REF below 4V, VDD dropping below the UNLO threshold, or an overcurrent fault is sensed (CS = 2.5V). VDD: Power Supply. VDD must be bypassed with a minimum of a 1.0µF low ESR, low ESL capacitor to ground. In the case of REF being pulled below 4V or an UVLO condition, SS/DISB is actively pulled to ground via an internal MOSFET switch. If an overcurrent is sensed, SS/DISB will sink a current of (10 • IRT) until SS/DISB falls below 0.5V. REF: 5V, ±1.2% voltage reference. The reference supplies power to internal circuitry, and can also supply up to 5mA to external loads. The reference is shut down during undervoltage lock-out but is operational during all other disable modes. For best performance, bypass with a 0.1µF low ESR, low ESL capacitor to ground Note that if SS/DISB is externally forced below 0.5V the pin will start to source current equal to IRT. Also note that the only time the part switches into the low IDD current mode is when the part is in undervoltage lockout. 6 UCC1895 UCC2895 UCC3895 BLOCK DIAGRAM IRT RT 8 CT 7 Q 8(IRT) OSC Q R SYNC 15 D S Q Q D S Q 6 R Q DELAY B D S Q DELAY C PWM COMPARATOR RAMP OUTA 9 DELAB 17 OUTB + 3 18 DELAY A VDD 0.8V EAOUT 2 EAP 20 EAN 1 ERROR AMP CURRENT SENSE COMPARATOR 14 NO LOAD COMPARATOR R Q 0.5V/ 0.6V DELAY D 2V CS 12 OVER CURRENT COMPARATOR OUTC 10 DELCD 13 OUTD 16 PGND 11 ADS 4 REF 5 GND ADAPTIVE DELAY SET AMPLIFIER 2.5V 0.5V REF IRT SS HI=ON Q S Q R UVLO COMPARATOR 11V/9V DISABLE COMPARATOR REF 0.5V REFERENCE OK COMPARATOR 19 HI=ON 4V 10(IRT) UDG-98140 7 UCC1895 UCC2895 UCC3895 CIRCUIT DESCRIPTION REF RT VREF RT IRT 8IRT 2.5V CT – S Q CLOCK + CT – + 0.2V CLOCK R SYNC UDG-98141 Figure 1. Oscillator block diagram. REF 0.5V 100K 75K TO DELAY A AND DELAY B BLOCKS + – CS DELAB + 100K ADS – 75K REF + – TO DELAY C AND DELAY D BLOCKS DELCD UDG-98142 Figure 2. Adaptive delay set block diagram. 8 UCC1895 UCC2895 UCC3895 CIRCUIT DESCRIPTION (cont.) BUSSED CURRENT FROM ADS CIRCUIT VREF 3.5V DELAB/CD FROM PAD DELAYED CLOCK SIGNAL 2.5V CLOCK UDG-98143 Figure 3. Delay block diagram (one delay block per output). APPLICATION INFORMATION CLOCK RAMP & COMP PWM SIGNAL OUTPUT A OUTPUT B OUTPUT C OUTPUT D UDG-98138 Figure 4. UCC3895 timing diagram (no output delay shown). 9 UCC1895 UCC2895 UCC3895 TYPICAL CHARACTERISTIC Vcs=0V Vcs=2V RT=47K 1800 1600 1600 1400 FREQUENCY (kHz) OUTPUT DELAY (ns) 2000 1400 1200 1000 800 600 400 RT=82k RT=100k 1200 1000 800 600 400 200 200 0 100 0 0 10 20 RDEL (kΩ) 30 40 Figure 5. Delay programming: characterizes the output delay between A/B, C/D. 1000 CT (pF) Figure 8. Frequency vs. RT/CT (oscillator frequency). Vdd=10V 1 Vdd=12V Vdd=15V Vdd=17V 9 8 0.95 Idd (mA) EAOUT TO RAMP OFFSET (V) RT=62k 0.9 0.85 7 6 5 4 0.8 -60 -40 -20 0 20 40 60 TEMPERATURE (°C) 80 100 0 120 800 1200 1600 OSCILLATOR FREQUENCY (kHz) Figure 6. EAOUT to RAMP offset over temperature. GAIN (dB) 400 Figure 9. Idd vs. Vdd / oscillator frequency (no output loading). Vdd=10V PHASE MARGIN (°C) 100 200 80 160 Vdd=12V Vdd=15V Vdd=17V 13 120 40 80 20 40 0 0 Idd (mA) 60 11 PHASE MARGIN (DEGREES) GAIN (dB) 12 10 9 8 7 6 5 4 1 100 10000 FREQUENCY (Hz) 0 1000000 400 800 1200 OSCILLATOR FREQUENCY (kHz) 1600 Figure 10. Idd vs. Vdd / oscillator frequency (with 0.1nf output loads). Figure 7. Error amplifier gain/phase margin. UNITRODE CORPORATION 7 CONTINENTAL BLVD. • MERRIMACK, NH 03054 TEL. (603) 424-2410 • FAX (603) 424-3460 10 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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