BFU590G ISM 866 MHz PA design

AN11501
BFU590G ISM 866 MHz PA design
Rev. 1 — 16 June 2014
Application note
Document information
Info
Content
Keywords
BFU590G, PA, ISM-band, 433MHz 866MHz
Abstract
This document describes an ISM Frequency PA design on BFU590G
Starter kit
Ordering info
BFU590G Starter kit OM7966, 12nc 9340 678 75598
Contact information
For more information, please visit: http://www.nxp.com
AN11501
NXP Semiconductors
Example PA design using BFU590G
Revision history
Rev
Date
Description
1
20140616
First publication
Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
AN11501
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 16 June 2014
© NXP B.V. 2014. All rights reserved.
2 of 23
AN11501
NXP Semiconductors
Example PA design using BFU590G
1. Abstract
In this application note an ISM band (industrial, scientific and medical) PA design using a BFU590G
transistor from NXP latest wideband transistor range is described. It shows the design, simulation and
implementation phases. Together with measurement results, parameters measured over temperature are
shown.
The application note (AN) can be a starting point for new design(s), and/or derivative designs.
2. Introduction
The BFU500 transistor family is designed to meet the latest requirements on high frequency applications
(up to approximately 2 GHz) such as communication, automotive and industrial equipment.
As soon as fast, low noise analogue up to medium power signal processing is required, combined with
medium to high voltage swings the BFU500 transistors are the perfect choice. Due to the high gain at low
supply current those types can also be applied very well in battery powered equipment.
Compared to previous Philips / NXP transistor generations and competitor products’ improvements on
gain, noise and thermal properties are realized. BFU500 transistors are available in various packages.
The transistors are promoted with a full promotion package, called “starter kits” (one kit type per packagetype). Those kits include two PCB’s (one with grounded emitter, one with emitter degeneration provision),
RF connectors, transistors and simulation model parameters required to perform simulations. See the
overview of available starter kits in the table below.
Table 1.
Customer evaluation kits
Basic type
Customer evaluation kits
1
BFU520W, BFU530W, BFU550W
OM7960, starter kit for transistors in SOT323 package
2
BFU520A, BFU530A, BFU550A
OM7961, starter kit for transistors in SOT23 package
3
BFU520, BFU530, BFU550
OM7962, starter kit for transistors in SOT143 package
4
BFU520X, BFU530X, BFU550X
OM7963, starter kit for transistors in SOT143X package
5
BFU520XR, BFU530XR, BFU550XR
OM7964, starter kit for transistors in SOT143XR package
6
BFU580Q, BFU590Q
OM7965, starter kit for transistors in SOT89 package
7
BFU580G, BFU590G
OM7966, starter kit for transistors in SOT223 package
AN11501
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 16 June 2014
© NXP B.V. 2014. All rights reserved.
3 of 23
AN11501
NXP Semiconductors
Example PA design using BFU590G
Fig 1. BFU590G evaluation boards
3. Requirements
The demonstrator circuit is designed to show the BFU590G capabilities for a 866 MHz ISM PA with strong
focus on best possible efficiency.
The goal of the demonstrator circuit was to design a PA optimized for the ISM band meeting following
requirements:
Supply Voltage:
Quiescent current:
Gain:
P1dB:
Input Return-Loss:
Efficiency:
8 Volts nominal
0 - 10mA at ambient temperature
approx. 10dB
>26dBm
>10dB
>55%
The design is aimed at low BOM cost and small PCB area, inductors are SMD types (preferable low cost
multilayer types) to enable simple tuning to other frequency bands.
4. Design considerations
Power amplifiers are critical components in wireless systems. They consume a substantial percentage of
the total power.
Design goals for a power amplifier can be the following:
•
High output power for given dissipation budget
•
High gain. (having less stages, less material and lower cost)
•
High efficiency (saving energy)
•
Low distortion (having a linear system and reducing unwanted spurious emissions)
•
Good stability (under given circumstances)
AN11501
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 16 June 2014
© NXP B.V. 2014. All rights reserved.
4 of 23
AN11501
NXP Semiconductors
Example PA design using BFU590G
In order to achieve maximum power, high efficiency and Gain (close to the maximum available gain), the
output impedance has to be close to the optimum loadline.
Designing for maximum output power and efficiency, will compromise for example the gain and input
return loss, but this is assumed to be acceptable.
At any time the circuit should be stable, hence during the design phase the K-factor needs to be observed
carefully.
5. Design approach
The design starts in the simulation phase, applying the Mextram Model (available at http://www.nxp.com).
Agilent “Advanced Design System” (ADS) was used for this but other simulation software packages
should give equal results. Spice / Gummel Poon models are also available but may give less reliable
results in nonlinear performance (P1dB, IP3 etc).
Once simulation results meet the requirements, the circuit is built on a universal Printed Circuit Board
(PCB) and evaluated. If measurement results show significant offset from simulated results, fine tuning is
required until required performance is met. To achieve better matching between simulations and
measurements, the PCB parasitic properties have to be added in the simulation template. Basic
knowledge of PA design is assumed, see literature.
Following blocks of passive components can be identified:
1) passives for DC biasing
2) passives set up collector load
3) passives for input matching
4) passives required to ensure stable operation
5.1 Simulation steps
Following simulation / design approach can be useful:
1) Configure the DC bias set-up, ensuring the Icc is set around desired value.
2) Configure the collector load circuit and output matching circuitry, optimizing the output Return
Loss (RL).
3) Check stability on the bench afterwards.
4) Configure the input matching for maximum gain and acceptable input return loss.
5) Check stability on the bench afterwards.
Assumptions:
-
Realistic passives are used by applying Murata design kit (0603/0805)
-
PCB tracks represented by strip-lines
AN11501
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 16 June 2014
© NXP B.V. 2014. All rights reserved.
5 of 23
AN11501
NXP Semiconductors
Example PA design using BFU590G
5.2 Implementation / evaluation steps
Following implementation / evaluation steps have been executed:
1) Implement simulated design on universal PCB.
2) Evaluate PA on output power / efficiency / Gain / matching / Stability at ambient temperature.
3) Fine tune passives if required.
4) In case significant differences between simulations and measured results are observed, add or
modify parasitic properties in the simulation template.
5) Measure PA design on RF parameters over temperature.
5.3 Setting up the DC bias circuit
+Vsupply
Vcontrol
C4
C2
R1
C3
L2
C1
L3
L1
RF transistor
DC bias circuit 1
DC bias circuit 2
Fig 2. Circuitry to set DC bias current
In a class A amplifier, it is custom to stabilize the operating point by means of an emitter and base
resistor. In a RF power amplifier, however, it is preferable to ground the emitter to obtain maximum power
gain.
Circuit 1 shows the basic circuit of the bias circuit of an RF power amplifier. Biasing de-coupling networks
are designed to present high impedance in the RF band and to have a low impedance in the low
frequency band.
Due to proper choice of RF chokes (L1,L2) and bypass capacitors (C1,C2,C3,C4), parasitic oscillations
can occur far below the working frequency. The RF chokes combined with the parasitic feedback
capacitor (Ccb) can result in a Hartley type of oscillator as shown below. In order to avoid oscillation the
inductance values of the chokes should fulfill the condition given in figure 3.
AN11501
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 16 June 2014
© NXP B.V. 2014. All rights reserved.
6 of 23
AN11501
NXP Semiconductors
Example PA design using BFU590G
Fig 3. Avoiding low frequency instability
The formula in figure 3 gives the ratio between the collector coil and base coil to avoid low frequency
instability.
It is good practice to de-couple the supply points with large capacitors (uF range) to eliminate transients
and interactions between other system components on the same supply rail.
To avoid LF instability this should not be inserted at the RF de-coupling points. Instead a LF choke (L2) is
added to isolate the RF and supply de-coupling points shunted by a resistor (R1).
Circuit 2 shows an example of the class-AB bias circuit. It is required to have a constant VBE, a low
output resistance, temperature compensation and low power consumption (efficiency)
The bias circuit shown here has large negative feedback. If the base current of the RF power transistor
increases the output voltage of the bias circuit will decrease slightly causing the collector current of Q1 to
decrease and its collector voltage to increase, counteracting the drop in output voltage.
Q1 should have a VBE level which is lower than that of the RF power transistor. R4 compensates for the
difference between these two values and used to set the bias level.
R1 is incorporated to protect Q2 in case of short circuit in the power transistor.
R2 is a preloading resistor used to reduce the base current variation.
This circuit can develop parasitic oscillation near 1MHz with highly capacitive loads (such as the base
supply bypass capacitors). The series combination C1-R5 can prevent this.
In this AN the circuit on the left has been implemented by using an additional power supply to set the bias
current. The circuit on the right is an example of how a bias circuit can be build up.
5.4 Setting up the Simulation circuit in ADS
The configuration below is used for the simulation by ADS. It’s a basic circuit amplifier available in the
ADS design guide: Amplifier / 1-Tone Nonlinear Simulations / Spectrum, gain, Harmonic Distortion.
AN11501
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 16 June 2014
© NXP B.V. 2014. All rights reserved.
7 of 23
AN11501
NXP Semiconductors
Example PA design using BFU590G
Fig 4. ADS design template for PA design
The circuit shows the possibility to choose any frequency, impedance, power range.
5.5 Setting up the collector load
The design has been concentrated to have maximum 1dB compression at 8V power supply having high
efficiency and gain.
The load impedance is:  =
(Vsupply−Vsaturation)2
2Pout
For 0.5W output power the load impedance should be close to 50 Ohm.
Two ways to calculate efficiency:
Efficiency: ɳ =


Power added Efficiency: ɳ =
In this AN the ɳc will be used.
( − )

= ɳ
1
(1−
1
)

The components C2, L2, C1 and L1 (see figure 4) have been used to tune the maximum 1dB
compression power, efficiency input return loss and gain in the required frequency band of 433MHz. The
bias coil to the base of the transistor was set to 470nH and for the collector was set to 18nH. This ratio
meets the low frequency stability rule see figure 3.
There are tradeoffs to make to meet the 1dB compression target:
•
Output collector coil (to supply): 18nH. Higher value will reduce the efficiency, a lower value will
reduce the gain.
•
Output series inductor: 6.8nH. Higher value will decrease the 1dB compression but will improve
the efficiency
AN11501
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 16 June 2014
© NXP B.V. 2014. All rights reserved.
8 of 23
AN11501
NXP Semiconductors
Example PA design using BFU590G
•
The input inductor (L2) and capacitor (C2) can be set to match the input for gain and input return
loss.
When going one level deeper in the PA design, the transistor template with it’s bias and collector coil is
shown, see figure 5.
Fig 5. ADS design transistor
The circuit below shows the Idc settings of the circuit:
Fig 6. ADS simulation DC biasing
By applying ~0.78V bias at the base of the transistor, the collector current is ~10mA.
AN11501
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 16 June 2014
© NXP B.V. 2014. All rights reserved.
9 of 23
AN11501
NXP Semiconductors
Example PA design using BFU590G
th
Harmonic balance simulation template is used, results to the 5 order are shown below:
Fig 7. ADS simulation for maximum output power, efficiency and gain
The simulation gives a 1dB compression of 28dBm. The gain is 10dB for low output power. The gain
increases slightly to 10.5dB just before reaching the 1dB compression. The harmonic content of the
output signal is also given in the table.
In the graph below the Idc over output power is shown.
Fig 8. ADS simulation over output power
AN11501
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 16 June 2014
© NXP B.V. 2014. All rights reserved.
10 of 23
AN11501
NXP Semiconductors
Example PA design using BFU590G
Fig 9. ADS simulation AM to AM and AM to PM plots
Natural behavior of a class AB circuit is the Idc increase over output power. At 1dB compression (28dBm)
the Idc= 133mA. Dissipated power in that situation is 8x0.133=1.06W which gives an efficiency of 59%.
5.6 Definition of input / source matching circuit
By tuning C2 and L2 the input match and gain can be set, results of the simulation see figure 10.
Fig 10. BFU590G Spar and gain over frequency.
S-parameters and gain over frequency.
AN11501
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 16 June 2014
© NXP B.V. 2014. All rights reserved.
11 of 23
AN11501
NXP Semiconductors
Example PA design using BFU590G
6. Application circuit
The circuit diagram of the evaluation board is shown in Fig 11 PCB schematic.
6.1 BFU590G 866 MHz ISM PA schematic
Vcc 8V
Vbb
22nF
10uF
10R
100pF
470nH
100pF
470nH
18nH
RF input
(SMA)
100pF
100pF
BFU590G
3.3pF 1.5nH
6.8nH
RF output
(SMA)
BFU590G 866MHz
Fig 11. Schematic as implemented for measurements
AN11501
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 16 June 2014
© NXP B.V. 2014. All rights reserved.
12 of 23
AN11501
NXP Semiconductors
Example PA design using BFU590G
6.2 BFU590G 866 MHz ISM PA PCB drawing
10uF NM NM
10R
470nH
100pF
NM
NM 470nH
NM
0R
22nF
100pF
18nH
100pF 0R
3.3pF 1.5nH
100pF
6.8nH
0R
NM
NM
NM
NM
10uF NM NM
Fig 12. PCB implementation for measurements
10R
Remarks:
470nH
0R = SMD jumper
NM = component not mounted.
This layout, as delivered with the Starter kit, accommodates the possibility to implement the biasing as
shown in the ADS schematics.
6.3 PCB properties, layer stack
Fig 13. PCB layers used for Evaluation Boards in Starter kit
AN11501
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 16 June 2014
© NXP B.V. 2014. All rights reserved.
13 of 23
AN11501
NXP Semiconductors
Example PA design using BFU590G
6.4 Typical PA evaluation board results
Table 2. Typical results measured on the evaluation boards
Operating Frequency is f = 866 MHz unless otherwise specified; Temp = 25 °C
Parameter
Symbol
EVB
Unit
Remarks
Supply Voltage
VCC
8
V
Supply Current
ICC
100
mA
Gp
10
dB
Input Return Loss
RLin
-12
dB
Output Power (P1dB)
P1dB
27
dBm
Efficiency
ɳc
55
%
Power Gain
Table 3. Bill Of Materials
Value
BFU590G
100 pF
3.3 pF
100 pF
10 uF
22 nF
100 pF
1.5 nH
470 nH
470 nH
18 nH
6.8 nH
10 Ω
AN11501
Application note
Description
Transistor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Inductor
Resistor
Inductor
Inductor
Inductor
Resistor
Footprint
SOT223
0603
0603
0603
0805
0805
0603
0603
0603
0603
0603
0603
0603
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 16 June 2014
Manufacturer
NXP Semiconductors
Various
Various
Various
Various
Various
Various
Various
Various
Various
Various
Various
Various
© NXP B.V. 2014. All rights reserved.
14 of 23
AN11501
NXP Semiconductors
Example PA design using BFU590G
7. Characterization of PA over temperature and supply voltage
7.1 Gain (S21) = f (freq)
30
|S21|^2
(dB)
25
20
15
10
5
0
600
650
700
750
800
850
900
950
1000
Frequency (MHz)
Vsup = 8.0
3.6 V; Tamb = -40 °C
Tamb = -40 °C
Fig9. Gain
Tamb
= 25 as
°C a function of frequency; typical values
Tamb = 85 °C
Tamb = 125 °C
Fig1. Insertion power gain as a function of frequency; typical
values
Fig 14. Measured S21 over frequency for different temperatures
7.2 Input return-loss (S11) = f (freq)
0
|S11|^2
(dB)
-5
-10
-15
-20
-25
-30
600
650
700
750
800
850
900
950
1000
Frequency (MHz)
Vsup = 8.0
3.6 V; Tamb = -40 °C
Tamb = -40 °C
Fig9. Gain
Tamb
= 25 as
°C a function of frequency; typical values
Tamb = 85 °C
Tamb = 125 °C
Fig2. Input return loss as a function of frequency; typical values
Fig 15. Measured S11 over frequency for different temperatures
AN11501
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 16 June 2014
© NXP B.V. 2014. All rights reserved.
15 of 23
AN11501
NXP Semiconductors
Example PA design using BFU590G
7.3 Output return-loss (S22) = f (freq)
0
|S22|^2
(dB)
-5
-10
-15
-20
-25
-30
600
650
700
750
800
850
900
950
1000
Frequency (MHz)
Vsup = 8.0
3.6 V; Tamb = -40 °C
Tamb = -40 °C
Fig9. Gain
Tamb
= 25 as
°C a function of frequency; typical values
Tamb = 85 °C
Tamb = 125 °C
Fig3. Output return loss as a function of frequency; typical values
Fig 16. Measured S22 over frequency for different temperatures
7.4 Isolation (S12) = f (freq)
-10
|S12|^2
(dB)
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
600
650
700
750
800
850
900
950
1000
Frequency (MHz)
Vsup = 8.0
3.6 V; Tamb = -40 °C
Tamb = -40 °C
Fig9. Gain
Tamb
= 25 as
°C a function of frequency; typical values
Tamb = 85 °C
Tamb = 125 °C
Fig4. Isolation as a function of frequency; typical values
Fig 17. Measured S12 over frequency for different temperatures
All Sparameters measured at low input power (-40dBm)
AN11501
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 16 June 2014
© NXP B.V. 2014. All rights reserved.
16 of 23
AN11501
NXP Semiconductors
Example PA design using BFU590G
7.5 1dB compression and efficiency = f (Tamb)
35
70.0
30
60.0
PL(1dB)
(dBm)
25
50.0
20
40.0
15
30.0
10
20.0
5
10.0
0
efficiency
(%)
0
2
4
6
Vsupply [V]
P1dB
8
10
0.0
Effeciency
Fig 18. Measured P1dB at 8V power supply over temperature
7.6 1dB compression and efficiency = f (Vsupply)
35
70.0
30
60.0
PL(1dB)
(dBm)
25
50.0
20
40.0
15
30.0
10
20.0
5
10.0
0
efficiency
(%)
-50
0
50
100
Tambt (degrC)
P~L(1dB)
150
0.0
Efficiency
Fig 19. Measured 1dB compression point at room temperature over
supply voltage
AN11501
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 16 June 2014
© NXP B.V. 2014. All rights reserved.
17 of 23
AN11501
NXP Semiconductors
Example PA design using BFU590G
7.7 2 tone IMD and Idc = f (Pout) for 3 bias currents
0
90
-10
80
-20
70
IMD [dB]
-30
60
-40
50
-50
40
-60
30
-70
20
-80
10
-90
-5
0
5
IMD (10mA)
10
15
Pout [dBm]
IMD (8mA)
20
IMD (6mA)
25
Idc
[mA]
0
Idc
Fig 20. Measured IMD and Idc for different bias currents over Output Power
AN11501
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 16 June 2014
© NXP B.V. 2014. All rights reserved.
18 of 23
AN11501
NXP Semiconductors
Example PA design using BFU590G
8. Conclusions / recommendations
With the BFU590G transistor a 866 MHz PA design can be implemented with a P1dB of about 27dBm and
having a good efficiency of about 55%. Gain is 10dB. The circuit can be used as a base for derivative
designs, matching to other frequencies can be done by tuning relevant capacitors and inductors.
For improvements on linearity over output level it could be recommended to set the correct DC biasing
current.
This PA can be tuned to other frequencies as well. The presented configuration has been designed for a
small bandwidth application.
For wideband power amplifiers a feedback is recommended which can be implemented on the existing
board.
9. References
BFU590G datasheet
BFU590G starter-kit (OM7966) User Manual, UM10772
AN11501
Application note
© NXP Semiconductors 2014. All rights reserved.
Rev. 1 — 16 June 2014
19 of 23
AN11501
NXP Semiconductors
Example PA design using BFU590G
10. Legal information
10.1 Definitions
Draft — The document is a draft version only. The content is still
under internal review and subject to formal approval, which may
result in modifications or additions. NXP Semiconductors does not
give any representations or warranties as to the accuracy or
completeness of information included herein and shall have no
liability for the consequences of use of such information.
10.2 Disclaimers
Limited warranty and liability — Information in this document is
believed to be accurate and reliable. However, NXP Semiconductors
does not give any representations or warranties, expressed or
implied, as to the accuracy or completeness of such information and
shall have no liability for the consequences of use of such
information. NXP Semiconductors takes no responsibility for the
content in this document if provided by an information source outside
of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect,
incidental, punitive, special or consequential damages (including without limitation - lost profits, lost savings, business interruption,
costs related to the removal or replacement of any products or rework
charges) whether or not such damages are based on tort (including
negligence), warranty, breach of contract or any other legal theory.
Notwithstanding any damages that customer might incur for any
reason whatsoever, NXP Semiconductors’ aggregate and cumulative
liability towards customer for the products described herein shall be
limited in accordance with the Terms and conditions of commercial
sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right
to make changes to information published in this document, including
without limitation specifications and product descriptions, at any time
and without notice. This document supersedes and replaces all
information supplied prior to the publication hereof.
Suitability for use — NXP Semiconductors products are not
designed, authorized or warranted to be suitable for use in life
support, life-critical or safety-critical systems or equipment, nor in
applications where failure or malfunction of an NXP Semiconductors
product can reasonably be expected to result in personal injury, death
or severe property or environmental damage. NXP Semiconductors
and its suppliers accept no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of
these products are for illustrative purposes only. NXP
Semiconductors makes no representation or warranty that such
applications will be suitable for the specified use without further
testing or modification.
Customers are responsible for the design and operation of their
applications and products using NXP Semiconductors products, and
NXP Semiconductors accepts no liability for any assistance with
applications or customer product design. It is customer’s sole
responsibility to determine whether the NXP Semiconductors product
is suitable and fit for the customer’s applications and products
planned, as well as for the planned application and use of customer’s
third party customer(s). Customers should provide appropriate design
and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any
default, damage, costs or problem which is based on any weakness
or default in the customer’s applications or products, or the
application or use by customer’s third party customer(s). Customer is
responsible for doing all necessary testing for the customer’s
applications and products using NXP Semiconductors products in
order to avoid a default of the applications and the products or of the
application or use by customer’s third party customer(s). NXP does
not accept any liability in this respect.
Export control — This document as well as the item(s) described
herein may be subject to export control regulations. Export might
require a prior authorization from national authorities.
Evaluation products — This product is provided on an “as is” and
“with all faults” basis for evaluation purposes only. NXP
Semiconductors, its affiliates and their suppliers expressly disclaim all
warranties, whether express, implied or statutory, including but not
limited to the implied warranties of non-infringement, merchantability
and fitness for a particular purpose. The entire risk as to the quality,
or arising out of the use or performance, of this product remains with
customer.
In no event shall NXP Semiconductors, its affiliates or their suppliers
be liable to customer for any special, indirect, consequential, punitive
or incidental damages (including without limitation damages for loss
of business, business interruption, loss of use, loss of data or
information, and the like) arising out the use of or inability to use the
product, whether or not based on tort (including negligence), strict
liability, breach of contract, breach of warranty or any other theory,
even if advised of the possibility of such damages.
Notwithstanding any damages that customer might incur for any
reason whatsoever (including without limitation, all damages
referenced above and all direct or general damages), the entire
liability of NXP Semiconductors, its affiliates and their suppliers and
customer’s exclusive remedy for all of the foregoing shall be limited to
actual damages incurred by customer based on reasonable reliance
up to the greater of the amount actually paid by customer for the
product or five dollars (US$5.00). The foregoing limitations,
exclusions and disclaimers shall apply to the maximum extent
permitted by applicable law, even if any remedy fails of its essential
purpose.
10.3 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are property of their respective owners.
AN11501
Application note
© NXP Semiconductors 2014. All rights reserved.
Rev. 1 — 16 June 2014
20 of 23
AN11501
NXP Semiconductors
Example PA design using BFU590G
11. List of figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10.
Fig 11.
Fig 12.
Fig 13.
Fig 14.
Fig 15.
Fig 16.
Fig 17.
Fig 18.
Fig 19.
Fig 20.
BFU590G evaluation boards .............................4
Circuitry to set DC bias current .........................6
Avoiding low frequency instability......................7
ADS design template for PA design ..................8
ADS design transistor .......................................9
ADS simulation DC biasing ...............................9
ADS simulation for maximum output power,
efficiency and gain .......................................... 10
ADS simulation over output power .................. 10
ADS simulation AM to AM and AM to PM plots11
BFU590G Spar and gain over frequency. ....... 11
Schematic as implemented for measurements12
PCB implementation for measurements .......... 13
PCB layers used for Evaluation Boards in Starter kit
........................................................................ 13
Measured S21 over frequency for different
temperatures ................................................... 15
Measured S11 over frequency for different
temperatures ................................................... 15
Measured S22 over frequency for different
temperatures ................................................... 16
Measured S12 over frequency for different
temperatures ................................................... 16
Measured P1dB at 8V power supply over
temperature ..................................................... 17
Measured 1dB compression point at room
temperature over supply voltage ..................... 17
Measured IMD and Idc for different bias currents
over Output Power .......................................... 18
AN11501
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 16 June 2014
© NXP B.V. 2014. All rights reserved.
21 of 23
AN11501
NXP Semiconductors
Example PA design using BFU590G
12. List of tables
Table 1.
Table 2.
Table 3.
Customer evaluation kits ...................................3
Typical results measured on the evaluation boards
........................................................................ 14
Bill Of Materials ............................................... 14
AN11501
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 16 June 2014
© NXP B.V. 2014. All rights reserved.
22 of 23
AN11501
NXP Semiconductors
Example PA design using BFU590G
13. Contents
1.
2.
3.
4.
5.
5.1
5.2
5.3
5.4
5.5
5.6
6.
6.1
6.2
6.3
6.4
7.
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8.
9.
10.
10.1
10.2
10.3
11.
12.
13.
Abstract ................................................................3
Introduction..........................................................3
Requirements.......................................................4
Design considerations ........................................4
Design approach .................................................5
Simulation steps .................................................5
Implementation / evaluation steps ......................6
Setting up the DC bias circuit .............................6
Setting up the Simulation circuit in ADS .............7
Setting up the collector load ...............................8
Definition of input / source matching circuit ...... 11
Application circuit ............................................. 12
BFU590G 866 MHz ISM PA schematic ............ 12
BFU590G 866 MHz ISM PA PCB drawing ....... 13
PCB properties, layer stack .............................. 13
Typical PA evaluation board results ................. 14
Characterization of PA over temperature and
supply voltage ................................................... 15
Gain (S21) = f (freq) ......................................... 15
Input return-loss (S11) = f (freq) ....................... 15
Output return-loss (S22) = f (freq) .................... 16
Isolation (S12) = f (freq).................................... 16
1dB compression and efficiency = f (Tamb) ..... 17
1dB compression and efficiency = f (Vsupply).. 17
2 tone IMD and Idc = f (Pout) for 3 bias currents18
Conclusions / recommendations ..................... 19
References ......................................................... 19
Legal information .............................................. 20
Definitions......................................................... 20
Disclaimers ....................................................... 20
Trademarks ...................................................... 20
List of figures ..................................................... 21
List of tables ...................................................... 22
Contents ............................................................. 23
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in the section 'Legal information'.
© NXP B.V. 2014.
All rights reserved.
For more information, visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 16 June 2014
Document identifier: AN11501
Similar pages