cd00245238

AN3031
Application note
SCLT3-8 input termination demonstration board
STEVAL-IFP007V1
1
Introduction
The SCLT3-8BT8 is an eight channel termination used for interfacing automation digital
inputs. It is designed for 24 VDC applications and meets type 3 input characteristics in
accordance with IEC 61131-2 (programmable controllers international standard). The chip
integrates an SPI peripheral output for communication with logic/ASIC/microcontroller. Its
structure allows the transfer not only of the data but also of additional information including
thermal alarm, undervoltage indication and parity bits. It is particularly beneficial for
applications with high channel counts. The serial communication allows for reduction of the
number of lines, which in most applications need to be galvanically isolated.
The device optimizes the input VI characteristic shape to reduce power dissipation. This
becomes critical when the application enclosure requires higher protection levels, such as
IP codes IP65 and IP67. These closed cabinets are used in various automated lines,
including the food industry. The power dissipated inside the module is very limited, as there
is usually no air circulation inside the box. The current limitation also reduces power losses
on the sensor side.
Another important parameter is electrical protection and susceptibility of the application.
The SCLT3-8BT8 implements large protection diodes on each input and supply voltage line.
Serial resistors ensure a higher level of susceptibility than required.
Thanks to its compact package, an SCLT3-8BT8 application occupies little space on the
PCB compared to discrete solutions.
Figure 1.
October 2009
STEVAL-IFP007V1 demonstration board
Doc ID 16144 Rev 1
1/28
www.st.com
Contents
AN3031
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
2.1
SCLT3-8BT8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2
STEVAL-IFP007V1 demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Demonstration board PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1
EMC optimal PCB considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2
PCB layer set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4
SPI communication speed calculation . . . . . . . . . . . . . . . . . . . . . . . . . 18
5
Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6
EMC requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1
Procedure to evaluate the robustness of the SCLT3-8BT8 . . . . . . . . . . . 23
6.2
ESD tests (according to IEC 61000-4-2) . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.3
Burst tests (according to IEC 61000-4-4) . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.4
Surge test (according to IEC 61000-4-5) . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.5
Conducted disturbance tests (according to the IEC 61000-4-6) . . . . . . . 24
6.6
Reverse analog input polarity tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7
EMC testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2/28
Doc ID 16144 Rev 1
AN3031
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
EMC immunity test requirements and results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Doc ID16144 Rev 1
3/28
List of figures
AN3031
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
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STEVAL-IFP007V1 demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SCLT3-8BT8 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SCLT3-8BT8 recommended application structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Application connection diagram - part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Application connection diagram - part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Application connection diagram - part 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Demonstration board photo - top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Demonstration board photo - bottom view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Top layer PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Top inner layer PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Bottom inner layer PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Bottom layer PCB layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Top overlay PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Bottom overlay PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Total propagation delay waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Signal conventions / protection structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Doc ID 16144 Rev 1
AN3031
2
Description
Description
The STEVAL-IFP07V1 demonstration board is an application intended to allow designers to
evaluate the behavior of the SCLT3-8BT8 device in industrial environmental conditions. The
board accommodates two SCLT3-8BT8 chips connected to the SPI bus in a daisy chain
configuration. It offers a 16-bit digital input interface and indicates each sensor logic state
with an LED.
Features
■
8/16 input channel topology (SCLT3-8BT8 chip / STEVAL-IFP007V1 board)
■
Fully integrated current limiter
■
Termination for IEC 61131-2 type 1 and 3 inputs
■
Digital filter on each input
■
SPI communication peripheral
■
Voltage regulator integrated on the chip
■
Thermal alarm
■
Wide range supply voltage operation
Benefits
■
Low power dissipation compared to discrete solutions
■
Small external component count
■
Overvoltage protection
■
ESD in accordance with IEC 61000-4-2, class 3, 8 kV air discharge, 6 kV contact
discharge
■
Excellent EMC immunity
– High energy surge (IEC 61000-4-5), 2 kV / criteria “B” (42 Ω / 0.5 µF) without any
Transil™ protection
– Fast transient burst (IEC 61000-4-4), +4 kV / –8 kV (±8 kV(a)) / criteria “A”
– RF amplitude modulation (IEC 61000-4-6), 150 kHz - 80 MHz, 10 V / criteria “A”
■
Cost-effective isolation thanks to an SPI bus
■
Reduces overall dissipation
■
Compact module HTSSOP-38 package
a. With 10 pF capacitive GND coupling (primary vs. secondary ground of the isolation).
Doc ID 16144 Rev 1
5/28
Description
2.1
AN3031
SCLT3-8BT8
The SCLT3-8BT8 (current limited termination) is an eight-channel digital input termination
device designed for 24 VDC automation applications. Typical applications for this device
include PLCs (programmable logic controllers), PACs (programmable automation
controllers), distributed I/O systems, etc. The device works as an interface for mechanical
switches, relay contacts and two-wire or three-wire digital sensors (also known as proximity
switches).
Available in eight-channel configuration, it offers a high-density termination by minimizing
the external component count. It is housed in a HTSSOP-38 surface mount package to
reduce the printed circuit board size.
The chip consists of a parallel input voltage protection circuit, a current limiting circuit which
regulates the channel current and feeds the indicator LEDs, a digital filter to prevent glitches,
a voltage regulator and SPI communication peripheral.
The SCLT3-8BT8 device is connected between the sensors and the application
microcontroller, FPGA or ASIC. The current limiting circuit is compensated over the entire
temperature range. Thanks to its low tolerance, the current limitation allows drastic reduction
of dissipation compared to a resistive input (discrete solution) - the overall module requires
less cooling capability and is smaller.
Thanks to integrated SPI communication, the solution reduces the number of lines which
typically need to be galvanically isolated, making the application more cost-effective. In a
16-bit input interface, conventional solutions require 16 isolators to decouple the control part
from an industrial environment. With the SCLT3-8BT8, the two-chip solution (16-bit
interface) connected in a daisy chain configuration requires only 3 isolators. In addition to
the input data, it also provides device status information including thermal alarm,
undervoltage indication, and others. Parity check bits for higher reliability are also included
in the frame extension.
The SCLT3-8BT8 device principal block diagram and recommended application structure is
provided in Figure 2 and Figure 3.
6/28
Doc ID 16144 Rev 1
AN3031
Description
Figure 2.
IN1
SCLT3-8BT8 block diagram
VDD
Protected input
MISO
VR
LD1
VIN > VR
8 lines
Input
state
register
8 lines
Data
shift
register
MISO
VDD
Write
COMP
INI
0.2 /
3 ms
ditigal
filters
Protected
inputs
I = 2 to 8
Capture
MOSI
8 lines
SCK
Transfer
logic
CS
Shift
SPM
16-bit
Parity
bits
gen.
REF
COMS
MOSI
Shift
7 lines
LDI
VDD
4 lines
Control
shift
register
Current
reference
VC
Power
reset
Power
supply
VDD
OSC
Oscillator
DVR
Overtemperature
alarm
VCS
Undervoltage
alarm
AM00621
Figure 3.
SCLT3-8BT8 recommended application structure
RS
VCS
RPD
UVA
Supply
VC
COMS
RC
COMP
RI
SCK
IN1
CPHA = 0
CLT
CPOL = 0
type 3
SPI
8 channels
O -C
Field bus
CS
O -C
controller
MISO
O -C
MISO
IN8
RREF
VDD
8 / 16 -bit
-
REF
MOSI
SPM
SCLT3-8
LD1
LD8
DVR
OSC
AM00622
Doc ID 16144 Rev 1
7/28
Description
2.2
AN3031
STEVAL-IFP007V1 demonstration board
The STEVAL-IFP007V1 connection diagram is provided in Figure 4, 5 and 6. It is compliant
with type 1 and 3 input characteristics in accordance with the IEC 61131-2 standard. The
application is typically supplied from two sides using two independent power supplies primary and secondary. The primary power supply has a typical voltage of 24 VDC
(functional range from 16 to 35 VDC), and is connected to the CN9 terminal. The secondary
supply is connected through the CN10 (SPI) socket. This supply voltage level derives from
the microcontroller or control logic supply voltage. It is considered within range from 3 VDC
up to 5 VDC. For immunity considerations, the board design is optimized for 5 V signal
levels. If interconnection of the board with 3 V or 3.3 V logic is required, resistors R48, R49,
R59 and R60 should be replaced by a value of approximately 160 Ω.
Special attention should be given top the input and supply line resistors (RI, RC). Their type
dramatically influences the application’s EMC - high voltage surge robustness (IEC 610004-5). The resistors should be capable of sustaining high peak voltage and current levels. A
suitable type is, for example, the MELF MMB0207 from VISHAY®. Peak ratings of such
resistors are 70 W, or 3 kV. Standard SMD 1206 resistors are not recommended, as their
rating are much lower. Therefore, the application fails at surge levels close to 1 kV
(differential mode, 42 Ω / 0.5 µF coupling).
Each SCLT3-8BT8 input signal is additionally filtered with a capacitor of 1 nF. These
components increase capacitive coupling to the GND reference and therefore maximize
EFT immunity. The capacitor values can be increased to 22 nF, for example, to achieve even
higher immunity levels, but with the drawback of bandwidth limitation.
Each SPI signal (CS, SCK, and MOSI) is filtered close to each SCLT3-8BT8 chip with an
integration R-C cell which limits the bandwidth to suppress noise sensitivity. Values used in
the application are 220 Ω - 100 pF, which correspond to the maximum communication baud
rate of approximately 3 Mbps. It is up to the application designer to set the appropriate R-C
values in order to suppress high frequency noise. Naturally, increasing the capacitor values
renders the signals more stable, which has a positive effect on the immunity, but the
communication bandwidth is lower.
8/28
Doc ID 16144 Rev 1
3
1
3
Doc ID 16144 Rev 1
3
1
ST70 2x2
Input 12
Input 13 2
Input 14
Input 15 4
ST70 2x2
CN4
3
1
ST70 2x2
CN3
4
2
1
ST70 2x2
CN2
4
2
Input 8
Input 9 2
Input 10
Input 11 4
Input 4
Input 5
Input 6
Input 7
Input 0
Input 1
Input 2
Input 3
R17
R18
R20
R21
R13
R14
R15
R16
R8
R10
R11
R12
R1
R3
R4
R5
2.2 kΩ
2.2 kΩ
2.2 kΩ
2.2 kΩ
2.2 kΩ
2.2 kΩ
2.2 kΩ
2.2 kΩ
2.2 kΩ
2.2 kΩ
2.2 kΩ
2.2 kΩ
2.2 kΩ
2.2 kΩ
2.2 kΩ
2.2 kΩ
C44
C45
C46
C47
C40
C41
C42
C43
IN12 C52
IN13 C53
IN14 C54
IN15 C55
IN8 C48
IN9 C49
IN10 C50
IN11 C51
IN4
IN5
IN6
IN7
IN0
IN1
IN2
IN3
1 nF
1 nF
1 nF
1 nF
1 nF
1 nF
1 nF
1 nF
1 nF
1 nF
1 nF
1 nF
1 nF
1 nF
1 nF
1 nF
GND
IN4
IN5
IN6
IN7
GND
VC_U1
VCS
SPM
IN0
IN1
C4
IN2
33 nF IN3
SGND
1 kΩ
VCC R6
SGND
51 kΩ
R2
DVR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
39
COMp
C19
100 pF
R52 220 Ω
C20
100 pF
R53 220 Ω
SGND
nCS_SCLT1
NC
NC
CS
SCK
MOSI
MI SO
MI SO
COMs
REF
NC
LD1
LD2
LD3
LD4
LD5
LD6
LD7
LD8
VDD
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
SGND
C1
33 nF
LED6
LED4
LED2
LED0
SD_0
nCS_OPT
LED7
LED5
LED3
LED1
R7
VDD
AM00617
SGND
15 kΩ
R50 22 Ω
nCS_SCLT1
SCK_SCLT1
SCK_OPT
SCLT3-8BT8
SGND
SCK_SCLT 1
DVR
OSC
SPM
COMp
VC
VCS
COMp
IN1
IN2
IN3
IN4
COMp
IN5
IN6
IN7
IN8
COMp
NC
NC
U1
LSB
Figure 4.
CN1
SPI_SLAVE
AN3031
Description
Application connection diagram - part 1
9/28
Description
Figure 5.
AN3031
Application connection diagram - part 2
SPI_MASTER to be connected
VDD
CN10
MI CRO_VCC
C13
10 µF / 6.3 V
nCS_uC
MI CRO_GND
SGND
VDD
1
3
5
7
9
11
13
15
17
19
C14
10 µF / 6.3 V
U5
MI CRO_VCC
8
VDD
SCK_OPT
A1
1
R48 330 Ω CLK_uC
2
R59 330 Ω
3
R49 330 Ω
4
R60 330 Ω
7
Vo1
CLK_uC
MI SO_uC
MLW 20G
MI CRO_GND
C1
C2
nCS_OPT
2
4
6
8
10
12
14
16
18
20
6
C2 Vo2
100 nF
5
GND
MI CRO_GND
nCS_uC
A2
Shield
ACPL-K73L
SGND
SCK
CLK_uC
1
MISO_SCLT
R57 330 Ω
MICRO_VCC
U6
1 A
Test point
6
VDD
CS
nCS_uC
2
NC
R58 330 Ω
Vo
Shield
3
C
SGND
5
MISO_uC
4
C25
100 nF
GND
ACPL-W70L
MI CRO_GND
1
Test point
MI SO
MI SO_uC
1
Test point
GND_MICRO
MI CRO_GND
1
Test point
Isolation barrier
AM00618
10/28
Doc ID 16144 Rev 1
1
2
Doc ID 16144 Rev 1
GND
VCC
GND_PWR
Test point
1
51 kΩ
C6
33 nF
SGND
1 kΩ
R22
SGND
R19
IN12
IN13
IN14
IN15
IN8
IN9
IN10
IN11
GND
VC_U2
VCS
SPM
DVR
R43
DVR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
39
SGND
VDD
NC
NC
CS
SCK
MOSI
MI SO
MI SO
COMs
REF
NC
LD1
LD2
LD3
LD4
LD5
LD6
LD7
LD8
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
SGND
JMP2
VDD4
SCLT3-8BT8
SPM
COMp
JMP1
VDD4
DVR
OSC
SPM
COMp
VC
VCS
COMp
IN1
IN2
IN3
IN4
COMp
IN5
IN6
IN7
IN8
COMp
NC
NC
U2
VCS
R44
120 kΩ
SGND
1.5 MΩ
GND SGND
VCC
SGND
C18
33 nF
LED14
LED12
LED10
LED8
LED15
LED13
LED11
LED9
R24
MISO_SCLT
VDD
SGND
15 kΩ
R51 22 Ω
nCS_SCLT2
SCK_SCLT2
SD_0f
VDD4
C22
100 pF
R55 220 Ω
SGND
C23
100 pF
R56 220 Ω
SGND
nCS_SCLT2
SD_0f
C21
100 pF
R54 220 Ω
SGND
SCK_SCLT2
AM00619
SD_0
nCS_OPT
SCK_OPT
Figure 6.
ST04 2-pin
CN9
AN3031
Description
Application connection diagram - part 3
11/28
Description
Table 1.
AN3031
Bill of material
Designator
Qty
Comment
Description
Footprint
C1, C4, C6, C18
4
33 nF
Ceramic capacitor
SMD 0805
C2, C25
2
100 nF
Ceramic capacitor
SMD 0805
C13, C14
2
10 µF / 6.3 V
Tantalum capacitor
SMD 1210
C19, C20, C21, C22, C23
5
100 pF
Ceramic capacitor
SMD 0805
C40, C41, C42, C43, C44, C45,
C46, C47, C48, C49, C50, C51,
C52, C53, C54, C55
16
1 nF
Ceramic capacitor
SMD 1206
CN1, CN2, CN3, CN4
4
MDSTB 2,5/ 2-G-5,08
Terminal block - Phoenix
Contact
THT
CN1_Plug, CN2_Plug, CN3_Plug,
CN4_Plug
4
MSTB 2,5/ 4-ST-5,08
Terminal block - Phoenix
Contact
THT
CN9
1
MSTB 2,5/ 2-G-5,08
Terminal block - Phoenix
Contact
THT
CN9_Plug
1
MSTB 2,5/ 2-ST-5,08
Terminal block - Phoenix
Contact
THT
CN10
1
MLW20G
Header, 10-pin, dual row,
with key
THT
CS, GND_MICRO, GND_PWR,
MISO, SCK
5
Test point
Header, 1-pin
THT
JMP1, JMP2
2
Header
Header 2-pins / 2.54 mm for
jumper
THT
JMP1_Socket, JMP2_Socket
2
Jumper
Jumper 2.54 mm
THT
LED0, LED1, LED2, LED3, LED4,
LED5, LED6, LED7, LED8, LED9,
LED10, LED11, LED12, LED13,
LED14, LED15
16
LED SMD
Green LED
SMD 0805
R1, R3, R4, R5, R8, R10, R11,
R12, R13, R14, R15, R16, R17,
R18, R20, R21
16
2.2 kΩ
Resistor - high peak power
SMD MELF 0207
R2, R19
2
51 kΩ
Resistor
SMD 0805
R6, R22
2
1 kΩ
Resistor - high peak power
SMD MELF 0207
R7, R24
2
15 kΩ
Resistor
SMD 0805
R43
1
1.5 MΩ
Resistor - high peak power
SMD MELF 0207
R44
1
120 kΩ
Resistor - high peak power
SMD MELF 0207
R48, R49, R57, R58, R59, R60
6
330 Ω
Resistor
SMD 0805
R52, R53, R54, R55, R56
5
220 Ω
Resistor
SMD 0805
R50, R51
2
22 Ω
Resistor
SMD 0805
U1, U2
2
SCLT3-8BT8
Digital input termination
SMD HTSSOP 38
U5
1
ACPL-K73L
Optocoupler
SMD SO8-wide
U6
1
ACPL-W70L
Optocoupler
SMD SO6-wide
12/28
Doc ID 16144 Rev 1
AN3031
Description
Figure 7.
Demonstration board photo - top view
Figure 8.
Demonstration board photo - bottom view
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Demonstration board PCB layout
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3
Demonstration board PCB layout
3.1
EMC optimal PCB considerations
The following section provides basic instructions on how to implement an EMC optimized
PCB layout.
It is necessary to filter the SPI signals close to each SCLT3-8BT8 chip to prevent noise
spikes that trigger the SCK, CS or influence the data line. Single integration R-C cells are
sufficient. The R-C values should be chosen according to the requested baud rate. For
example, given a 220 Ω resistor and a ceramic capacitor with a value of:
a)
100 pF
b)
220 pF
c)
470 pF
the corresponding maximum communication frequency in the STEVAL-IFP007V1
application structure is:
a)
3 MHz
b)
1.6 MHz
c)
870 kHz
The route length should be minimized.
The path between the input signal terminals through input resistors to the filtering capacitors
should also be as short as possible. The SCLT3-8BT8 also embeds digital filters to reduce
accidental pulses (or “glitches”) entering the input lines. The use of capacitive filters is
recommended in addition to improve overall application EMC immunity.
The main reason is to establish a capacitive coupling between the input signals and GND
(which is a reference for all the application signals on the primary side).
Practical experience with several PCB design revisions has shown that application immunity
is substantially influenced by routing shape and the copper pours. Extending the board to
four routing layers improved EMC performance. The outer (top and bottom) layers are used
for signal routing. Moreover, they use copper pours surrounding the primary (SCLT) and
secondary (microcontroller) part. The inner layers are used to distribute GND, VCC and
VREG potentials. The layouts of the different layers are shown in Figures 9 to 12.
The consequence of such a structure is maximized capacitive coupling between all the
signals vs. GND reference. Therefore, all noise influencing any signal (input, supply voltage)
is eliminated and has a common mode effect.
An empty isolation space (without routes, copper areas and components) is implemented
between the primary and secondary application parts. Due to the isolator (optocoupler)
sensitivity on fast common mode transitions, both application sections could be additionally
coupled with high voltage ceramic capacitors. This increases overall application robustness.
EMC tests show immunity increases when a 10 pF capacitor has been placed between
SGND and MICRO_GND.
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3.2
Demonstration board PCB layout
PCB layer set
Figure 9.
Top layer PCB layout
Figure 10. Top inner layer PCB layout
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Demonstration board PCB layout
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Figure 11. Bottom inner layer PCB layout
Figure 12. Bottom layer PCB layout
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Demonstration board PCB layout
Figure 13. Top overlay PCB layout
Figure 14. Bottom overlay PCB layout
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SPI communication speed calculation
4
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SPI communication speed calculation
The chips are connected in cascade (daisy chain) decoupled from the control unit by highspeed low power optocouplers. SPI signals are filtered by RC cells (Rf = 220, Cf = 100 pF)
placed close to each SCLT3-8BT8 and microcontroller SPI inputs. The signal filtering
implementation reduces the communication bandwidth of the SPI bus.
Using the following simple equations, we can estimate the upper limit of the communication
frequency:
Equation 1
T CLKMIN
----------------------- – t su = t ptot
2
then
Equation 2
T C LKMI N = 2 × ( tptot + t su )
and
Equation 3
1
f CLKMAX = ----------------------T C LKMI N
where: tsu is the data setup time of the microcontroller
(for ST 32-bit microcontrollers like the STM32x, it is 5 ns)
tptot is the total propagation delay which is a sum of the propagation delays on the
SPI - CLK and MISO lines and write out propagation time (influenced by the
galvanic isolator, RC filtering cells and SCLT3-8BT8 chip)
The total propagation delay measured on the application is visible in the figure below; its
value is approximately 160 ns. The maximum communication frequency, considering tsu
(data setup time of an SPI master) as 5 ns, is then:
Equation 4
T CLKMIN – application = 2 × ( tptot + t su ) = 2 × ( 160ns + 5ns ) = 330ns
Equation 5
1 1 - = ---------------≅ 3MHz
f CLKMAX – application = ---------------------330ns
T CLKMIN
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SPI communication speed calculation
Figure 15. Total propagation delay waveform
1. Red: clock signal measured on the microcontroller.
2. Blue: MISO data measured on the microcontroller.
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Thermal management
5
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Thermal management
The SCLT3-8BT8 device limits the current that flows in each input pin. Together with a
voltage drop on each input pin versus GND, it also creates power dissipation. Another
contribution is power dissipation coming from the supply voltage pin. The sum of both of
these portions causes an increase in the junction temperature. The maximum allowed
junction temperature of the SCLT3-8BT8 is 150 °C. The HTSSOP38 package with a given
PCB surface has a thermal resistance (junction-to-ambient) of 80 °C / W, as specified in the
device datasheet. This parameter allows the determination of the maximum ambient
temperature during device operation. The ambient temperature to take into account is the
air temperature near the component.
The main equation corresponds to the following:
Equation 6
ΔTJ-A = TJ – TA = PD RthJA
where:
●
TJ is the junction temperature,
●
TA is the ambient temperature,
●
PD: is the power dissipation,
●
RthJA is the thermal resistance junction-ambient.
This paragraph presents the method to evaluate the dissipated power.
Figure 16. Signal conventions / protection structure
IC
Supply
voltage I
IN
Input
SCLT3 –8
VC
RC
RI
CC
VDD
IN1
…
VCC
VI
CI
VIN
IDD
VC
IIN
VF
LD1
…
COMP
VDD
Load
COMS
AM00620
The maximum ambient temperature determines the maximum allowed ΔTJ-A. To estimate
the maximum power dissipation, refer to the parameter of the datasheet that gives the
maximum specification of the current limitation. The purpose is to add all “thermal supplies”
inside the die. There are 2 main sources of power dissipation: the current limiters embedded
in each line of the SCLT3-8BT8 device and the current consumption of the VC pin (IC).
Current consumption of the VC pin depends on the load of the embedded linear voltage
regulator. Then, the maximum power dissipation can be estimated as follows:
Equation 7
P = 8 x [(VIN – VF) x IIN] + VC x IC - VDD x IDD
As shown in Equation 7 we must subtract the power dissipated by the indicator LEDs and
voltage regulator load.
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Thermal management
Considering the above application structure and the following conditions:
●
VCC = 30 V
●
VI_MAX = 30 V
●
IIN_MAX = 2.7 mA
●
VIN_MAX = 24 V
●
fCLK = 1.3 MHz
●
IC = 6 mA
●
VC = 24 V
●
VF = 1.9 V
●
VDD = 5 V
●
ID = 4.5 mA
●
RC = 1 kΩ
●
RI = 2.2 kΩ
the overall chip power dissipation is:
Equation 8
PD = 8 x [(VIN – VF) x IIN] + VC x IC – VDD x IDD = 8 x [(24V – 1.9V) x 2.7mA] + 24V x 6mA – 5V x 4.5 A = 599mW
In case of a maximum allowed ambient temperature equal to 100 °C, the thermal resistance
must be lower than:
Equation 9
ΔT J – A
C – 100° C = 83° C ⁄ W
-----------------------------------------R THJAMAX = ----------------- = 150°
0.599W
PD
Since the application RTH value of the HTSSOP38 is 80 °C/W, the SCLT3-8BT8 works
correctly at this ambient temperature.
In the final application we must consider other cases also. One example is spurious
connection of one channel to negative voltage.
In this negative biasing of the input, the current (IREV) flows through the protection diode.
The voltage (VREV) is then equal to the forward voltage of the protection diode, which is
approximately 0.7 V at 16 mA.
All of the other inputs work correctly.
The total power dissipation in this case can be calculated by with the equation:
Equation 10
V CC – V R EV
30 – 0.7V
I REV = ------------------------------= ------------------------- = 13mA
2200Ω
R IN
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Thermal management
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and
Equation 11
P = 7 x [(VIN – VF) x IIN] + VC x IC – VDD x IDD + VREV x IREV = 7 x [(24 V-1.9 V) x 2.7 mA]
+ 24 V x 6 mA – 5 V x 4.5 mA + 0.7 V x 13 mA = 548 mW
If we consider the same conditions as those above, maximum ambient temperature of 100
°C, we must achieve a thermal resistance lower than 91 °C / W. The SCLT3-8BT8 works
correctly at these conditions. Connecting the input in reverse polarity conditions, the total
power dissipation decreases. It allows biasing of all the SCLT3-8BT8 inputs by reverse
polarity current without risk of component damage.
Special care must be taken on the serial resistor ratings. During normal operation/worstcase conditions, the power ratings of the serial resistors are:
●
16 mW for input serial resistors (RIN)
●
36 mW for supply serial resistor (RC)
During a reverse polarity connection at 25 °C, the resistors must be able to dissipate:
372 mW - input serial resistors (RIN)
858 mW - supply serial resistor (RC)
To increase the reliability of the resistors, considering long-term reverse polarity, the
following options are suggested:
1.
Parallel connection of two (or more) resistors
2.
Use of high power-rating resistors
3.
Reverse polarity diode connection in series with RC resistor
At point 3 above, it is important to either choose the diode with a VR rating higher than the
required surge immunity voltage (e.g. 1 or 2 kV), or to use additional Transil™ protection
(bidirectional) at the application supply voltage terminal (e.g. SM15T36CA).
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EMC requirements
6
EMC requirements
6.1
Procedure to evaluate the robustness of the SCLT3-8BT8
The reference for evaluating the robustness of the SCLT3-8BT8 device is the IEC 61131-2
international standard. This international standard provides all requirements and test
conditions applicable to programmable logic controllers (PLCs) and their associated
peripherals.
The IEC 61131-2 standard specifies the electromagnetic compatibility (EMC) requirements
and the nature of the tests to perform in to determine if the system meets these
requirements. The levels of each test depend on the zone where the system will be installed.
The most typical industrial environmental levels correspond to zone B: local power
distribution zone and dedicated power distribution zone (see table 28: “EMC immunity
zones” of the IEC 61131-2-Ed2 standard). The following paragraphs recall the test levels for
this zone.
6.2
ESD tests (according to IEC 61000-4-2)
The electrostatic discharge test shall be applied to operator accessible devices. This means
that these tests have to be performed on each connector pin. The required levels are: air
discharge: ±8 kV contact discharge: ±4 kV.
The PLC system shall continue to operate as intended. Temporary degradation of the
performance is acceptable during the test, but the system must recover by itself after the
test (criteria “B” according to the IEC61131-2 standard).
6.3
Burst tests (according to IEC 61000-4-4)
The fast transient burst tests must be applied on all input pins of the system. A capacitive
clamp-coupling device (50-200 pF) must be used as described in the IEC 61000-4-4
standard. The required burst voltage levels are: analog or DC I/O: ±1 kV, DC power line: ±2
kV. The PLC system shall continue to operate as intended. Temporary degradation of the
performance is acceptable during the test, but the system must recover by itself after the
test (criteria “B” according to the IEC 61131-2 standard).
6.4
Surge test (according to IEC 61000-4-5)
Since the voltage surge consists of a single but energetic pulse, the SCLT3-8BT8 device
embeds an overvoltage protection on each point. The absorbed energy complies at least
with the requirements of the IEC 61131-2 standard. The high energy surge test must be
applied on all input pins of the system. For all analog inputs, the coupling method is a 42 Ω
serial resistor and a 0.5 µF capacitor. For DC power line, the coupling is 2 Ω, 18 µF with
differential mode, and 12 Ω, 9 µF with common mode. The required voltage surge levels are:
analog or DC I/O: 0.5 kV (line-to-line and line-to-earth coupling modes), DC power line: 0.5
kV (line-to-line), DC power line: 1 kV (line-to-earth). The PLC system shall continue to
operate as intended. Temporary degradation of the performance is acceptable during the
test, but the system must recover by itself after the test (criteria “B” according to the IEC
61131-2 standard).
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EMC requirements
6.5
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Conducted disturbance tests
(according to the IEC 61000-4-6)
The conducted radio frequency interference test must be applied on all input pins of the
system. The frequency range is 150 kHz to 80 MHz, with 80% amplitude modulation of a 1
kHz sinusoidal wave. A CDN (coupling/decoupling network) or a current coupling clamp (as
described in the IEC 61000-4-6 standard) must be used to apply stress to the system. The
required level is: 3 VRMS, whatever the tested system input is. The PLC system shall
continue to operate as intended. No loss of function or performance is acceptable (criteria
“A” according to the IEC 61131-2 standard).
6.6
Reverse analog input polarity tests
The test procedure is described in the IEC 61131-2 standard (paragraph 5.4.4.5 of Ed2 of
the standard). A signal of reverse polarity (negative voltage) for unipolar analog inputs is
applied for 10s. The result of this test shall be as stated by the manufacturer. Each input of
the SCLT3-8BT8 device may be biased to a reverse polarity. This case corresponds to a
connection mistake, or a reverse biasing that is generated by the demagnetization of a
monitored inductive solenoid. The input involved withstands the high reverse current up to
20 mA; its corresponding bit in the data frame remains in a logic low state. The other inputs
remain operational. Considering the supply operation, a reverse blocking diode can be
connected between the module ground and the common COM pin to protect the application
(especially the serial resistors) from a spurious reverse supply connection. The thermal
management of this accidental situation is described in Section 4: SPI communication
speed calculation.
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7
EMC testing
EMC testing
The EMC requirements according to the IEC 61131-2 standard have been verified.
Application tests show much better results than given by the industrial standard. Test
requirements and results are listed in the table below. No additional protection devices have
been used in the application.
Table 2.
EMC immunity test requirements and results
Minimum requirements of international
standards
Tests conditions
Levels
Tests conditions
Levels
Air discharge
±8 kV
RC = 1 kΩ
RIN = 2.2 kΩ
±8 kV
Contact discharge
±4 kV
RC = 1 kΩ
RIN = 2.2 kΩ
±6 kV
Analog input
±1 kV
ESD test
IEC61000-4-2
Burst test
IEC61000-4-4 DC power line
Analog input
Surge test
IEC61000-4-5
Robustness of the STEVAL-IFP007V1
±2 kV
42 Ω, 0.5 µF
differential and
common mode
±0.5 kV
RIN = 2.2 kΩ C = 1 nF
IN
C C = 33 nF
RC = 1 kΩ
SPI signals R-C filter:
220 Ω - 100 pF
Analog
input
2 Ω, 18 µF
±0.5 kV
differential mode
DC power
DC power line
line
12 Ω, 9 µF
±1 kV
common mode
Conducted
150 kHz to
disturbance
80 MHz
test
IEC61000-4-6
No failure, no
disturbance
R IN = 2.2 kΩ ±2 kV
±2 kV
No failure,
temporary
disturbance
R C = 1 kΩ
±2 kV
R IN = 2.2 kΩ
10 VRMS
C IN = 1 nF at
AM ± 80%
the INPUT
No failure, no
disturbance
–30 VDC applied to one input, +30 VDC
on the others
No failure, no
cross-talk
3 VRMS
22 nF capacitors
150 kHz to
AM ±
at the output
80 MHz
80%
Reverse input
–VCC applied to one input during 10 s
polarity test
±4 kV
±6 kV(1)
±8 kV (1),(2)
Behavior of
the SCLT38BT8
1. Primary and secondary grounds of the optocouplers have been coupled with a 10 pF capacitor
2. Forced input filtering capacitors to maximize EFT immunity (C40 - C55 = 22 nF) with a drawback of bandwidth reduction
(<10 kHz).
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Ordering information
8
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Ordering Information
The demonstration board is available through the standard ordering system, with order code
STEVAL-IFP007V1. The complete kit contains:
9
●
Demonstration board, assembled as described in Section 2.2
●
Demonstration board documentation
●
PCB fabrication data, such as gerber files
●
Assembly files (pick-and-place)
●
Component documentation
Conclusion
This document illustrates that the SCLT3-8BT8 application works in harsh environments
without problems. All industrial standard requirements are fulfilled. Moreover, the test levels
are higher than required for a majority of final products. No additional protection devices are
necessary, increasing the cost-effectiveness of the application.
The SCLT3-8BT8 application passed the reverse polarity tests, including the thermal
management considerations.
10
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References
1.
SCLT3-8BT8 device datasheet
2.
IEC 61131-2 - Programmable Controllers - Equipment Requirements and Tests
3.
EN 60947-5-2: Low-voltage switchgear and controlgear - Part 5-2: Control circuit
devices and switching elements - Proximity switches
4.
IEC 61000-4-2: Electrostatic discharge
5.
IEC 61000-4-4: Electrical fast transient/burst immunity test
6.
IEC 61000-4-5: Surge immunity test
7.
IEC 61000-4-6: Immunity to conducted disturbances, induced by radio-frequency fields.
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11
Revision history
Revision history
Table 3.
Document revision history
Date
Revision
06-Oct-2009
1
Changes
Initial release.
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