cd00278141

AN3241
Application note
QVGA TFT-LCD direct drive
using the STM32F10xx FSMC peripheral
Introduction
This application note describes a low cost solution for directly driving QVGA TFT-LCD using
any STM32F10xxx microcontroller, which is not equipped with an on-chip LCD controller.
The powerful STM32F10xxx devices have an embedded FSMC (flexible static memory
controller) which can be used together with the on-chip DMA controller to implement a direct
drive for TFT-LCDs. This low cost solution is ideal for applications such as digital photo
frames, stand-alone information displays and static advertisement panels.
The application note describes how to use the STM32F10xx as LCD controller to drive a
QVGA 3.5" TFT panel interfaced with the FSMC. The optimization that can be achieved with
this solution means that only 1% of CPU load is needed to display static images.
A firmware demonstration has been developed and tested on a CT05350DW0000T QVGA
3.5" LCD module with a resolution of 320x240 pixels.
July 2010
Doc ID 17695 Rev 1
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www.st.com
Contents
AN3241
Contents
1
STM32 QVGA TFT-LCD direct drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
2
STM32 QVGA TFT-LCD direct drive principle . . . . . . . . . . . . . . . . . . . . . . 3
STM32 QVGA TFT-LCD drive implementation . . . . . . . . . . . . . . . . . . . . 6
2.1
QVGA TFT-LCD signal interfacing with STM32F10xx FSMC . . . . . . . . . . . 6
2.2
Image format and resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3
Image source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4
STM32 QVGA LCD-TFT direct drive flow . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4.1
2.5
Display modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
TFT-LCD backlight control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3
Hardware reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4
Firmware package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Project. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1
Firmware installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2
How to configure the QVGA TFT-LCD parameters . . . . . . . . . . . . . . . . . 18
5
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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1
STM32 QVGA TFT-LCD direct drive
STM32 QVGA TFT-LCD direct drive
The STM32 microcontrollers have an embedded Flexible Static Memory Controller (FSMC)
to interface with external memories such as NAND, NOR, SRAM and PSRAM memories.
The microcontroller also has a large number of general-purpose I/O port pins which
together with the FSMC can act as a cost-effective TFT-LCD controller for low-end displays:
1.1
●
The 16-bit data bus of the FSMC peripheral can easily be interfaced with the 565 RGB
format lines of a TFT-LCD panel (in 565 RGB format, 5 bits are for red, 6 bits for green
and 5 bits for blue).
●
An external memory can be used as the image source as well as a frame buffer for the
TFT-LCD refresh.
●
The general-purpose I/O pins can provide the synchronization logic for the LCD.
STM32 QVGA TFT-LCD direct drive principle
Controller-less TFT-LCD panels have different data-line configurations, for example 16-bit,
18-bit or 24-bit RGB lines. A TFT-LCD with a 16-bit data interface offers 565 format for each
pixel.
The TFT-LCD panel displays are managed as row and column structures. Vertical scanning
controls row data output and horizontal scanning controls column data output.
Apart from different data line configurations, other data display management signals are
common to all TFT-LCD panels:
●
The frame synchronization signal (VSYNC) manages vertical scanning and acts as an
image (frame) update strobe.
●
The line synchronization signal (HSYNC) manages horizontal line scanning and acts
as line display strobe.
●
Synchronization signals along with pixel data clock (DCLK) perform data output to TFT
RGB data lines.
●
The DCLK simply acts as the data valid signal for the TFT. The TFT considers data as
input only on the DCLK edge. DCLK valid edge (rising/falling) is mentioned in the TFT
datasheet.
The horizontal scanning builds one line for display and the vertical scanning builds a
complete frame. The vertical and horizontal scanning of the image is carried out in a
continous manner for multiple frames per second.
The TFT also needs a TFT-enable signal that acts simply as a chip-enable signal and TFT
reset signal.
The TFT signals must be synchronized in accordance with the display timing constraints to
ensure that the display has a continuous visual effect.
Figure 1 shows the horizontal and vertical scanning signals.
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STM32 QVGA TFT-LCD direct drive
Figure 1.
AN3241
QVGA TFT-LCD display scanning signals
Vertical 1Frame scan
VSYNC scan signal
QVGA TFT LCD
R G B Pixel
(5, 6, 5)
Horizontal scan line (240)
HSYNC signal for 1 line scan
ai18401
The FSMC bus data width is 16-bit. Hence, if the TFT-LCD panel has 24-bit RGB lines, the
MSBs of the LCD RGB data lines can be interfaced in 565 format.
Images must be displayed on the TFT-LCD continuously, this is easily managed by the
STM32 microcontroller.
Figure 2 shows the TFT synchronization signals waveform.
Figure 2.
Frame synchronization signal waveform
Back porch
Active data
Front porch
VCYCLE = 262 lines
tVBP = 18
VSYNC
V
DISP
= 240 lines
tVFP = 4
HSYNC
Line 0
Line 239
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STM32 QVGA TFT-LCD direct drive
Figure 3.
TFT Line synchronization signal waveform
Back porch
Active data
Front porch
HCYCLE = 408
tHFP = 20
HDISP = 320
tHBP = 68
DOTCLK
HSYNC
Pixel
data
Dummy
D0
D1
D318 D319 D320
Dummy
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STM32 QVGA TFT-LCD drive implementation
2
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STM32 QVGA TFT-LCD drive implementation
The STM32-based TFT-LCD drive is implemented using the FSMC 16-bit data bus. The
STM32 has two internal DMA controllers that are used to boost the display performance,
thereby enabling an increased display frame rate.
An external SRAM memory is used as frame buffer to allow a continuous image-refresh
process which can be controlled by a timer.
Figure 4.
STM32 TFT-LCD Drive
VSYNC, HSYNC
GPIOs
STM32F103ZE
72 MHz
64 KB SRAM
512 KB Flash
FSMC
• RGB signal
• DCLK
• TFT - Enable
3.5”
TFT - LCD
320 x RGB x 240
R G B
Pixel
(5, 6, 5)
DMA
External
SRAM
(Frame
buffer)
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2.1
QVGA TFT-LCD signal interfacing with STM32F10xx FSMC
The TFT-LCD synchronization signals VSYNC and HSYNC are managed through STM32
GPIOs.
The FSMC memory interface Write-enable signal is used in inverted configuration as a
DCLK (pixel clock) for the TFT, and the FSMC chip-select signal acts as a TFT-enable
signal.
When data is transferred to the FSMC bus, the chip-select is first asserted low to enable the
TFT-LCD. Then the write-enable signal is asserted low to allow 16-bit data transfer to the
TFT RGB line on its low level which results in a single pixel display:
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■
TFT-Enable: FSMC chip select (pin PG12)
■
VSYNC: GPIO - pin PA8
■
HSYNC: GPIO - pin PC6
■
DCLK: FSMC WE in inverted mode - pin PD5
■
Data Bus: FSMC[D0:D15]
■
SPI1: used for LCD configuration
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2.2
STM32 QVGA TFT-LCD drive implementation
Image format and resolution
The 16-bit data bus of the STM32 FSMC can drive a controller-less 24-bit LCD module. With
only 16 data lines on the FMSC memory bus, the interface is a 565-format RGB. The
remaining lines of the QVGA TFT-LCD are left open. The images are loaded in external
SRAM memory in 565 format to avoid conversion overhead for the STM32.
From a performance perspective, converted image availability in memory offers the benefit
of fast data transfer to the TFT interface. So, a faster image refresh rate can be supported.
2.3
●
Pixel data size = 16 bit = 2 bytes
●
Image memory size for QVGA TFT = 320 x 240 x 2 = 153600 Bytes
Image source
The 565 format images are programmed in NOR memory.
In a first step, two images are transferred from NOR to external on-Board SRAM. External
SRAM acts as frame refresh buffer for TFT-LCD.
To implement an animated banner display, the SRAM frame buffers are updated during run
mode with new images from NOR memory. This approach is used to maintain the exact
working model of the TFT-LCD controller.
The on-board NOR memory contains the programmed images which are to be used for
display on the LCD. SRAM Double buffer management allows the source data to be updated
in run mode.
2.4
STM32 QVGA LCD-TFT direct drive flow
To achieve a static image view on a controllerless TFT, the image frame has to be refreshed
at a rate of at least 15 fps. Vertical and horizontal scanning of one frame are performed as
per the TFT-LCD module specifications.
A QVGA-LCD module single-frame display needs 320x240 pixels of data.
240 horizontal lines (each of 320 pixels) are scanned vertically on the TFT to display one
frame.
Along with data scanning, dummy data writes are required for the TFT to reach the required
horizontal and vertical front and back-porch values. These values are available the TFT
datasheet.
Dummy data writes are composed of writing zero data to the TFT RGB lines.
●
DMA1_Channel1 is used for back porch data transfer
●
DMA1_Channel2 is used for active data transfer
●
DMA1_Channel3 is used for front porch data transfer
The FSMC is configured in asynchronous mode and operates in Mode1 which is the default
mode selected when configuring the SRAM memory type.
Figure 5 and Figure 6 show the FSMC asynchronous read and write transactions in SRAM
mode1 for one 16-bit data pixel.
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STM32 QVGA TFT-LCD drive implementation
Figure 5.
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Mode 1 - SRAM read accesses
Memory transaction
A[25:0]
NBL[1:0]
NEx
NOE
NWE
High
data driven
by memory
D[15:0]
(ADDSET +1)
HCLK cycles
(DATAST + 1)
HCLK cycles
2 HCLK
cycles
Data sampled Data strobe
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STM32 QVGA TFT-LCD drive implementation
Figure 6.
Mode1- SRAM write accesses
Memory transaction
A[25:0]
NBL[1:0]
NEx
NOE
1HCLK
NWE
D[15:0]
data driven by FSMC
(ADDSET +1)
HCLK cycles
(DATAST + 1)
HCLK cycles
ai14721c
The DMA channels are used to refresh images on the TFT-LCD. This offloads the CPU from
data transfer tasks.
The DMA is configured with external SRAM memory as the source and the LCD as the
destination. DMA transfer complete interrupts are used to toggle the VSYNC and HSYNC
synchronisation signals for a new frame transfer. A timer (TIM3) is used to control the
display frame rate.
When the DMA writes data on the FSMC bus, the FSMC generates the TFT-enable signal,
TFT DCLK, and data are written to the TFT RGB lines.
In this way, the STM32 manages the complete image display for controller-less TFT LCD
modules.
Figure 7 and Figure 7 show the TFT- LCD single-frame and horizontal-line display flow
diagram.
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STM32 QVGA TFT-LCD drive implementation
Figure 7.
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TFT- LCD single-frame display flow diagram
Start new frame
Reset TFT-LCD module
Set VSYNC signal low for vertical front porch
Write dummy data horizontal line for vertical
front porch period
Set VSYNC signal high
Write 240 active data horizontal lines
Write dummy data horizontal lines for vertical
back porch period
Note:
10/21
Refer to the TFT-LCD datasheet for the vertical front porch and back porch period values.
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STM32 QVGA TFT-LCD drive implementation
Figure 8.
TFT- LCD single horizontal-line display flow diagram
Start new horizontal line scan
Set HSYNC signal low for horizontal
line front porch period
Write dummy data pixels on TFT-LCD RGB lines
Set HSYNC signal high for active data write
Write 320 active data horizontal lines
Write dummy data pixels for horizontal line front
line back porch period
Note:
Refer to the TFT-LCD datasheet for the horizontal front porch and back porch period values
2.4.1
Display modes
Two display modes are provided and can be selected.
STM32 slide-show display mode
In this mode, two static images in the SRAM buffers are displayed on the TFT-LCD after a
fixed time interval. The user can configure more than 2 images as well as change the
Frame buffer address location. In this mode, up to 40 frames per second can be displayed.
Table 1.
STM32 slide-show display: CPU load & frame rate
Parameter
Value
DCLK (pixel clock)
3.6 MHz
Maximum frame rate
40 Hz
CPU load
1%
STM32 banner display mode
In this mode, image buffers in SRAM are dynamically updated from NOR Flash memory to
show an image animation. For updating the image, two DMA channels are used.
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STM32 QVGA TFT-LCD drive implementation
Table 2.
AN3241
STM32 slide-show display: CPU load & frame rate
Parameter
Value
DCLK (pixel clock)
3.6 MHz
Maximum frame rate
19 Hz
CPU load
51%
The frame rate in Banner display mode is lower due to the SRAM frame buffer dynamic
update for the animation. The Frame buffer update is made after the display of one complete
frame display.
Note:
The frame rate and CPU load measurements were done with high speed optimization using
EWARM Toolchain V5.5. The CPU frequency is 72 MHz.
2.5
TFT-LCD backlight control
In both display modes, the TFT backlight is also controlled via a Timer and an ADC channel.
The timer (TIM4) is configured to generate 1 KHz PWM signal output on PB6 and can be
used as a PWM enable signal for the TFT backlight controller. The TFT-LCD backlight
control is implemented by varying the duty cycle of the PWM enable signal by rotating the
RV1 potentiometer installed on the MB672 STM3210E-EVAL evaluation board.
For more details on the potentiometer hardware, please refer to the MB672
STM3210E-EVAL evaluation board user manual.
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3
Hardware reference design
Hardware reference design
The STEVAL-CCM002V1 evaluation board intended to be used as a daughter board for
MB672 STM3210E-EVAL Evaluation board. The STEVAL-CCM002V1 board has a QVGA
TFT 3.5" (CT05350DW0000T (thin-film-transistor liquid crystal display)).
The table below provides description of the CT05350DW0000T TFT signals when
interfacing with STM32F103ZET6.
Table 3.
STM32F103ZET6 signal interface with CT05350DW0000T LCD
LCD signal
STM32F103ZET6 signal
Description
LCD Reset
GPIO- PC1
Used to reset TFT-LCD
LCD X1,X2,Y1,Y2
Connected to STMPE811
touchscreen controller device
LCD touch screen signals
LCD B0-LCD B2
Do not connect
LCD blue data lines [0-2]
LCD B3-LCD B7
FSMC[D0..D4]
LCD blue data lines [3-7]
LCD G0-LCD G1
Do not connect
LCD green data lines [0-1]
LCD G2-LCD G7
FSMC[D5..D10]
LCD green data lines [2-7]
LCD R0-LCD R2
Do not connect
LCD red data lines [0-2]
LCD R3-LCD R7
FSMC[D11..D15]
LCD red data lines [3-7]
LCD HSYNC
GPIO- PC6
LCD horizontal synchronization
signal
LCD VSYNC
GPIO- PA8
LCD vertical synchronization
signal
LCD DCLK
FSMC NWE Inverted
LCD pixel clock signal
LCD SPI CS
SPI1_CS - PA4
LCD SPI chip select signal
LCD SPI CLK
SPI1_CLK - PA5
LCD SPI clock signal
LCD SPI DATA
SPI1_ MOSI -PA7
LCD SPI data signal
LCD ENABLE
FSMC NE4
LCD chip select signal
Please refer to User manual UM0921 for a complete description of the STEVAL-CCM002V1
daughter board.
The daughter board order code is: STEVAL-CCM002V1.
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Hardware reference design
Figure 9.
STM3210E- EVAL board connector for TFT-LCD
GND
PG7
PG5
PG3
PC13
RESET#
PD12
PD10_LCD_R7
PD8_LCD_R5
D5V
PB13
PB11_TSC_SDA2
PE15_LCD_R4
PE13_LCD_G7
PE11_LCD_G5
PD15_LCD_B4
PE9_LCD_G3
PE7_LCD_B7
PG1
GND
PF14
PF12
PB2
PB1
3V3
AN3241
PB0
PC4
PA6
PA4_SPI_CS
GND
PA1
PC3_TSC_INT
PC1_LCD_RESET
PF10
3V3
J1
CN6
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
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51
53
55
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61
63
65
67
69
2
4
6
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52
54
56
58
60
62
64
66
68
70
PG8
PG6
PG4
PG2
GND
PD13
PD11
PD9_LCD_R6
PB15
PB14
PB12
PB10_TSC_SCL2
PE14_LCD_R3
PE12_LCD_G6
GND
PD14_LCD_B3
PE10_LCD_G4
PE8_LCD_G2
GND
PG7
PG5
PG3
PC13
RESET#
PD12
PD10_LCD_R7
PD8_LCD_R5
D5V
PB13
PB11_TSC_SDA2
PE15_LCD_R4
PE13_LCD_G7
PE11_LCD_G5
PD15_LCD_B4
PE9_LCD_G3
PE7_LCD_B7
PG1
GND
PF14
PF12
PB2
PB1
PG0
PF15
PF13
PF11
GND
PC5
PA7_SPI_DATA
PA5_SPI_CLK
PA3
PA2
PB0
PC4
PA6
PA4_SPI_CS
GND
PA1
PC3_TSC_INT
PC1_LCD_RESET
PF10
3V3
3V3
PC2
PC0
GND
J2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
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51
53
55
57
59
61
63
65
67
69
CON70A
GND
PC7
PC9
PA9
PA0
PA12
PA14
PC10
GND
PD0_LCD_B5
PE2
PD2
PD4
PD6
PD7
PG10
PG12_LCD_ENB
PG14
GND
PB4
PB6
PB8
PE0
D5V
PE4
PE6
PC14
PF0
GND
PF2
PF4
PF6
PF8
3V3
3V3
J3
PG8
PG6
PG4
PG2
GND
PD13
PD11
PD9_LCD_R6
PB15
PB14
PB12
PB10_TSC_SCL2
PE14_LCD_R3
PE12_LCD_G6
GND
PD14_LCD_B3
PE10_LCD_G4
PE8_LCD_G2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
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48
50
52
54
56
58
60
62
64
66
68
70
PC6
PC8
PA8
PA10
GND
PA11
PA13
PA15
PC11
PC12
PD1_LCD_B6
PE1
PD3
PD5
GND
PG9
PG11
PG13
PG15
PB3
PB5
PB7
PB9
3V3
GND
PE3
PE5
PC13
PC15
PF1
PF3
PF5
PF7
PF9
GND
PG0
PF15
PF13
PF11
GND
PC5
PA7_SPI_DATA
PA5_SPI_CLK
PA3
PA2
PC2
PC0
GND
CON70A
CN5
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
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65
67
69
2
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6
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10
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30
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2
4
6
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30
32
34
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40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
PC6
PC8
PA8
PA10
GND
PA11
PA13
PA15
PC11
PC12
PD1_LCD_B6
PE1
PD3
PD5
GND
PG9
PG11
PG13
PG15
PB3
PB5
PB7
PB9
3V3
GND
PE3
PE5
PC13
PC15
PF1
PF3
PF5
PF7
PF9
GND
GND
PC7
PC9
PA9
PA0
3V3
CON70A
PA12
PA14
PC10
GND
PD0_LCD_B5
PE2
PD2
PD4
PD6
PD7
PG10
PG12_LCD_ENB
PG14
GND
PB4
PB6
PB8
PE0
D5V
PE4
PE6
PC14
PF0
GND
PF2
PF4
PF6
PF8
3V3
3V3
J4
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
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61
63
65
67
69
3V3
CON70A
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Hardware reference design
Figure 10. TFT-LCD 54 pin connector
J5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
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37
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39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
LED_CATHODE
LED_ANODE
PC1_LCD_RESET
TSC_Y1
TSC_X1
TSC_Y2
TSC_X2
PD14_LCD_B3
PD15_LCD_B4
PD0_LCD_B5
PD1_LCD_B6
PE7_LCD_B7
PE8_LCD_G2
PE9_LCD_G3
PE10_LCD_G4
PE11_LCD_G5
PE12_LCD_G6
PE13_LCD_G7
PE14_LCD_R3
PE15_LCD_R4
PD8_LCD_R5
PD9_LCD_R6
PD10_LCD_R7
HSYNC
VSYNC
DCLK
3V3
R13
0
3V3
R3
0
PC6
R4
0
PA8
PA4_SPI_CS
GND
R14
0
PA5_SPI_CLK
PA7_SPI_DATA
PD5
R1
0
R2
0
FSMC_INV_CLK
PG12_LCD_ENB
TFT_CONN54
3V3
3V3
GND
DCLK
LED_ANODE
TSC_Y1
TSC_X1
TSC_Y2
TSC_X2
HSYNC
VSYNC
LED_CATHODE
J6
1
2
3
4
5
6
7
8
9
10
LCD_SIGNAL_CONN
ai18410
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Firmware package
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Firmware package
The firmware associated to this application note consists of a demonstration of a direct drive
TFT (CT05350DW0000T) using the STM32F103ZE device. The source code example is
based on the STM32F10xxx standard peripheral library V3.3.0.
The user may build any similar application using the same library and driver, and different
interfacing firmware/hardware.
The firmware package installation folders are shown in Figure 11.
Figure 11. Firmware package architecture
Libraries
The Libraries folder contains all the subdirectories and files that make up the core of the
STM32F10xxx Standard Peripheral library V3.3.1:
CMSIS
●
CM3\CoreSupport: contains the Cortex-M3 files
●
CM3\DeviceSupport\ST\STM32F10x: contains the STM32F10x CMSIS layers files.
STM32F10x_StdPeriph_Driver
●
inc subfolder: contains the Standard Peripheral library header files
●
src subfolder: contains the Standard Peripheral library source files
Project
STM3210x-LCDDrive
Images: contains the Image.dfu file of the bitmap images.
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Firmware package
EWARMv5: contains preconfigured projects for the EWARM toolchain
ARM-MDK: contains preconfigured projects for the RVMDK toolchain
HiTOP: contains preconfigured projects for the HiTOP toolchain
RIDE: contains preconfigured projects for the RIDE toolchain
TrueSTUDIO: contains preconfigured projects for the attolic toolchain
●
●
inc subfolder: contains the TFT-LCD driver and the demonstration heard files:
–
lcd_driver.h: contains the prototypes of the basic functions to drive a controllerless TFT-LCD. It includes also the TFT-LCD configurable parameters following the
TFT specification.
–
backlight_control.h: contains the prototypes of the basic functions used to control
the TFT backlight.
–
main.h: this file contains prototypes for the main.c file
–
stm32f10x_it.h: contains the headers of the interrupt handler.
–
stm32f10x_conf.h: the microcontroller library configuration file
src subfolder: contains the TFT-LCD driver and the demonstration source files:
–
lcd_driver.c: it contains basic routines to drive a controller-less QVGA TFT-LCD
including the FSMC, GPIO pins and DMA configurations
–
backlight_control.c: contains the basic functions used to control the TFT-LCD
backlight.
–
mainc.c: initializes the TFT-LCD Drive demonstration
–
stm32f10x_it.c: contains all the peripheral interrupt service routines used in the
LCD driver and provides templates for all exception handlers.
Utilities
STM3210E-EVAL: contains the STM3210E-EVAL board-related drivers
4.1
Firmware installation
The firmware associated with this application note is built for the STM3210E- EVAL
Evaluation board and the STEVAL-CCM002V1 daughter board.
After successful hardware setup and firmware programming, a bitmap image starts
displaying on the TFT-LCD on the STEVAL-CCM002V1 evaluation board.
Banner display mode is selected by default.
Push the Key button connected to PB3 on the STM3210E-EVAL Evaluation board to switch
to slide show display mode.
Demonstration Images
16-bit Bitmap images are copied by the firmware from NOR memory to on-board external
SRAM during firmware initialization. Then the image is refreshed on the TFT-LCD from
external SRAM only.
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Firmware package
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These images are programmed by default in the NOR memory the MB672 STM3210EEVAL Evaluation board. If the images are not available in NOR memory, they can be easily
programmed in the NOR memory using USB DFU firmware. For more details on board and
NOR programming, refer the UM0549 user manual available on www.st.com.
The USB DFU firmware and DFU image file are available for download from the
STMicroelectronics website: www.st.com.
4.2
How to configure the QVGA TFT-LCD parameters
The LCD driver can be customized to support other types of QVGA LCDs. The QVGA LCD
parameters that can be updated are the front porch, back porch period or frame rate
frequency as well as the I/O pins used for VSYNC and HSYNC, TFT power control and
backlight.
These configurable parameters are defined in the lcd_driver.h and backlight_control.h
header files.
The TFT LCD driver can be easily ported to other hardware. Table 4 describes the
configurable TFT-LCD parameters.
Table 4.
QVGA TFT-LCD driver configurable parameters
QVGA TFT-LCD parameters
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Description
#define LCD_FRAME_FRONT_PORCH
Frame Front Porch value
#define LCD_FRAME_BACK_PORCH
Frame Back Porch value
#define LCD_LINE_FRONT_PORCH
Line Front Porch value
#define LCD_LINE_BACK_PORCH
Line Back Porch value
#define SRAM_IMAGE1_ADDR
Address of first image in frame buffer
#define SRAM_IMAGE2_ADDR
Address of second image in frame buffer
#define FRAME_RATE
Frame rate frequency value (can be 40 Hz or 19 Hz)
#define SLIDESHOW_TIME_GAP
Slide show time value in second
#define TFT_VSYNC_GPIO_PIN
GPIO Pin:GPIO_Pin_8
#define TFT_VSYNC_GPIO_PORT
GPIO Port: GPIOA
#define TFT_HSYNC_GPIO_PIN
GPIO Pin: GPIO_Pin_6
#define TFT_HSYNC_GPIO_PORT
GPIO Port: GPIOC
#define LCD_BL_GPIO_PIN
GPIO Pin: GPIO_Pin_6
#define LCD_BL_GPIO_PORT
GPIO Port: GPIOB
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5
Conclusion
Conclusion
The versatile capabilities of the STM32 peripherals have been put to good use in this case,
with the objective of simplifying and lowering the cost of a TFT-LCD based application. The
STM32 with its powerful DMA controller and highly flexible FSMC peripheral combine to
offer a cost-effective solution for driving a QVGA TFT-LCD with a CPU load of only 1% for
static image display.
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Revision history
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Revision history
Table 5.
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Document revision history
Date
Revision
16-Jul-2010
1
Changes
Initial release.
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