brspear0511

SPEAr family of embedded
microprocessors
STMicroelectronics
www.st.com/spear
SPEAr devices, based on ARM core architecture, offer substantial processing
power and wide peripheral support
Embedded applications today demand increasingly higher levels of performance and power efficiency for
computing, communication, control, security and multimedia.
ST’s SPEAr® embedded MPUs meet these challenges head-on with state-of-the-art architecture, silicon
technology and intellectual property, targeting networked devices used for communication, display and control of
a broad range of applications.
The SPEAr family of embedded microprocessors are based on ARM cores: a single ARM926EJ-S core for the
SPEAr300 series, dual ARM926EJ-S cores for the SPEAr600, and dual Cortex-A9 cores for the SPEAr1300 series.
Key features
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Key benefits
The family presents a scalable
processing power range,
depending on the type and number
of cores used
Within a series, each device targets
a specific application segment, and
offers peripherals and controllers in
line with this specialization
All SPEAr embedded
microprocessors embed the
external memory management
function via a dynamic memory
controller
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ST’s low-power technology makes SPEAr microprocessors extremely
power-efficient, permitting portable applications to run longer without
recharging, saving operating costs for end customers and allowing your
applications to meet the most stringent regulatory standards
Standard core architecture is supported by a wide range of 3rd party tool
providers, for easy development
Processing
power
SPEAr1310
Dual ARM Cortex-A9
600 MHz
3000 DMIPS
SPEAr600
Dual ARM926EJ-S
333 MHz
733 DMIPS
360 DMIPS
SPEAr300
ARM926EJ-S
333 MHz
SPEAr310
ARM926EJ-S
333 MHz
SPEAr320
ARM926EJ-S
333 MHz
LFBGA289
15 x 15 mm, 0.8 mm pitch
2
SPEAr1340
Dual ARM Cortex-A9
600 MHz
PBGA420
23 x 23 mm, 1 mm pitch
PBGA628
23 x 23 mm, 0.8 mm pitch
Package
Device summary
SPEAr device
SPEAr300
Core
ARM926EJ-S
Max CPU speed
Memories
Connectivity
400
LP_DDR2, DDR2, SRAM,
NAND/NOR Flash
Ethernet, USB2.0 (3),
I2C, I2S, FIrDA, SPI,
UART, TDM
Peripherals
Other functions
FPGA, SDIO/MMC card
camera I/F,
LCD controller,
touchscreen controller,
keyboard controller
Cryptography
accelerator,
JPEG, ADC,
62 GPIOs
Ethernet (5), USB2.0 (3),
I2C, SPI, UARTs, TDM,
HDLC, RS485
FPGA
Cryptography
accelerator,
JPEG, ADC
102 GPIOs
SPEAr310
ARM926EJ-S
400
LP_DDR2, DDR2, SRAM,
NAND/NOR Flash
SPEAr320
ARM926EJ-S
400
LP_DDR2, DDR2, SRAM,
NAND/NOR Flash
Ethernet (2), USB2.0 (3),
I2C, I2S, IrDA, SPIs, UARTs,
CAN(2)
FPGA, SDIO/MMC card,
LCD controller,
touchscreen controller
Cryptography
accelerator,
JPEG, ADC, PWM
102 GPIOs
SPEAr600
Dual
ARM926EJ-S
400
DDR1, DDR2, SRAM,
NAND/NOR Flash
Giga-Ethernet,
USB2.0 (3), I2C, I2Ss,
IrDA, SPIs, UARTs
LCD controller,
touchscreen controller
Ext local bus,
JPEG, ADC,
10 GPIOs
SPEAr1310
Dual
ARM Cortex-A9
600
DDR3, DDR2, SRAM,
NAND/NOR Flash, OTP
Giga-Ethernet (2),
Ethernet (3), PCIe/SATA (3),
USB2.0 (3), CAN (2), TDM,
HDLC, UARTs, I2S, I2C, SPI
Memory card,
LCD controller,
touchscreen controller,
keyboard controller
Cryptography
accelerator,
JPEG, ext local bus,
ADC, GPIOs
DDR3, DDR2, SRAM,
NAND/NOR Flash, OTP
Giga-Ethernet, PCIe/SATA,
USB2.0 (3), UARTs, I2S,
I2C, SPI
Memory card,
LCD controller,
touchscreen controller,
keyboard controller,
camera I/F,
video input
Mali 200 GPU, HW
HD video encoder
and decoder,
cryptography
accelerator,
JPEG, ADC, GPIOs
SPEAr1340
Dual
ARM Cortex-A9
600
Design support
SPEAr embedded microprocessors are supported by many 3rd party development tools, including:
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ARM (www.arm.com)
Green Hills Software (www.ghs.com)
IAR (www.iar.com)
Lauterbach (www.lauterbach.com)
Mentor Graphics (www.mentor.com/embedded)
Wind River (www.windriver.com)
Our SPEAr evaluation kits are designed to:
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Speed up the software development/debug process
Familiarize you quickly with SPEAr eMPU features – each evaluation kit offers all of the interfaces that the SPEAr device can
manage
Act as a starting point for your final application board development
Device
Board part number
Description
SPEAr300
EVALSPEAR300
Evaluation kit
SPEAr310
EVALSPEAR310
Evaluation kit
SPEAr320
EVALSPEAR320CPU
EVALSPEAR320PLC
EVALSPEAR320HMI
Evaluation kit comprised of CPU + PLC boards, for industrial applications
Single board evaluation kit for generic applications
Application board for HMI applications (CPU board is required – order separately)
SPEAr600
EVALSPEAR600
EVALSPEAR600FPG
Evaluation kit
Evaluation kit with FPGA for system development
Note:
SPEAr1300 series evaluation boards will be available from Q3 2011
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SPEAr products
SPEAr300
The SPEAr300 delivers everything you want for low power consumption, high-connectivity applications, such as IP phones,
human-machine interfaces and security applications.
Key features
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9x9 keyboard
2 x USB 2.0 Hosts
+ PHYs
JPEG codec
accelerator
ADC
(8-channel, 10-bit)
1 bit DAC
GPIOs
FSMC
Dithered DDR
clock
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Low jitter USB PLL
ARM926EJ-S
@ 333 MHz
Dithered system
clock
Vectorized
interrupt controller
USB 2.0 device
+ PHY
MII Ethernet
MAC 10/100
UART
Real-time clock
IrDA
Watchdog
I²C
6 x 16-bit timers
I²S
Connectivity interfaces
C3 crypto
accelerator
Codec/SLIC I/F
Memory interfaces
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LCD controller
AMBA bus 2.0
Application specific functions
Camera interface
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SPI
Dynamic memory
controller
TDM controller
512 timeslots
Serial Flash I/F
ARM926EJ-S core, 400 MHz
High-performance 8-channel DMA
Connectivity:
QQ USB 2.0 (2 hosts, 1 device)
QQ Fast Ethernet (MII port)
2
²
QQ SPI, I C, I S, UART and fast IrDA
interfaces
QQ Up to 8 I²C/SPI chip selects
QQ TDM bus (512 timeslots)
Peripherals supported:
QQ Camera interface (ITU-601/656
and CSI2 support)
QQ LCD controller (resolutions up to
1024 x 768 and up to 24 bpp)
QQ Touchscreen support
QQ 9 x 9 keyboard controller
QQ Glueless management of
up to 8 SLICs/codecs
SDIO/MMC card I/F
SPEAr310
Key features
JPEG codec
accelerator
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C3 crypto
accelerator
2 x USB 2.0 Hosts
+ PHYs
ADC
(8-channel, 10-bit)
Low jitter USB PLL
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FSMC
Dithered DDR
clock
MII Ethernet
MAC 10/100
Quad SMII Ethernet
MAC10/100
Real-time clock
6 x UART
Watchdog
IrDA
6 x 16-bit timers
I²C
SPI
Dynamic memory
controller
Serial Flash I/F
2 x HDLC RS-485
TDM controller
128 ch with 64 HDLC
Connectivity interfaces
Vectorized
interrupt controller
Memory interfaces
USB 2.0 device
+ PHY
ARM926EJ-S
@ 333 MHz
Dithered system
clock
4
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GPIOs
AMBA bus 2.0
Application specific functions
The SPEAr310 targets telecom and networking applications with its high number of Ethernet ports (1 MII and 4 SMII ports), and
2 HDLC ports.
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ARM926EJ-S core, 400 MHz
High-performance 8-channel DMA
Connectivity:
QQ USB 2.0 (2 hosts, 1 device)
QQ 1 fast Ethernet MII port
QQ 4 fast Ethernet SMII ports
2
QQ SPI, I C and fast IRDA interfaces
QQ 6 UART interfaces
QQ TDM bus (128 timeslots with
64 HDLC channels)
QQ 2 HDLC ports with RS-485
support
Miscellaneous functions:
QQ Integrated real-time clock,
watchdog and system controller
QQ 8-channel, 10-bit ADC, 1 MSPS
QQ JPEG codec accelerator
QQ 6 general-purpose 16-bit
timers with capture mode and
programmable prescaler
QQ Up to 102 GPIOs with interrupt
capablility
SPEAr320
Key features
The SPEAr320 targets factory automation and consumer applications, with an
integrated LCD controller (resolution: 1024x768) and touchscreen support, as well
as a host of ports and interfaces.
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4 x PWM
ADC
(8-channel, 10-bit)
2 x USB 2.0 Hosts
+ PHYs
JPEG codec
accelerator
GPIOs
Low jitter USB PLL
ARM926EJ-S
@ 333 MHz
Dithered system
clock
Vectorized
interrupt controller
Memory interfaces
FSMC
Dithered DDR
clock
USB 2.0 device
+ PHY
2 x Ethernet MACs
10/100 (MII/SMII)
3 x UART
Real-time clock
IrDA
Watchdog
2 x I²C
6 x 16-bit timers
STD parallel port
Connectivity interfaces
C3 crypto
accelerator
AMBA bus 2.0
Application specific functions
LCD controller
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3 x SPI
Dynamic memory
controller
2 x CAN interfaces
Serial Flash I/F
SDIO/MMC card I/F
Key features
SPEAr600
High-performance dual 32-bit ARM926EJ-S CPU cores make this device the right
choice for cost-sensitive applications that require extra computational power.
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External local bus
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JPEG codec
accelerator
2 x USB 2.0 Hosts
+ PHYs
ADC
(8-channel, 10-bit)
Vectorized
interrupt controller
FSMC
Dithered DDR
clock
Dynamic memory
controller
Serial Flash I/F
GMII Ethernet MACs
10/100/1000
2 x UART
IrDA
Real-time clock
I²C
Watchdog
3 x SPI
10 x 16-bit timers
3 x I²S
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Connectivity interfaces
USB 2.0 device
+ PHY
ARM926EJ-S
@ 333 MHz
Dithered system
clock
Memory interfaces
Low jitter USB PLL
ARM926EJ-S
@ 333 MHz
AMBA bus 2.0
Application specific functions
LCD controller
GPIOs
ARM926EJ-S core, 400 MHz
High-performance 8-channel DMA
Connectivity:
QQ USB 2.0 (2 hosts, 1 device)
QQ 2 fast Ethernet ports (MII/SMII
ports)
QQ 2 CAN interfaces
2
QQ I S and fast IRDA interfaces
QQ 3 SPI ports
2
QQ 2 I C interfaces
QQ 3 UART interfaces
QQ 1 standard parallel device port
Peripherals supported:
QQ LCD controller (resolutions up to
1024 x 768 and up to 24 bpp)
QQ Touchscreen support
Miscellaneous functions:
QQ Integrated real-time clock,
watchdog and system controller
QQ 8-channel, 10-bit ADC, 1 MSPS
QQ JPEG codec accelerator
QQ 6 general-purpose 16-bit
timers with capture mode and
programmable prescaler
QQ Up to 102 GPIOs with interrupt
capablility
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Dual ARM926EJ-S cores, 400 MHz
High-performance 8-channel DMA
Up to 733 DMIPS
Connectivity:
QQ USB 2.0 (2 hosts, 1 device)
QQ 1 Giga Ethernet port (GMII port)
2
QQ I C and fast IrDA interfaces
QQ 3 SPI ports
2
QQ 3 I S interfaces (1 stereo input, 2
stereo outputs)
QQ 2 UART interfaces
Peripherals supported:
QQ LCD controller (resolutions up to
1024 x 768 and up to 24 bpp)
QQ Touchscreen support
Miscellaneous functions:
QQ Integrated real-time clock,
watchdog and system controller
QQ 8-channel, 10-bit ADC, 1 MSPS
QQ JPEG codec accelerator
QQ 10 general-purpose 16-bit
timers with capture mode and
programmable prescalers
QQ 10 GPIOs with interrupt
capablilities
QQ External 32-bit local bus
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SPEAr1310
The SPEAr1310, with dual ARM Cortex-A9 cores and a DDR3 (third-generation, double-data-rate) memory interface, offers
an unprecedented combination of processing performance and advanced power reduction control for next-generation
communication appliances.
SPEAr1310 targets cost and power sensitive networking applications for the home and small businesses as well as telecom
infrastructure equipment, with lowest overall leakage under real operating conditions. The device integrates ARM’s latest
generation ARMv7 CPU cores, ST’s proven C3 security coprocessor, and advanced connectivity interfaces and controllers.
EXPI expansion interface
2 x USB 2.0 Hosts
+ PHYs
Cortex-A9
@ 600 MHz
2x 32-Kbyte L1
HD display controller
Touchscreen
Cortex-A9
@ 600 MHz
2x 32-Kbyte L1
Keyboard controller
GPIOs
Dithered system
clock
ADC, 10-bit, 8 ch
Vectorized
interrupt controller
RTC + 64-byte RAM
Memory interfaces
Low jitter USB PLL
ECC
512-Kbyte
L2 ACP
32-Kbyte boot RAM
DMAs
510 + 209-bit OTP
System timers
Ext-memory I/F
Watchdogs
USB OTG 2.0
+ PHY
2x Giga
Ethernet MAC
3x Ethernet MAC
10/100
3x PCIe/SATA
PCI32 @ 66 MHz
Dual CAN
Connectivity interfaces
C3 crypto accelerator
Interconnection subsystem (Noc)
Application specific IPs
JPEG codec
accelerator
2x HDLC (E1/TDM)
2x HDLC (RS485)
Dynamic memory
controller
DDR2/DDR3 ECC
6x UARTs
NAND/NOR Flash I/F
2 x I²S
Memory card I/F
SPI
2x I²C
Key features
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Dual ARM Cortex-A9 cores
running at 600 MHz
Supports both symmetric and
asymmetric multiprocessing
Bus: 64-bit multilayer
network-on-chip
Connectivity:
QQ Giga/Fast Ethernet ports
QQ 3x PCIe 2.0 / SATA
QQ 3x USB 2.0 (Host/OTG)
QQ 2x CAN 2.0 a/b interfaces
QQ 2x HDLC RS485
2
2
QQ I S, UART, I C and SPI ports
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Peripherals supported:
QQ TFT LCD display
up to 1920 x 1080 (60 Hz)
QQ Touchscreen interface
QQ 9 x 9 keyboard
QQ Memory card interface
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Power saving:
QQ Power islands for leakage
reduction
QQ IP clock gating for dynamic
power reduction
QQ Dynamic frequency scaling
SPEAr1340
ST’s SPEAr1340 integrates a powerful ARM Mali-200 graphics processing unit to offer advanced 2D and 3D acceleration for
user interfaces, navigation, browsing and gaming. This device also embeds a hardware video encoder and decoder supporting
major compression standards (including H.264 and AVS), with video resolution up to 1080p and 30 frames per second. These
capabilities also enable multiple concurrent video flows in applications like surveillance and video-conferencing. Hardware
implementations of graphic and video capabilities in the SPEAr1340 result in state-of-the art multimedia performance at ultralow power consumption. Meanwhile, the two Cortex-A9 cores are available to perform concurrent tasks as required. With
its multiple interfaces, including I2S and S/PDIF, the SPEAr1340 also provides excellent audio capabilities, handling up to 7.1
surround-sound configurations in both input and output paths.
In security, the SPEAr1340 integrates a multi-standard cryptographic engine and one-time programmable (OTP) registers for
unique identification and external Flash memory anti-tamper protection.
Manufactured in ST’s low-power 55 nm HCMOS (high-speed CMOS) process technology, this new microprocessor benefits
from the state-of-the-art SPEAr1300 architecture, which combines the unrivalled low-power and multi-processing capabilities
of two ARM Cortex-A9 cores with innovative network-on-chip (NoC) technology.
The SPEAr1340 has a dual ARM Cortex-A9 core and is optimized for user interfaces and multimedia in web-connected and
industrial applications, including applications with high-resolution video-conferencing and security cameras.
2 x USB 2.0 Hosts
+ PHYs
C3 crypto accelerator
Cortex-A9
@ 600 MHz
2x 32-Kbyte L1 512-Kbyte
L2 ACP
Cortex-A9
@ 600 MHz
2x 32-Kbyte L1
HD video decoder
2D/3D graphic
HD LCD controller
Touchscreen
Dithered system
clock
Keyboard controller
4 x PWM
ADC, 10-bit, 8 ch
Vectorized
interrupt controller
GPIOs
RTC + 64-byte RAM
DMAs
Memory interfaces
32-Kbyte boot RAM
System timers
510 + 209-bit OTP
Low jitter USB PLL
USB OTG 2.0
+ PHY
Watchdogs
Ext-memory I/F
Giga
Ethernet MAC
1x PCIe/SATA
2x UARTs/IrDA
2x I²C
SPI
Connectivity interfaces
HD video encoder
Interconnection subsystem (Noc)
Application specific IPs and accelerators
It includes a Mali-200 2D/3D GPU and a multistandard HD video encoder and decoder. The device integrates ARM’s latest
generation ARMv7 CPU cores, ST’s proven C3 security coprocessor, and advanced connectivity interfaces and controllers.
Audio input
Audio output
Video input
Dynamic memory
controller
DDR2/DDR3
4 camera interfaces
2x HDMI-CEC
NAND/NOR Flash I/F
Memory card I/F
Key features
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Dual ARM Cortex-A9 cores running
up to 600 MHz
Supports both symmetric and
asymmetric multiprocessing
Bus: 64-bit multilayer
network-on-chip
ARM Mali-200 2D/3D GPU
up to 1080p, OpenGL ES 2.0,
OpenVG 2.0
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Multimedia:
QQ Multi-standard HD video decoder
and encoder, up to 1080p
QQ Digital video port with alternate
configuration for 4 camera
interfaces
QQ 7.1 multichannel surround audio
Connectivity:
QQ Giga/Fast Ethernet ports
QQ 1x PCIe 2.0 / SATA
QQ 3x USB 2.0 (Host/OTG)
2
2
QQ I S, UART and I C
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Peripherals supported:
QQ TFT LCD display
up to 1920 x 1080 (60 Hz)
QQ Touchscreen interface
QQ 9 x 9 keyboard
QQ Memory card interface
Power saving:
QQ Power islands for leakage
reduction
QQ IP clock gating for dynamic
power reduction
QQ Dynamic frequency scaling
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© STMicroelectronics - May 2011 - Printed in United Kingdom - All rights reserved
The STMicroelectronics corporate logo is a registered trademark of the STMicroelectronics group of companies
All other names are the property of their respective owners
Order code: BRSPEAR0511
For more information on ST products and solutions, visit www.st.com
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