Repetitive voltage suppressors for overvoltage protection The STRVS is the first TVS series to be specified against repetitive overvoltages in high temperature conditions In applications, overvoltage constraints may not always come from lightning, electrical overstress or electrostatic discharge, but from the circuit itself. In such cases, standards do not apply. Repetitive surges may raise protection device temperature. This is why protection devices must be selected according to their power capability at high junction temperatures and their clamping voltage specified at high temperature. KEY FEATURES KEY BENEFITS Application driven • Better Transil™ selection for cost • 2 key parameters specified: VCL for multiple temperatures and peak current from 0 to 2 A • RD for multiple temperatures and peak currents from 0 to 2 A • Application note supporting product selection • Improved power derating versus temperature • optimization (oversizing avoided) • Fixed and reliable clamping voltage not sensitive to output load • Better protection with smaller package versus competition • Reduced power consumption versus discrete protection (RC snubber) • Customer design effort reduced TARGETED APPLICATIONS MOSFET and IGBT protection in: • Solar inverters • SMPS and auxiliary power supplies • Smart metering • LED drivers www.st.com DESIGN NOTES APPLICATION KEY PARAMETERS 2.0 1.5 125°C RD 1.0 Ipp(A) Design information and calculations are developed in detail in the application note “Design methodology of TVS in repetitive mode: STRVS”. Below, you will find a short summary of the steps to be considered. 1. VRM selection The VRM selected should be higher than the highest voltage at STRVS nodes during normal operating conditions. 2. VCL @ 125 °C verification The designer should check that VCL @ 125 °C is low enough to protect the MOSFET during surges (assuming that 125 °C is the worst case application temperature). 3. STRVS temperature verification • The power dissipated in the STRVS should be calculated. • Pstep= Ipeakx(3xVCL0+2xIpeakxRD)/6 • PD= tpxFSWxPstep • The calculated temperature has to be lower than 125 °C: • Tjpeak= Rth(j-a)xPD+Tamb Ipeak 0.5 0.0 Vcl0 110 120 Vcl * Vpeak@125°C Glossary • Vpeak: Clamping voltage @ Ipeak for a given temperature (25/85/125°C) • VCL0: Voltage value where the RD line crosses the 0 A axis • Rd: Dynamic resistance allowing designer to linearize the avalanche zone for 0 < I < Ipeak • Ipeak: Maximum current flowing through the STRVS during each pulse STRVS PROTECTION FOR ST COMPANION CHIPS • VIPers • HVLEDs • Power MOSFETs • ALTAIR DEVICE SUMMARY IRM max @ VRM (25 °C) Part number VBR (typ. with IR = 1 mA) Values @ 125 °C Packages (µA) (V) (V) Ipeak (A) Vpeak (typ) (V) VCL0 (V) RD(Ω) STRVS118X02C(*) 0.2 85 100 2 118 116 1.0 SMC STRVS142X02F(*) 1 102 120 2 142 140 1.0 DO-201 STRVS182X02F(*) 1 128 150 2 182 177 2.5 DO-201 0.2 128 150 2 185 178 3.5 SMB/DO-15 STRVS222X02F(*) 1 154 180 2 222 213 4.5 DO-201 STRVS225X02E(*) 0.5 154 180 2 225 214 5.5 DO-15 STRVS241X02E(*) 0.5 171 200 2 241 234 3.5 DO-15 STRVS248X02C(*) 0.2 171 200 2 248 238 5.0 SMC STRVS252X02F(*) 1 171 200 2 252 239 6.5 DO-201 STRVS280X02F(*) 1 188 220 2 280 263 8.5 DO-201 STRVS185X02B/E(*) Note: (*): available in october 2012 © STMicroelectronics - February 2013 - Printed in United Kingdom - All rights reserved The STMicroelectronics corporate logo is a registered trademark of the STMicroelectronics group of companies All other names are the property of their respective owners Order code: FLSTRVSPROT0313 For more information on ST products and solutions, visit www.st.com