cd00253868

AN3095
Application note
STEVAL-ISV002V1, STEVAL-ISV002V2 3 kW
grid-connected PV system, based on the STM32F103xx
Introduction
The STEVAL-ISV002V2 demonstration board is the same as the STEVAL-ISV002V1, but
assembled in a metal suitcase. In recent years, the interest in photovoltaic (PV) applications
has grown exponentially. As PV systems need an electronic interface to be connected to the
grid or standalone loads, the PV market has started appealing to many power electronics
manufacturers. Improvements in design, technology and manufacturing of PV inverters, as
well as cost reduction and high efficiency, are always the main objectives, [see References
1, 2].
This application note describes the development and evaluation of a conversion system for
PV applications with the target of achieving a significant reduction in production costs and
high efficiency. It consists of a high frequency isolated input power section performing DCDC conversion and an inverter section capable of delivering sinusoidal current of 50 Hz to
the grid. The system operates with input voltages in the range of 200 V to 400 V and is tied
to the grid at 230 Vrms, 50 Hz, through an LCL filter. Other peculiar characteristics of the
proposed converter are the integration level, decoupled active and reactive power control
and flexibility towards the source. A prototype has been realized and a fully digital control
algorithm, including power management for grid-connected operation and an MPPT
(maximum power point tracking) algorithm, has been implemented on a dedicated control
board, equipped with a latest generation 32-bit (STM32F103xx) microprocessor.
Figure 1.
November 2012
3 kW PV system image
Doc ID 16555 Rev 3
1/55
www.st.com
Contents
AN3095
Contents
1
System description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
DC-DC converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
DC-DC converter design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4
DC-AC converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5
Schematic description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6
STM32F103xx-based current control strategy for inverter grid
connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7
Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8
Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
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AN3095
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
System specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
MOSFET electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Diode rectifier electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
HF transformer specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
STGW35HF60WD electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Operating modes of grid-connected voltage source inverter . . . . . . . . . . . . . . . . . . . . . . . 38
Execution time of the main control functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
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3/55
List of figures
AN3095
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
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3 kW PV system image. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Block scheme of hardware implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DC-DC and DC-AC converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
DC-DC converter control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
DC-DC converter equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Current flow in mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Current flow in mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Current path in mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
DC-DC converter operating waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Modulation and transformer current in DCM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power transfer function for different input voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Variation of parameter “d” with input voltage for n=1.2. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Conversion systems with modified DC-AC inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Schematic of the power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Output sensing and relay board schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Schematic of the AC voltage measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Line current conditioning circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
ADC interrupt service routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
STM32F103xx microcontroller schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DC-DC converter driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
DC-AC converter driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5 V,1 A flyback converter with VIPER17HN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Multi-output flyback converter with VIPER27HN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Block diagram of the implemented control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Stationary reference frame and rotating reference frame . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Implemented PLL structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
DQ components of the current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Block diagram of the implemented MPPT algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Grid angle and Vd component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Grid angle and grid voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Grid angle (yellow), grid voltage (red), 90° phase-shifted voltage (blue) . . . . . . . . . . . . . . 46
DC-DC phase-shift modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Phase-shifted signals, transformer current in CCM, power MOSFET M1 drain current . . . 47
Power MOSFET M1- Ch1 gate signal; Ch2 drain-source voltage and drain current Ch4. . 47
Phase-shifted gate signals (Ch1, Ch2), primary and secondary transformer voltage
(Ch3, Ch4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
DC-AC voltage and current in standalone mode (open-loop operation) . . . . . . . . . . . . . . . 48
Grid voltage (blue), inverter voltage (red), injected current (green); injected power (math
function) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Inverter voltage (green) and current (blue) at 800 W,PF=0.97 . . . . . . . . . . . . . . . . . . . . . . 48
Inverter voltage (green) and current (yellow) at 2500 W, PF . . . . . . . . . . . . . . . . . . . . . . . 48
DC-DC converter efficiency at different input voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
System efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
MOSFET M1- Ch1 gate signal, Ch2 drain-source voltage and Ch 4 drain current. . . . . . . 49
Phase-shifted gate signals (Ch1, Ch2), primary and secondary transformer voltage (Ch3,
Ch4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Doc ID 16555 Rev 3
AN3095
Figure 44.
Figure 45.
List of figures
Low-side device modulation (red and blue track); high-side device modulation (yellow
track and green track) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
High-side device modulation in leg 1 (yellow track); high-side device modulation in leg 2
(green track); inverter output voltage (blue track) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Doc ID 16555 Rev 3
5/55
System description
1
AN3095
System description
A general description of the system is shown in Figure 2 with a block scheme representing
hardware implementation.
Figure 2.
Block scheme of hardware implementation
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!-V
It consists of 5 boards as listed below:
●
Main power board
●
Multi-output power supply board
●
Control and signal conditioning board
●
Output sensing and relay board
●
Input current sensing board.
The system may be completed by adding two additional boards with input and output EMI
filters which, at the moment, are not included in the final prototype.
The main power board is a dual-stage converter using DC-DC to adapt voltage levels and
impedance from the PV array and a sinusoidal PWM DC-AC to perform grid connection at
230 Vrms and 50 Hz, [see References 3]. Gate driving circuitry, input and output voltage
sensors of the DC-DC converter, as well as high frequency (HF) transformers, are also
placed on the power board. The principle reason for using a HF transformer is the galvanic
isolation provided between the PV module and the grid, to minimize the risk of hazardous
operations on the PV side caused by a fault on the grid side; voltage step-up and also
interruption of the resonance path formed by the parasitic capacitances to ground of the PV
array and the inductance of the LCL filter. Another advantage is the elimination of high
common mode currents allowing the use of unipolar pulse-width modulation for the inverter
with a consequent reduction in current harmonic content compared to bipolar pulse-width
modulation, [see References 4, 5].
Both the multi-output power supply board and control board are connected to the main
power board by means of a 34-pin connector. In this way, the connection/disconnection of
the ancillary boards is very easy and allows the separation of debug and characterization.
6/55
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AN3095
System description
The output sensing and relays board was realized to interface the power system and the
grid. This task is accomplished with the implementation of a proper control algorithm which
requires both grid-current and grid-voltage sensing. For this reason, the board is equipped
with current and voltage Hall effect sensors. Two relays, controlled by an I/O of the
microcontroller, are also placed on the same PCB to interrupt/connect phase and neutral of
the system to phase and neutral of the grid. Moreover, this board is provided with two-way
connectors for electrical wiring of the LCL filter to the main power board.
The multi-output power supply board implements two independent offline flyback
converters, with wide input voltage range, based on VIPER technology, to generate the
following output voltages:
●
+5 V to supply DC-DC converter gate drivers
●
+5 V to supply DC-AC converter gate drivers
●
+5 V to supply the microcontroller
●
+/-15 V for LEM sensors supply
●
24 V for relays supply
The main advantage of an offline solution is the availability of a power supply for circuits
dedicated to communication and data transfer even at night or in the case of weak PV field
energy production. The price to pay for such an advantage is higher power consumption
during standby mode of the main power unit.
The specifications in Table 1 for the PV system are used as inputs for the design of the
boards mentioned above. All parameters are assumed to be equal to their nominal value if
not otherwise stated.
Table 1.
System specifications
Specification
Value
DC-DC input voltage
200 V - 400 V
DC-DC output voltage
450 V
DC-AC output voltage
230 Vac
Nominal output power
3 kW
DC-AC switching frequency
17 kHz
DC-DC switching frequency
35 kHz
Transformer turns ratio
1.2
Grid voltage
230 Vrms +/- 20 %
Grid frequency
50 Hz
Power factor above 10 % rated power
>0.9
THD@ full load
<5 %
Doc ID 16555 Rev 3
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DC-DC converter
2
AN3095
DC-DC converter
The dual-stage inverter for grid-connected applications includes a DC-DC converter to
amplify the voltage and a DC-AC inverter to control the current injected into the grid.
Figure 3.
DC-DC and DC-AC converter
The DC-DC converter is depicted in Figure 3 together with the DC-AC converter and LCL
filter. The converter consists of an input capacitor, C1, six switches, M1 - M6, six
freewheeling diodes, two rectifier diodes, D1 and D2, a HF transformer with turns ratio equal
to 1.2 and a DC link capacitor C2.
The transformer provides voltage isolation between the PV array and the grid, improving
overall system safety. Its leakage inductance is used as a power transfer element,
eliminating device overvoltage problems and the need for snubber circuits. Proper phaseshift control between input bridge legs (M1-M4) and active rectifier legs (M5-M6) allows
transformer current shaping, therefore achieving ZCZVS for all the power devices, as well as
voltage step-up. The adopted phase-shift modulation is shown Figure 4.
Figure 4.
DC-DC converter control signals
VGSM1
VGSM2
VGSM5
VGSM6
AM05398v1
The same drive signal used for device M1 also controls M4, as the one controlling M3 is also
used for M2. The effect of the input bridge modulation is to generate a square wave on the
8/55
Doc ID 16555 Rev 3
AN3095
DC-DC converter
input of the HF transformer which varies between +Vin and -Vin, while the effect of the
modulation on the active rectifier is to generate, on the secondary of the HF transformer, a
square wave varying between +Vbus and -Vbus, where Vbus is the voltage on capacitor C2,
phase shifted with respect to the primary one of an angle δ, equal to the phase shift of the
modulating signals, as shown in the equivalent circuit of figures 5, 6, 7, 8, 9, 10, and 11.
Figure 5.
DC-DC converter equivalent circuit
/HDNDJHLQGXFWDQFH
7;
6,K
6BUS
6IN
!-V
As a result, the primary voltage and the secondary transformer voltage reflected to the
primary determine the rising and falling slope of the current in the leakage inductance.
According to leakage inductance current waveforms, two operating modes may be
distinguished for the converter:
●
Discontinuous current mode DCM
●
Continuous current mode CCM
Both in CCM and DCM, three main operating modes or intervals may be distinguished in
half the switching period. Considering the modulation shown in Figure 9, in CCM the
leakage inductance current may be calculated as follows:
●
Mode 1, interval (t0 - t1):
At t0 M1 and M4 are turned on at ZVS, M6 is also on. The voltage across the leakage
inductance is:
Equation 1
VLK = Vin +
Vbus
n
and the current may be written as follows:
Equation 2
iL k (t) =
d=
1
Vin (1 + d)(t − t1 ) + iLk (t 0 )
Lk
Vbus
Vin ⋅ n
Since this current is negative, as shown in Figure 9, it flows in the circuit as demonstrated in
Figure 6.
Doc ID 16555 Rev 3
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DC-DC converter
Figure 6.
AN3095
Current flow in mode 1
0
0
'
/ON
0
7;
&
&
9LQ
0
0
'
/
2
$
'
0
!-V
This mode ends when leakage inductor current reaches zero at t=t1.
●
Mode 2, interval (t1-t2):
When the leakage inductor current reaches zero, D1 and D2 turn-off with soft switching, as
the current naturally reaches zero. After t=t1 M6 is still on, primary current changes polarity
and flows through M1 and M4. On the secondary side the transformer is shorted through M6
and D2, as shown in Figure 7. Inductor current may be written as:
Equation 3
iL k (t) =
Figure 7.
(
)
1
Vin t − t1 + iLk (t 0 )
Lk
Current flow in mode 2
0
0
'
/ON
0
7;
&
&
9LQ
0
0
'
/
2
$
'
0
!-V
●
Mode 3, interval (t2-t3):
At t=t2 M6 is turned off and M5 is turned on under ZVS. A positive voltage equal to +Vbus is
applied on transformer secondary winding. Leakage inductor current is given by:
Equation 4
iL K (t) =
1
Vin (1 − d)(t − t2) + iLlk (t 2 )
Lk
The current path in the circuit is drawn in Figure 8.
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AN3095
DC-DC converter
Figure 8.
Current path in mode 3
0
0
'
/ON
0
7;
&
&
0
0
'
/
2
$
'
0
!-V
Figure 9.
DC-DC converter operating waveforms
t0 t1 t2
t3 t4 t5
t6 t0
M1,M4
M2,M3
M5
M6
IM1,IM2
IM3,IM4
Vpri, V’bus
ILK.
IM5,IM6
ID1
ID2
AM05603v1
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DC-DC converter
AN3095
Due to symmetry during the two halves of the switching period, current expressions and
current paths may be derived with similar considerations for the second half of the switching
period.
If d >1 the current in the leakage inductor may reach zero and there is a boundary between
CCM and DCM.
In DCM there are also three modes of operation, as shown in Figure 10.
●
Mode 1, interval t0-t1:
At t=t0 inductor current is zero. After t=t0 devices M1and M4 are turned on under zero
current and inductor current rises according to the following equation:
Equation 5
iL k (t) =
(
)
1
Vin t − t1 + iLk (t )
Lk
Figure 10. Modulation and transformer current in DCM
t0
t1
t2
t3
AM05604v1
●
Mode 2, interval t1-t2:
At t1 M6 turns off and M5 turns on with zero current. Inductor current expression is given by:
Equation 6
iL K (t) =
1
Vin (1 − d)(t − t 2 ) + iLlk (t 2 )
Lk
and reaches zero at t=t3.
●
Mode 3, t2-t3
Equation 7
iL K (t) = 0
The boundary between DCM and CCM depends on the phase-shift angle, input voltage,
output voltage and transformer turns ratio and is given by:
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DC-DC converter
Equation 8
φB =
d −1
π
d
By integrating the leakage current expression over the switching period and multiplying the
result by the input voltage value the expression of power transfer may be derived as:
Equation 9
⎧
⎪P =
⎪
⎪
⎨
⎪
⎪P =
⎪⎩
Vin2
d
φ2
ωsL k 2π(d − 1)
φ < φB
Vin2
d
⋅ F(φ)
ωsL k 2(2 + d)2
φ > φB
where ωs=2πfs is the switching frequency in rad/s, φ=ωst is the phase-shift angle and
F(φ) = π(1 + d − 2d 2 ) + 4φ(1 + d + d 2 ) − 2
φ2
.
(2 + 2d + d 2 )
π
once the operation of the converter has been described, based on the specification in
Table 1, the power transfer function may be plotted as shown in Figure 11.
Figure 11. Power transfer function for different input voltages
0OWERTRANSFERFUNCTIONWITH6IN666
0OWER;7=
0HASESHIFTANGLE;RAD=
!-V
As the converter operates in boost mode the value of parameter “d” must be kept greater
than “1” for every value of input voltage in order to maintain controllability, also at low power
levels. In fact, if d<1 the converter is characterized by a minimum power level under which
the converter cannot be controlled. For this reason, transformer turns ratio has been chosen
at equal to 1.2. The value of leakage inductance must also be chosen carefully and it is a
compromise between peak current value and the maximum energy transfer between input
and output.
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DC-DC converter
AN3095
Figure 12. Variation of parameter “d” with input voltage for n=1.2
6ARIATIONOFDWITH6INFORN
0ARAMETERD
)NPUT6OLTAGE;6=
!-V
A leakage inductance value comprised between 35 µH and 55 µH is suitable to obtain the
desired power level of 3 kW in all the input voltage range for the chosen transformer turns
ratio of 1.2.
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AN3095
3
DC-DC converter design
DC-DC converter design
After having described the operation of the DC-DC converter, the design may be completed
according to the specifications in Table 1.
●
Input power: assuming 90 % efficiency the input power is:
Equation 10
Pin =
●
Pout
= 3333 W
0.9
Maximum average input current:
Equation 11
Iin =
●
Pin
3333
=
= 16.66 A
Vin min
200
Maximum average output current:
Equation 12
Iout =
●
Pout
= 7.5 A
Vout min
Maximum input power device RMS current value:
Equation 13
1+ K + K 2
Irms = 2 Dmax Iin
3(K + 1)2
Where K=0 for triangular waveforms and K=1 for rectangular waveforms. This said, the
maximum RMS current value in DCM is:
Equation 14
Irms _ DCM = 2 Dmax Iin
1+ K + K 2
3(K + 1)
2
=2
Dmax
IIn =13.6 A
3
And assuming K=0.6 for trapezoidal current waveform in CCM:
Equation 15
Irms _ CCM = 2 Dmax Iin
●
1+ K + K 2
3(K + 1)2
= 2 Dmax IIn 1.15 = 27.2 A
Minimum input power device breakdown voltage:
Equation 16
VBrk Mos = 1.3 • VMPPT max = 1.3 * 400 = 520 V
Doc ID 16555 Rev 3
15/55
DC-DC converter design
●
AN3095
Transformer turns ratio:
As the converter operates in boost mode, to avoid problems of controllability for low power
levels, the value of parameter “d” must always be greater than one:
Equation 17
d ≥ 1→ n ≤
Vout
≤ 1.12
dVin MAX
Moreover, considering the voltage drop across the leakage inductor it is possible to operate
the converter with n=1.2 without incurring regulation problems for high input voltage values
at low power.
●
Minimum output power device breakdown voltage:
Equation 18
VBrk Mos _ OUTPUT = 1.2 • VMPPT max * n = 1.2 * 400 = 576 V
●
Power device selection:
According to the calculations above, four STW55NM60ND MOSFETs were selected for the
input bridge and also two STW55NM60NDs for the active rectifier. The main characteristics
of this MOSFET are reported in Table 2 and 3:
Table 2.
●
MOSFET electrical characteristics
[email protected]
RDSon_max
[email protected]°C
Coss
Qg
650 V
0.06 Ω
29 A
900 pF
190 nC
Rectifier diode selection:
Two STTH60L06s are selected for the diode leg. The main characteristics are shown in
Figure 3:
Table 3.
●
Diode rectifier electrical characteristics
Vf_max @150 °C IF=60 A
Vrrm
Trr_max
IF
IRM
1.4 V
600 V
85 n
60 A
10.5 A
Input capacitor value:
The input capacitor, C1, is designed to smooth the high frequency ripple at the input of the
PV array. If the current generated by the module is assumed to be constant and the current
drawn by the converter is assumed to be a pulse train, the following equation gives the value
of the input capacitance:
Equation 19
C1 >
16/55
Parray
2fs Δv array Vinmin
Doc ID 16555 Rev 3
AN3095
DC-DC converter design
where:
Parray is the PV field maximum output power, ΔVarray is the allowable peak-to-peak voltage
ripple at the input of the array, fs is the switching frequency and Vinmin is the minimum
operating value for the input voltage. Assuming 90 % efficiency for the converter and 0.1 %
of admissible peak-to-peak ripple voltage the input capacitance value is:
Equation 20
Parray
C1 >
2fs Δv array Vin min
=
3333 .33
= 1.1 mF
2 * 35000 * 0.2 * 200
Three 330 µF, 450 V electrolytic capacitors are connected in parallel at the input of the
converter to limit the effect of the high frequency ripple on the PV generator.
●
Output capacitor value:
In a similar way the value of the C2 bus capacitor may be calculated, taking the fact that the
ripple is sinusoidal at twice the grid frequency into account:
Equation 21
C2 >
Pout
3000
=
= 1.17 mF
2ωgrid Δv bus Vbus 2 * 2 * π * 50 * 9 * 450
where the peak-to-peak voltage of 9 V corresponds to a voltage ripple of 1 % of the nominal
bus voltage and the grid frequency is 50 Hz.
●
HF transformer design:
The design is based on the core geometry method. The transformer specifications are
shown in Table 4:
Table 4.
HF transformer specifications
Specification
Symbol
Value
Nominal input voltage
Vin
300 V
Maximum input voltage
Vinmax
400 V
Minimum input voltage
Vinmin
200 V
Input current
Iin
27 A
Nominal output voltage
Vout
450 V
Output current
Iout
22.5 A
Switching frequency
f
35 kHz
Efficiency
η
99 %
Regulation
α
0.15
Max operating flux density
Bm
0.15 T
Window utilization
Ku
0.3
Duty cycle
Dmax
0.5
Maximum temperature rise
Tr
70 °C
Doc ID 16555 Rev 3
17/55
DC-DC converter design
AN3095
The transformer apparent power is:
Equation 22
P0
1
+ P0 = ( + 1)V0I0 = 6061 W
η
η
Pt =
Then the electrical condition parameter calculation Ke may be evaluated:
Equation 23
( )
2
K e = 0.145 • K 2f • f 2 • Bm
10 -4
where Kf=4.44 is the waveform coefficient.
Equation 24
( )
K e = 0.145(4.44)2 (35.000)2 (0.15)2 10 -4 = 7606
Now, the core geometry parameter is calculated as:
Equation 25
Kg =
Pt
= 2.65 cm 5
2K e α
The Kg parameter of a generic transformer core is given by the following equation:
Equation 26
K gCORE =
Wa A 2cK u
MLT
Using two sets of E70/33/32s the following condition is verified:
Equation 27
K gCORE =
Wa A 2cK u
>Kg
MLT
The number of primary turns for the design flux swing is:
Equation 28
N1 =
Vinmin Dmax T
ΔB ⋅ 2 ⋅ A c
= 14 turns
The primary inductance value is:
Equation 29
L p = N2 A L = (14 ) * 12666 nH = 2.48 mH
2
and the number of secondary turns is:
Equation 30
N2 = n • N1 = 17turns
18/55
Doc ID 16555 Rev 3
AN3095
DC-DC converter design
The next step is to choose the wire size in order to realize primary and secondary windings.
At 35 kHz, current penetration depth is:
Equation 31
δ=
6.62
f
= 0.035 cm
Then, the wire diameter may be selected as follows:
Equation 32
d = 2δ = 0.07 cm
And the conductor section is:
Equation 33
AW = π
d2
= 0.0038 cm2
4
AWG21, having d=0.072 cm and a wire area of AWAWG22=0.0040 cm2, may be used for this
design. Considering a current density of J=500 A/cm2, the number of primary wires is given
by:
Equation 34
Snp =
A wp
A w AWG26
= 13.5 → choose Snp = 14
where
Equation 35
A wp =
Irms CCM
J
= 0.054 cm2
Since the AWG21 has a resistance of 420 µΩ/cm, the primary resistance is:
Equation 36
rp =
420 μΩ / cm
= 30 μΩ / cm
14
and so the value of resistance for the primary winding is:
Equation 37
Rp = N1 ⋅ 2 ⋅ MLT ⋅ rp = 13.7 mΩ
With the same procedure for the secondary winding it is:
Equation 38
A ws =
Irms _ CCM
n⋅J
= 0.045 cm 2
Sns =
A ws
= 11
A wawg21
rs =
420 μΩ / cm
= 38 μΩ / cm
11
R s = N2 ⋅ 2 ⋅ MLT ⋅ rs = 21.1 mΩ
Doc ID 16555 Rev 3
19/55
DC-DC converter design
AN3095
The total copper losses are:
Equation 39
PCu = Pp + Ps = RpI2in + R sI2s = 20.9 W
From the core loss curve of N87 material, at 100 °C, 0.15 T and 35 kHz, the selected core
has the following losses:
Equation 40
PV = 20
kW
m3
• 2 ⋅ Ve = 4 W
Where Ve=102000 mm3 is the core volume of one set of E75/33/32.
The efficiency of the transformer is:
Equation 41
24.9 ⎞
⎛
ηT = ⎜1 −
⎟ * 100 = 99.17%
⎝ 3000 ⎠
The transformer temperature rise is:
Equation 42
Tr = 0.5 ⋅ R th • (PCu + PV ) = 79.68 o C
With
Equation 43
R th = 6.4
20/55
Doc ID 16555 Rev 3
o
C
W
AN3095
4
DC-AC converter
DC-AC converter
The DC-AC inverter is a standard single-phase full bridge based on IGBTs with ultrafast copack diodes, as depicted in Figure 3. The connection to the grid is realized by means of
current control performed in DQ rotating reference frame. An LCL filter is placed between
the bridge and the grid in order to reduce the current harmonics generated by the unipolar
sinusoidal pulse-width modulation (USPWM) at 17 kHz. L filters or LC filters may also be
chosen for the application, but in the first case large values of inductance are required to
perform good high frequency noise damping and large currents through the capacitor may
arise in the second case together with high voltage harmonics. LCL filters show good
performance in terms of current harmonic reduction but they may lead to instability of the
control loop in the presence of large grid impedance. This instability is due to the presence
of extra poles introduced by the additional inductor. The problem may be solved with proper
filter design and by adding a damping resistor in series with the filter capacitor.
The value of Lf is designed in order to limit the current ripple to about 10 % of the nominal
current value according to:
Equation 44
Lf =
(V
BUS
)
− Vgrid _ pk ⋅ D
2 ⋅ Δi ⋅ fsw
=
(450 − 324 ) * 0.72 = 2.05 mH
2 * 1.3 * 17000
The filter capacitor value is designed to limit the exchange of reactive power below 5 % of
nominal active power:
Equation 45
Preactive =
Xc ≥
C≤
2
Vgrid
Xc
2
Vgrid
0.05Pn
≤ 0.05Pn
= 352.6 Ω
1
= 9 uF
ωX c
To avoid resonance problems for the filter, due to low and high order harmonics, its resonant
frequency, given by
fres =
1 Lg + L f
2π L f L g C f
, should be in a range between ten times the line
frequency and one half of the switching frequency:
Equation 46
10 * fgrid ≤ fres ≤ 0.5fsw
500 Hz ≤ fres ≤ 8.5 kHz
In fact, if the resonant frequency is too small the filter resonance increases the low
frequency harmonics and, in the same way, if it is too high it increases the harmonics
multiple of the switching frequency.
With a filter capacitor value of 3.3 µF and a grid inductor value of 2 mH the resulting
resonant frequency is 2771 Hz, which is in the specified range.
Doc ID 16555 Rev 3
21/55
DC-AC converter
AN3095
The LCL filter is effective only if proper damping is added. Passive damping, realized with a
resistor series connected to the filter capacitor was used for this application. The value of
the resistor is chosen to be one third of the impedance of the capacitor at the resonant
frequency:
Equation 47
R damp =
●
1
3 * ωres * C
= 5.8 Ω
Selection of semiconductor devices
The semiconductors selected for the DC-AC section are 600 V, 35 A IGBTs with internal fast
diodes used to minimize the effect of recovery at turn-on. The choice of IGBTs is a trade off
between cost and efficiency. The part number of the device used is STGW35HF60WD,
which shows very good performance in terms of switching losses. The electrical
characteristics of this device are shown in Table 5.
Table 5.
STGW35HF60WD electrical characteristics
Part number
STGW35HF60WD
Saturation voltage
Collector
current
VCEsat @125 °C,13 A
[email protected] °C
1.8 V
37 A
Eoff
Eon
Eoff @125 °C,15 A Eon @125 °C,15 A
360 µJ Rg=47 Ω
300 µJ Rg=56 Ω
Gate
charge
Qg
102 nC
The power losses in each IGBT may be calculated considering conduction losses, switching
losses and diode losses.
Conduction and switching losses in IGBTs may be evaluated according to the following
equations:
Equation 48
Pcond = VCE * Ipk (
1 1
1 ma
cos φ) = 9.6 W
+ ma cos φ) + R CE * I2 pk * ( +
2π 8
8 3π
Eon
fsw = 1.94 W
π
Eoff
Psw _ off =
fsw = 1.62 W
π
Psw _ on =
Where
VCE = 1.8 V
ma =
Vgrid _ pk
Vbus
=
325
= 0.72
450
cos φ = 1
R CE = 0.02 Ω
22/55
Doc ID 16555 Rev 3
AN3095
DC-AC converter
Diode losses may be evaluated according to the following equations:
Equation 49
1 ma
Pdiode _ DC = VF * Ipk * ( −
cos φ) = 1.3 W
8 3π
1
Pdiode _ RR = Irr trr Vpk fSW = 0.45 W
8
where
Equation 50
Vpk = 450 V
Irr = 5.4 A
t rr = 88 ns
The resulting total losses for the single-phase inverter are calculated below:
Equation 51
Ptot = 4(Pdiode _ DC + Pdiode _ RR + Psw _ on + Psw _ off + Pcond ) = 59.6 W
resulting in 98% theoretical efficiency for the inverter stage. A simple modification of the
control strategy, together with a different choice of power devices, may improve the
efficiency and performance of the DC-AC stage. The modified circuit is shown in Figure 13.
Figure 13. Conversion systems with modified DC-AC inverter
0
0
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The low-side power devices, Z2 and Z4, are low-drop IGBTs switching at 50 Hz according to
grid polarity while the high-side devices are MOSFETs switching at high frequency with
pulse-width modulation. Compared to the standard topology, the main advantages are lower
conduction losses of both MOSFETs and low-drop IGBTs, absence of switching losses for
the low-side devices and, eventually, the possibility of using higher switching frequencies
with a reduction of reactive components size and cost and wider bandwidth for the control
loop.
The possible implementation of this solution may be based on the use of STW55NM60ND
for the high-side and STGW35NB60SD, connected in parallel to an external SiC diode, for
the low side. A gain in efficiency between of 0.5 % and 1 % may be measured with such an
implementation.
Doc ID 16555 Rev 3
23/55
Schematic description
5
AN3095
Schematic description
The power board schematic is shown in Figure 14. The input voltage, produced by the PV
array and comprising between 200 V and 400 V, is fed to the power circuit through
connector J7. The input filter consists of 3 high voltage electrolytic capacitors and two 0.1 µF
polypropylene capacitors connected at the input of the bridge, to reduce the effects of
parasitic inductances due to cables and PCB tracks. Each of the four input power
MOSFETs, STW55NM60ND, are connected in parallel to a STTH30R06, 600 V 30 A ultrafast, soft recovery diode. This diode carries only a small amount of current during ZVS
operation of the DC-DC converter due to the relatively lower forward voltage of the MOSFET
body diode.
The power MOSFETs in the active rectifier are connected in parallel to 4.7 nF, 630VDC
polypropylene capacitors used as voltage snubbers to minimize turn-off losses.
The HF transformer is realized using two E70/33/32 cores with N87 ferrite. In a transformer
having only a primary and a secondary winding, the value of the leakage inductance is
determined by the number of turns in each of the two windings and by the spatial
arrangements of these windings. The leakage inductance increases with an increasing
number of turns and with an increasing distance between the windings. However, the spatial
arrangement of the windings cannot be chosen arbitrarily, mainly because of mechanical
restrictions introduced by the core geometry chosen for the specific application. Then, if a
high value of leakage inductance is needed, an additional coil may be added in series to the
primary or a bigger core may be selected for the transformer. The leakage inductance of the
transformer in this application is designed without an additional external coil to achieve a
more compact set-up and lower cost.
A bank of four 330 µF, 500 V electrolytic capacitors, connected in parallel, is placed on the
inverter bus to filter the 100 Hz ripple, together with a 2.2 µF, polypropylene capacitor to
filter the high frequency component generated by the DC-DC converter. The output of the
DC-DC converter is connected to J9, a two-way connector mounted on the PCB in
order to allow the independent operation of both conversion stages. For example, by
connecting an electrical load to J9 and a DC voltage source to J7 the operation of the DCDC converter may be evaluated independently from the inverter. In the same way,
connecting a DC voltage source to J9 and disabling the modulation of the DC-DC converter
the operation of the DC-AC inverter may be evaluated both in standalone or grid-connected
operation. In standalone mode of operation the system is controlled in open loop, while in
grid connection mode the system operates with closed loop control.
The full bridge inverter consists of two legs implemented with STGW35HF60WD IGBTs.
A 0.1 µF, 630VDC polypropylene capacitor (CF1, CF2) is connected across each leg. The
mid point of each leg is then reported on J8 to allow the connection of the two 1 mH
inductors used as high frequency filters together with capacitor C1 (Figure 15). This
capacitor, placed on the output sensing and relays board, is connected to the filter inductors
through a two-way connector J7, placed on the same board. The current in the filter inductor
is sensed by means of a Hall effect sensor CS1 and is used as a feedback for the control
algorithm. Also the grid voltage, sensed with LV1, is a feedback for the control algorithm and
is used for current synchronization to obtain unitary power factor.
Hall sensors provide inherent galvanic isolation between the grid and the control circuitry
and are very simple to use, requiring only a +15 V/-15 V supply voltage and a measurement
resistor. Despite these advantages, their cost is higher compared to other sensing solutions.
24/55
Doc ID 16555 Rev 3
AN3095
Schematic description
For example, a cheaper solution may be implemented using a simple voltage divider or a
shunt resistor together with an analog opto-isolator to provide galvanic isolation between the
power stage and control section. The price to pay in this case is the added complexity of the
sensing circuitry.
The physical connection to the grid is realized by means of two relays, placed on line and
neutral, which are controlled by an I/O of the control board with the STM32F103xx
microcontroller, and supplied by the 24 V bus generated by the multi-output power supply.
The feedback signals are sent to the control board by means of coaxial shielded cables
connected to J14 and J15 on the relays board.
Doc ID 16555 Rev 3
25/55
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Schematic description
AN3095
Figure 14. Schematic of the power stage
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AN3095
Schematic description
The output voltage of the sensor circuits must be adapted to the voltage range of the analog
to digital converter (ADC) of the STM32F103xx microcontroller, which is 0-3.3 V. This task is
accomplished using simple circuits based on operational amplifiers, such as the one shown
in Figure 16 for grid-voltage measurement.
Doc ID 16555 Rev 3
27/55
28/55
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Schematic description
AN3095
Figure 15. Output sensing and relay board schematic
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AN3095
Schematic description
Figure 16. Schematic of the AC voltage measurement circuit
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The circuit is supplied by the 5 V bus generated by the multi-output power supply and the
measured voltage is fed through connector J11. The output voltage of this circuit is then
equal to the sum of the measured voltage plus an offset voltage according to the following
equation:
Equation 52
Vout = Vmeas.
R11// R13
R13 // R12
+ Vcc
R12 + R11// R13
R11 + R13 / R12
Where Vmeas is the voltage on J11, Vcc is the 5 V supply voltage and Vout is the voltage on
pin 8 of the operational amplifier. The line current conditioning circuit was designed in a
similar way and the electrical scheme is shown in Figure 17:
Doc ID 16555 Rev 3
29/55
Schematic description
AN3095
Figure 17. Line current conditioning circuit
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In this case the output voltage is given by:
Equation 53
Vout =
R10
⎛ R6 ⎞
⋅ Vmeas. ⎜1 +
⎟
R10 + R8
⎝ R7 ⎠
Where: Vmeas is now the voltage output of the current sensor, having an offset of 2.5 V
generated by a TL431 configured as the voltage reference.
The same circuit in Figure 17 is used for the sensing of the DC bus voltage, PV array voltage
and PV array current.
In summary, the overall control architecture requires five feedback signals for correct
operation, input current and input voltage are used for maximum power point tracking;
inverter bus DC voltage, grid voltage and grid side current are used for grid-tied operation
and current injection. These signals are sent to the ADC inputs of the microcontroller,
according to the pin assignment of Figure 19 and sampled at 17.4 kHz (Figure 18).
Figure 18. ADC interrupt service routine
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AN3095
Schematic description
Figure 20. DC-DC converter driver
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AN3095
The outputs of the microcontroller are the PWM signals used to control the power devices in
each leg of the conversion system.
Power MOSFETs and IGBTs must be interfaced to the control circuit while maintaining
galvanic isolation. Two slightly different solutions were implemented for the DC-DC and the
DC-AC converter. In the first, a L6386 IC with a bootstrap capacitor for a floating drive
supply was selected because of the low cost and the capability of driving a high-side and a
low-side device with a single IC, therefore simplifying the layout of the board. The optoisolator receives the signal generated by the microcontroller and performs the level shifting
of this signal from 0-5 V to 0-15 V. The opto-isolator output pin is connected to the L6386
input pin. A totem pole circuit, consisting of a PNP-NPN BJT pair, connects the output of the
IC to the gate of each MOSFET, amplifying the driving current and allowing fast switching,
both at turn-on and turn-off. The +15 V supply voltage of the IC and opto-isolator is provided
by an isolated DC-DC converter, as shown in Figure 20. A similar solution was used to drive
the IGBTs in the inverter bridge. The main difference is the use of a single driver IC, TD350,
characterized by 0.75 A/1.2 A source/sink current capability and includes some dedicated
control and protection functions such as IGBT desaturation, two level turn-off and fault
detection output. The circuit implemented is shown in Figure 21.
34/55
Doc ID 16555 Rev 3
Doc ID 16555 Rev 3
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Schematic description
Figure 22. 5 V,1 A flyback converter with VIPER17HN
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Figure 23. Multi-output flyback converter with VIPER27HN
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AN3095
Schematic description
The isolated DC-DC converters used in the driver circuits are supplied by a 5 V bus
generated by an offline flyback converter, with wide input voltage, using VIPER 17HN
according to the electrical scheme of Figure 22. The circuit is capable of delivering up to 5
W and feeds the control circuitry of the main DC-DC converter, the DC-AC inverter and the
control board through 5 V voltage regulators.
In a similar way, the 24 V and +/-15 V bus is generated with a VIPER27HN device,
implementing a multi-output flyback solution.
Doc ID 16555 Rev 3
37/55
STM32F103xx-based current control strategy for inverter grid connection
6
AN3095
STM32F103xx-based current control strategy for
inverter grid connection
A single-phase grid-connected inverter, with unipolar pulse-width modulation, operates from
a DC voltage source and is characterized by four modes of operation or states. Two modes
take place during the positive load current period and two modes in the negative load
current period, as shown in Table 6.
Table 6.
Operating modes of grid-connected voltage source inverter
Mode
Z1
Z2
Z3
Z4
D3
D4
Vout
Iout
1
On
Off
Off
On
Off
Off
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Off
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Off
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Off
On
On
Off
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Off
Off
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0
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The switching patterns are defined by a control algorithm which generates the desired
outputs starting from the information provided by the feedback signals. For example,
algorithms for the grid connection are based on the use of current controllers, consisting of a
single loop or multiple loops according to the desired level of dynamics and accuracy.
Multiple-loop controllers are generally preferred, thanks both to their superior performance
and the relative ease of implementation in modern microcontrollers. With single-voltage loop
control methods, the inverter output voltage is compared with a sinusoidal reference,
proportional to the grid voltage and the generated error is then sent to the input of a current
regulator to create a sinusoidal reference for the PWM modulator. Despite its simple
implementation, this approach does not provide good regulation under non-linear loads and
is characterized by steady-state error. For these reasons, both output voltage and current
are used in control algorithms to provide better dynamic response and damping of the
resonant peak caused by the output LC or LCL filter. However, the time varying nature of the
controlled variables prevents an optimal regulation of output voltage and current. To
overcome such problems, a predictive current controller or deadbeat controller may be
implemented. The first approach, based on the assumption that a precise model of the
controlled system is available, predicts the inverter voltages required to force the measured
current to follow the reference current, but has the disadvantage of being difficult to
implement. The second method, while providing really fast dynamic response, is very
sensitive to system noise and is dependent on system parameters, [see References 12, 13,
14, 15, 16].
Recently, new methods such as the PR (proportional resonant) current control method have
been adopted to control the PV inverters with zero steady-state error and the possibility of
selective harmonic compensation with low computational effort. However, implementations
in low cost fixed-point microcontrollers have been proven to be difficult due to limited
computational capability and restricted numerical representation.
Another possible current-control method uses DQ synchronous reference frames and
provides both the advantage of zero steady-state error, thanks to the use of PI controllers,
and simple implementation.
38/55
Doc ID 16555 Rev 3
AN3095
STM32F103xx-based current control strategy for inverter grid connection
For these reasons, this method was implemented on a 32-bit ARM-based STM32F103xx
microcontroller and its performance was verified through simulations and experimental
results on the grid connected inverter.
A block diagram of the implemented control algorithm is shown in Figure 24.
Figure 24. Block diagram of the implemented control
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Every algorithm for grid-connected inverter operation is based on the estimation or direct
measurement of grid-voltage frequency and phase angle. Both parameters are fundamental
for correct operation and special care must be taken in their detection to avoid the influence
of any external noise. The detection method used in this implementation for a single-phase
inverter is based on a synchronous reference frame PLL. While in three-phase inverters the
use of DQ based PLL is quite common, for single-phase inverters, the necessity of a virtual
bi-phase system arises. In fact, to create a rotating DQ reference, starting from a stationary
frame, at least two independent phases are required. This problem is overcome with the
creation of a virtual voltage, Vβ, phase-shifted with respect to the real grid voltage, Vα, of
90°. This task may be easily accomplished with firmware. If the two voltage components Vα
and Vβ are available, the transformation from the stationary reference frame to the DQ
rotating frame is given by:
Equation 54
⎡Vd ⎤ ⎡ cos θ sin θ ⎤ ⎡ Vβ ⎤
⎢ ⎥=⎢
⎥⋅⎢ ⎥
⎣Vq ⎦ ⎣− sin θ cos θ⎦ ⎣Vα ⎦
where θ is the angle between the DQ reference frame and the stationary reference frame
(Figure 25). The reverse transformation is given by:
Equation 55
⎡ Vβ ⎤ ⎡cos θ − sin θ⎤ ⎡Vd ⎤
⎢ ⎥=⎢
⎥⋅⎢ ⎥
⎣Vα ⎦ ⎣ sin θ cos θ ⎦ ⎣Vq ⎦
Doc ID 16555 Rev 3
39/55
STM32F103xx-based current control strategy for inverter grid connection
AN3095
Figure 25. Stationary reference frame and rotating reference frame
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⎡ Vβ ⎤ ⎡Vm cos θ e ⎤
⎢ ⎥=⎢
⎥
⎣Vα ⎦ ⎣ Vm sin θ e ⎦
Then the two components on the DQ reference frame are:
Equation 57
Vd = Vm cos θ e cos θ + Vm senθ e senθ = Vm cos(θ − θ e )
Vq = −Vm cos θ e sin θ + Vm sin θ e cos θ = Vm sin(θ − θ e )
Therefore, if θ=θ e the two components are reduced:
Equation 58
Vd = Vm
Vq = 0
In order to detect the grid-voltage angle, used to perform the transformation, a PLL structure
may be used. In Figure 25, the block diagram of the PLL implemented in this application is
shown.
Figure 26. Implemented PLL structure
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STM32F103xx-based current control strategy for inverter grid connection
The grid voltage and the 90° phase-shifted voltage are used to perform the reference frame
change, or “park transformation”, and create two voltage components on the DQ reference
frame called Vd and Vq. One of the two components is controlled to zero with a PI regulator.
The output of the PI regulator is the grid frequency which may be integrated to obtain the
grid angle.
It is worth knowing that if the Vq component is controlled to zero then the Vd component
follows the grid-voltage rotation. In this case, the active power injected into the grid may be
controlled, transforming the current in the same reference frame and by acting on the
amplitude of the Id component. The Iq component must also be controlled in order to ensure
zero reactive power injection. On the contrary, if the Vq component is controlled to zero in
the PLL, the active power is controlled with the Iq current component and the Id current
component is used to control the reactive power to zero or to the desired value.
This said, the advantages of such a control structure are clear: first of all the current
components on the synchronous reference frame are constants and may then be controlled
with standard PI regulators ensuring zero steady-state error; the second advantage is a
decoupled control of active and reactive power.
The reference values for the active and reactive component of the current are set by two
additional PI regulators in the outer control loop. The active reference current component is
generated by confronting the DC bus voltage with the reference voltage value. The error
between the actual value and the reference DC bus voltage is sent to a PI regulator whose
output is the active current component value (Figure 26).
Similarly, the reactive current reference value is set by another PI regulator whose input is
the error generated between the reactive power command and the actual estimated value.
Figure 27. DQ components of the current
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The difference between reference components of the current and the actual DQ
components are the inputs of the PI regulators in the inner control loop. The outputs of the
PI regulators in the inner loop are two voltage components, Vd and Vq. By performing a
reverse park transformation, two AC voltages are generated back to the stationary reference
frame, and therefore the generation of the modulating signals of the DC-AC converter may
be executed by the microcontroller.
The amount of power injected into the grid depends on the power available from the PV
array. This power is then processed by the DC-DC converter which is controlled in order to
maximize the energy yield from the array, independent to temperature variations and
irradiation conditions, by controlling its input impedance. The control of the input impedance
requires both PV array current and voltage sensing and some simple calculations executed
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STM32F103xx-based current control strategy for inverter grid connection
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by the well known maximum power point algorithm. The main functions of the MPPT
algorithm are shown in Figure 28.
Figure 28. Block diagram of the implemented MPPT algorithm
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The block diagram is an explanation of the perturb and observe (P and O) method, a very
common and easy way to implement an MPPT technique. The PV array voltage is
compared to a constant reference voltage, which corresponds, once the algorithm has
reached the convergence, to the PV array voltage at the maximum power point, under
specific atmospheric and temperature conditions. The error signal is used as the input of a
PI regulator which generates a command (phase-shift angle) used to drive the power
devices of the DC-DC converter. The reference voltage is the output of the flow chart of
Figure 27 where, based on the calculation of PV output power by sampling input voltage and
current values, the power change is detected, by comparing the present and previous
voltage levels, together with the change of the input voltage. Therefore, the reference
voltage is incremented or decremented according to both array power and voltage change,
[see References 17, 18].
Apart from gird connection and MPPT, some other functions are implemented for the correct
operation of the conversion system. The following is a brief description of these functions:
●
Input voltage control
Input voltage value is constantly monitored to ensure that the array voltage is always in the
correct operating range, between 200 V and 400 V. The voltage value is also utilized to
minimize the conversion ratio between the input and output of the DC-DC converter. For
example, if the input voltage is between 200 V and 250 V the output voltage is regulated at
400 V. For higher input voltage values the reference bus DC voltage is regulated at 450 V. In
this way, the conversion ratio for the DC-DC converter is minimized and the efficiency
improved. If the input voltage value is below 200 V or above 400 V, the input
under/overvoltage protection is enabled. Consequently, the modulation is disabled in both
stages and the relays disconnect the system from the grid. For the sake of security the
complementary pairs must be disabled synchronously in case of power stage failure/fault
and this is performed by a dedicated emergency stop input embedded in the peripheral.
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STM32F103xx-based current control strategy for inverter grid connection
●
Input current control
The same kind of strategy is used to detect any condition of overcurrent in the system. This
protection is enabled when the average input current is above 18 A.
●
Bus DC voltage control
The output of the bus DC is controlled in order to stabilize the inverter input voltage to the
bus DC reference voltage. The minimum DC bus voltage is a function of the peak-to-peak
AC line voltage in order to minimize total harmonic distortion (THD) of the injected current.
This limit depends on grid-voltage fluctuations and may be calculated according to the
following equation:
Equation 59
⎛
P * Zc
Vbus ref _ min = 2 ⎜ Vgrid _ max + dc
⎜
Vgrid _ max
⎝
⎞
⎟
⎟
⎠
where Pdc is the average power on the DC bus, Vgrid_max is the maximum RMS value of the
grid voltage and Zc is the output LCL filter impedance. In other words, the DC bus must
never decrease below the peak grid-voltage value plus the drop across the IGBTs and the
LCL filter. To ensure safe operation, this voltage must never surpass the protection threshold
of 480 V.
In case of bus DC under/overvoltage the system is disconnected from the grid according to
the strategy already described.
●
Burst mode operation at startup
In the case of an overcurrent or overvoltage event, the DC-DC converter modulation is first
disabled by the control algorithm. Then, the DC-DC modulation is disabled and the interface
relays are disconnected, preventing any power flow from the system to the grid. After that,
the control algorithm performs some checks on the input voltage, bus DC voltage, gridvoltage and grid-frequency value. If the sensed voltages are in the allowable range (200-400
V input, 380-450 V bus DC, 230 Vrms +/- 10 %, 49.7 Hz-50.3 Hz grid voltage) the DC-DC
converter is started in burst mode in order to charge the bus DC voltage at the reference
voltage level. This same check procedure is executed at startup, before the connection to
the grid is actually performed. During burst mode of operation the DC bus voltage is
regulated with hysteretic control. The boundary values of the hysteresis window Vb1, Vb2
are chosen to limit the DC bus voltage ripple to 5 % of the reference value. Once the bus
capacitor is charged, the control loop mode of operation is enabled and the connection to
the grid performed.
●
Line voltage and frequency detection and anti-islanding
The PLL continuously measures the line voltage and frequency in all operating states. If the
voltage or frequency exceeds the high or low limits, the inverter ceases to deliver power to
the grid. These conditions are also used to implement a passive method for island operation
detection. An island operation occurs when the utility power is disconnected for
maintenance or fault reasons while the inverter is still delivering power. With a passive
method, detection of islanding from the utility grid is achieved via AC under/overvoltage and
under/overfrequency detection functions.
●
Output overcurrent
Due to fault conditions or AC line transient conditions, the maximum current may be
exceeded. In this case, the inverter ceases to deliver power to the grid according to the
strategy explained above. The current threshold value is set to 15 A.
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STM32F103xx-based current control strategy for inverter grid connection
●
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Open loop operation
This mode of operation was implemented to allow system debug independently from grid
operation. This mode, used for maintenance, test and debug, allows system operation only
with manual control by acting on a set of pushbuttons on the microcontroller board. The DCDC converter power transfer may be adjusted by acting on the phase-shift parameter
through the pushbutton placed on the microcontroller board. In the same way, the power
transfer of the DC-AC converter may be modified acting on the modulating index.
The dead time of the power bridges in each converter may also be adjusted.
●
LCD display
The microcontroller board is equipped with a graphic LCD display. The selectable functions
are:
1. Open-loop mode
2. Closed-loop mode
3. Calibration
4. DC-DC converter manual control
5. DC-AC converter manual control
It is important to note that the calibration function must be performed by the operator when
the system is first connected to the grid. In this way, any offset affecting the feedback signals
used for control mode operation is compensated via firmware. When the calibration function
is executed the display shows a grid current offset of about 2.5 V and a grid-voltage offset of
about 1.8 V.
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7
Experimental results
Experimental results
Control issues have been thoroughly investigated and the possibility of implementing the
algorithm using a 32-bit ARM-based microcontroller from STMicroelectronics is verified. The
dedicated control board, developed for this purpose, is equipped with an STM32F103xx
microcontroller, characterized by a 32-bit CORTEX TM-M3 core with suitable peripherals.
The core, running at 72 MHz, is able to perform up to 90 MIPS. A high performance CPU,
based on Harvard architecture, plus suitable peripherals such as two advanced PWMs, fast
and accurate 12-bit A/D conversions with double S and H circuit and high resolution timers,
allows the implementation of very sophisticated control algorithms.
The control loop has been synchronized with the A-D conversions triggered by the ON
states of the two PWM timers. This brings benefits in terms of accuracy, avoiding the
acquisition of analog quantities (e.g. currents) during commutations of the power devices.
The execution time of the most relevant tasks is reported in Table 7.
Table 7.
Execution time of the main control functions
Function
Execution time
n.5 A/D acquisitions
1 µs
MPPT
1.5 µs
DQ_PLL+internal PID
10 µs
Direct park transf
5 µs
PI regulator
3 µs each
Reverse park transf
5 µs
Sine modulation
1.5 µs
Total control loop execution time @ 72 MHz
≅ 30 µs
The entire control loop is executed in about 30 µs (50 % CPU-load) with a sampling time of
57 µs. Further code may be executed in the remaining 50 %, allowing the implementation of
a HMI (human machine interface) such as LCD driving or a graphical user interface via SPI,
in order to have a complete smart-platform.
For this application, the three main control issues regarding a PV converter, namely, MPPT,
grid synchronization and power management control, have been included within the
firmware. All the PWM signals, necessary for power management, are generated with
proper dead-time, settable with a resolution of 16.6 ns by acting on the firmware developed
for this application. The algorithm may control both the active and reactive power in the DQ
synchronous frame, while the implemented MPPT algorithm is based on the P and O
method and may be optimized with simple modifications to the source code. The inverter
current is transformed, using Park equations, in the two components referred to the rotating
DQ reference frame of the grid voltage. These components, Id and Iq, are proportional to
active and reactive generated power, respectively. The reference current value of q axis, I*q,
is calculated in order to regulate the voltage of the DC bus Vbus. Reactive power is
maintained at zero through I*d, as only the injection of active power into the mains is
allowed, according to international standards. PI outputs are transformed back into AC
quantities, using the inverse park transformation, providing the signals for inverter
modulation. The most critical task of the power management control is the estimation of the
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Experimental results
AN3095
grid angle. The required software and hardware operations of the PLL have been performed
with the same microcontroller used for the main digital control. The experimental results may
be seen in Figure 29 and 30, where the grid angle (in yellow) is drawn together with the
voltage component on the d axis (green track) of the synchronous reference frame, which is
controlled to zero. Figure 31 shows the synchronization between the estimated angle and
the two voltages on the stationary reference frame, namely, the grid voltage (red track) and
the 90° phase-shifted voltage (blue track), [see References 19, 20].
Figure 29. Grid angle and Vd component
Figure 30. Grid angle and grid voltage
Figure 31. Grid angle (yellow), grid voltage (red), 90° phase-shifted voltage (blue)
The phase-shift modulation (Figure 32) for the DC-DC stage is also implemented in the
digital control loop. The STM32F103xx microcontroller allows a high resolution phase shift
(16 ns), thanks to 16-bit timers, with a consequent advantage in terms of output voltage
regulation of the DC-DC converter. In Figure 33, the driving signals of M1 and M6 are
drawn, together with the HF transformer current in CCM and the M1 drain current under
ZVS operation. Commutation of the device M1 may be seen in Figure 34, where the control
signal is shown together with the drain source voltage and drain current at 200 V and 5 A
input. Figure 35 shows phase-shift and control signals (Ch1, Ch2), transformer primary
voltage (Ch3), and secondary voltage (Ch4).
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Experimental results
Figure 32. DC-DC phase-shift modulation
Figure 33. Phase-shifted signals, transformer
current in CCM, power MOSFET M1
drain current
Figure 34. Power MOSFET M1- Ch1 gate
signal; Ch2 drain-source voltage
and drain current Ch4
Figure 35. Phase-shifted gate signals (Ch1,
Ch2), primary and secondary
transformer voltage (Ch3, Ch4)
The PWM embedded peripheral used for the DC-AC stage is configured to generate a
triangular carrier at 17.4 kHz with a resolution of 16,6 ns and programmable dead-time
insertion to avoid cross-conduction. For the sake of security the complementary pairs must
be disabled synchronously in the case of power stage failure/fault (e.g. overcurrent) and this
is performed by a dedicated emergency stop input embedded in the peripheral.
Inverter output voltage and current are shown in Figure 36, 37, 38 and 39 at different power
levels and both in standalone and grid-connected operation. The efficiency of the DC-DC
converter and overall system is shown in Figure 40 and 41, with different values of input
voltage. Further improvements in terms of efficiency are possible using the hybrid inverter
topology (two low frequency IGBTs and two high frequency MOSFETs). In this case the
modulating strategy controlling the high-side devices (MOSFETs) and the low-side devices
(IGBTs) must be modified according to the information in Figure 42 and 43, where the
modulation used for the high-side and low-side devices is shown. The proposed converter
performs with a power factor value higher than 90 % for any power level above 1 % of
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Experimental results
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nominal output power and current THD percentage slightly higher than 5 % at 2500 W
output power, as measured in Figure 44 and 45.
Figure 36. DC-AC voltage and current in
standalone mode (open-loop
operation)
Figure 37. Grid voltage (blue), inverter voltage
(red), injected current (green);
injected power (math function)
Figure 38. Inverter voltage (green) and current Figure 39. Inverter voltage (green) and current
(blue) at 800 W,PF=0.97
(yellow) at 2500 W, PF
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Experimental results
Figure 40. DC-DC converter efficiency at
different input voltages
Figure 41. System efficiency
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Figure 42. MOSFET M1- Ch1 gate signal, Ch2 Figure 43. Phase-shifted gate signals (Ch1,
drain-source voltage and Ch 4 drain
Ch2), primary and secondary
current
transformer voltage (Ch3, Ch4)
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Experimental results
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Figure 45.
Figure 44. Low-side device modulation (red
and blue track); high-side device
modulation (yellow track and green
track)
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High-side device modulation in leg
1 (yellow track); high-side device
modulation in leg 2 (green track);
inverter output voltage (blue track)
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8
Conclusions
Conclusions
This application note describes the design and performance of a power conversion
architecture characterized by high efficiency, good integration levels and galvanic isolation,
with the aim of demonstrating STMicroelectronics’ complete and high performing product
portfolio to implement any PV conversion system. For this reason, the power converter,
based on a dual-stage topology, has been investigated and experimentally evaluated for
photovoltaic applications. The converter performs MPPT and grid connection by means of
an ARM Cortex M3-based STM32F103xx microcontroller, which is proven to be well suited
for such an application. In fact, the implemented DQ axis control scheme shows excellent
regulation of both active and reactive power, as is also required for low power applications in
the near future. Simulation and experimental results have confirmed the consistency of the
proposed solution for PV generation systems.
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References
9
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References
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
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Review of PV Inverter Technology Cost and Performance Projections, 2006, NREL
Report No. SR-620-38771
The 4th edition of Solar Generation - a publication in cooperation between The
European Photovoltaic Industry Association and Greenpeace. September 2007
“A review of single-phase grid-connected inverters for photovoltaic modules”, IEEE
Transactions on Industry Applications, vol. 41, n. 5, sept/oct. 2005, pp. 1292-1306
“Developing a 'next generation' PV inverter,” in Proc. 29th IEEE Photovolt. Spec. Conf.,
May 19-24, 2002, pp. 1352-1355
“A High Gain Transformer-Less DC-DC Converter for Fuel-Cell Applications”, 36th
IEEE Power Electronics Specialists, Conference, 11-14 Sept. 2005, p. 2514 - 2520
“High-frequency link inverter for fuel cells based on multiple-carrier PWM”, IEEE
Transactions on Power Electronics volume 19, issue 4, sept. 2004 pp:1279 - 1288
“Performance characterization of a high-power dual active bridge DC-to-DC converter”,
IEEE Transactions on Industry Applications; volume 28, Issue 6, Nov.-Dec. 1992
pp:1294 - 130
“Comparison study of phase-shifted full bridge ZVS converters”, IEEE 35th Power
Electronics Specialists Conference, 2004, PESC 04, volume 1, pp: 533 - 539. 20-25
June 2004
“Performance Optimization of a High Current Dual Active Bridge with a Wide Operating
Voltage Range”, 37th IEEE Power Electronics Specialists Conference, PESC 06, 18-22
June 2006, pp:1-7
“Transformer-Coupled Multiport ZVS Bi-directional DC-DC Converter With Wide Input
Range”, IEEE Transactions on Power Electronics, volume. 23, n. 2, March 2008, pp:
771 - 781
“A Three-phase Soft-switched High-power-density DC/DC Converter for High-power
Applications”, IEEE Transactions on Industry Applications, volume 27, Issue 1, Jan.Feb. 1991 pp. 63 - 73
“A single-stage three-phase grid-connected photovoltaic system with modified MPPT
method and reactive power compensation,” IEEE Transaction on Energy Conversion,
volume 22, Issue 4, Dec. 2007, pp. 881-886
“Intelligent PV module for grid-connected PV systems”, IEEE Transaction Industrial
Electronics, vol. 53, Issue 4, Jun. 2006, pp: 1066-1073
“Photovoltaic power conditioning system with line connection”, IEEE Transaction on
Industrial Electronics, vol. 53, no. 4, Jun. 2006, pp. 1048-1054
“Overview of control and grid synchronization for distributed power generation
systems”, IEEE Transaction on Industrial Electronics, vol. 53, Issue 5, Oct. 2006, pp.
1398-1409
“Advanced grid synchronization system for power converters under unbalanced and
distorted operating conditions”, in Proc. 32nd IEEE Annual Conference, IECON06, Nov.
2006, pp: 5173 - 5178
“Optimization of perturb and observe maximum power point tracking method”, IEEE
Transactions on Power Electronics, vol. 20, no. 4, July 2005, pp. 963 - 973
“Comparison of photovoltaic array maximum power point tracking techniques”, IEEE
Transaction on Energy Conversion, vol. 22, no. 2, Jun. 2007, pp. 439-449
Doc ID 16555 Rev 3
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References
19. “Analysis and Software Implementation of a Robust Synchronizing PLL Circuit Based
on the pq Theory”, IEEE Transactions on Industrial Electronics, vol. 53, Issue 6, Dec.
2006, pp: 1919 - 1926
20. “Stability of Photovoltaic and wind turbine grid-connected inverters for a large set of
grid impedance values”, IEEE Transactions on Power Electronics, vol. 21, n. 1, Jan
2006, pp. 263-272.
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Revision history
10
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Revision history
Table 8.
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Document revision history
Date
Revision
Changes
02-Aug-2010
1
Initial release.
21-Jun-2011
2
Modified: Figure 14
Added reference to the STEVAL-ISV002V2 demonstration board on
coverpage.
08-Nov-2012
3
Modified: Figure 22 and 23
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