dm00035397

AN3961
Application note
STEVAL-IME003V1 demonstration board based on the
STHV748 ultrasound pulser
Introduction
The STEVAL-IME003V1 demonstration board is based on the STHV748, a state-of-the-art
4-channel ultrasound pulser for ultrasound imaging applications.
The output waveforms can be displayed directly on an oscilloscope by connecting the scope
probe to the relative BNCs. 16 preset waveforms are available to test the HV pulser under
varying conditions.
Figure 1. STHV748 ultrasound pulser demonstration board (STEVAL-IME003V1)
Warning:
May 2014
Before applying any voltage supply to the STEVAL-IME003V1,
please read carefully the instructions contained in this
document.
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Contents
AN3961
Contents
1
Board features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Getting started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
3
Programming waveform description, flagged by LED (D6-D9) . . . . . . . . . 5
Hardware layout and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2
MCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3
SPI Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4
FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.1
4
Stored patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.5
STHV748 stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.6
Operating supply conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.1
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.2
MCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.3
SPI Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.4
FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5
Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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AN3961
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
STHV748 ultrasound pulser demonstration board (STEVAL-IME003V1). . . . . . . . . . . . . . . 1
Scheme of program “0” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Scheme of program “1” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Scheme of program “2” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Scheme of program “3” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Scheme of program “4” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Scheme of program “5” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Hardware block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
STEVAL-IME003V1 board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Acquisition by program “0” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Acquisition by program “1” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Acquisition by program “2” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Acquisition by program “3” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Acquisition by program “4” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Acquisition by program “5” CHA/C/D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Acquisition by program “5” CHB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
STHV748 single channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Power supply connector J4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Power supply connector J1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Power supply connector J2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Power supply connector J3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
USB mini-B connector (CN1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
SWD (J40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Memory expansion connector (J10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
STHV748 I/O connector (J6) not mounted on the board . . . . . . . . . . . . . . . . . . . . . . . . . . 34
STEVAL-IME003V1 hierarchical blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
STEVAL-IME003V1 FPGA bank 0 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
STEVAL-IME003V1 FPGA bank 1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
STEVAL-IME003V1 FPGA bank 2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
STEVAL-IME003V1 FPGA bank 3 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
STEVAL-IME003V1 FPGA bank 3 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
STEVAL-IME003V1 FPGA power and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
STEVAL-IME003V1 STHV748 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
STEVAL-IME003V1 STM32 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
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Board features
1
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AN3961
Board features
•
STHV748 ultrasound pulser with integrated T/R switch
•
4 monolithic channels, 5-level high-voltage pulser
•
On-board equivalent piezoelectric load implemented by means of:
–
R/C equivalent network
–
SMD landing areas available for a customized output load
•
USB interface available to upload customized output waveforms
•
4 Mb serial Flash memory available for storing customized waveforms
•
Memory expansion connector is available to expand serial Flash size
•
High voltage and low voltage connectors to power the STHV748
•
25 LEDs to check the board status and proper operation
•
Human machine interface to select, start and stop the stored output waveforms
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2
Getting started
Getting started
To use the STEVAL-IME003V1, perform the following steps:
2.1
1.
Connect the power supply to the board (see Section 3.1).
2.
Connect the BNC to the oscilloscope.
3.
Check that switch SW1 is set to the FPGA position.
4.
Check that the LED indicator DONE (D23) turns on.
5.
Check that FPGA is in the idle state (LED D4 is on).
6.
Select the waveform with the PROGRAM button. The corresponding program LED
(D6-D29) turns on.
7.
Press the START button to run the selected program; the START LED (D2) turns on.
After the program ends, the FPGA returns to the idle state (LED D4 is on).
8.
If a continuous wave program has been selected (Program “2”), the STOP button must
be pressed to stop program execution. The FPGA returns to the idle state and the
STOP LED (D3) turns on.
9.
To run the same program again, restart from step 7. To run a different program, restart
from step 6.
Programming waveform description, flagged by LED (D6-D9)
Program “0” (see Figure 2)
Note:
–
XDCR_A: pulse wave mode, TX0 switching, 5 pulses, time-period TP=400 ns and
PRF=150 µs
–
XDCR_B: pulse wave mode, TX0 switching, 5 pulses in counter phase respect to
XDCR_A, time-period TP=400 ns and PRF=150 µs
–
XDCR_C: pulse wave mode, TX1 switching, 5 pulses, time-period TP=200 ns and
PRF=150 µs
–
XDCR_D: pulse wave mode, TX1 switching, 5 pulses in counter phase respect to
XDCR_C, time-period TP=200 ns and PRF=150 µs
TX0 means H-bridge supplied by HVP/M0, while TX1 means H-bridge supplied by HVP/M1.
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Getting started
AN3961
Figure 2. Scheme of program “0”
7S QV
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35) —V
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7S QV
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Getting started
Program “1” (see Figure 3)
–
XDCR_A: pulse wave mode, TX0&TX1 (half-bridges in parallel) switching, 5
pulses, time-period TP=200 ns and PRF=150 µs.
–
XDCR_B: pulse wave mode, TX0&TX1 (half-bridges in parallel) switching, 5
pulses in counter phase respect to XDCR_A, time-period TP=200 ns and
PRF=150 µs.
–
XDCR_C: pulse wave mode, TX0&TX1 (half-bridges in parallel) switching, 5
pulses, time-period TP=100 ns and PRF=150 µs.
–
XDCR_D: pulse wave mode, TX0&TX1 (half-bridges in parallel) switching, 5
pulses in counter phase respect to XDCR_C, time-period TP=100 ns and
PRF=150 µs.
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Getting started
AN3961
Figure 3. Scheme of program “1”
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35) —V
;'&5B$
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7S QV
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35) —V
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;'&5B&
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;'&5B'
7S QV
35) —V
+90+90
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Getting started
Program “2” (see Figure 4)
–
XDCR_A: continuous wave mode, TX-CW switching, time-period TP=400 ns.
–
XDCR_B: continuous wave mode, TX-CW switching in counter-phase respect to
XDCR_A, time-period TP=400 ns.
–
XDCR_C: continuous wave mode, TX-CW switching, time-period TP=200 ns.
–
XDCR_D: continuous wave mode, TX-CW switching in counter-phase respect to
XDCR_C, time-period TP=200 ns.
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Getting started
AN3961
Figure 4. Scheme of program “2”
7S QV
+93
;'&5B$
+90
7S QV
+93
;'&5B%
+90
+93
7S QV
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7S QV
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Getting started
Program “3” (see Figure 5)
–
XDCR_A: pulse wave mode, TX0 switching, 1.5 pulses, time-period TP=400 ns
and PRF=100 µs.
–
XDCR_B: pulse wave mode, TX0 switching, 1.5 pulses, time-period TP=200 ns
and PRF=100 µs.
–
XDCR_C: pulse wave mode, TX0 switching 1 pulse and consequently TX1
switching 1 pulse, time-period TP=400 ns and PRF=100 µs.
–
XDCR_D: pulse wave mode, TX0 switching 1 pulse and consequently TX1
switching 1 pulse both in counter phase respect to XDCR_C, time-period
TP=400 ns and PRF=100 µs.
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Getting started
AN3961
Figure 5. Scheme of program “3”
7S QV
+93
35) —V
;'&5B$
+90
7S QV
+93
35) —V
;'&5B%
+90
+93
7S QV
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35) —V
;'&5B&
+90
+90
+93
;'&5B'
7S QV
+93
35) —V
+90
+90
$0Y
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Getting started
Program “4” (see Figure 6)
–
XDCR_A: 5 level mode example, STATE sequence; clamp-->HVP0-->HVM0->HVP0-->clamp (1 µs)-->HVP1-->HVM1-->HVP1-->HVM1-->HVP1-->HVM1->HVP1-->HVM1-->clamp, Tp=200 ns and PRF=150 µs.
–
XDCR_B: 5 level mode example, STATE sequence; clamp-->HVM0-->HVP0->HVM0-->clamp (1 µs)-->HVP1-->HVM1-->HVP1-->HVM1-->HVP1-->HVM1->HVP1-->HVM1-->clamp, Tp=200 ns and PRF=150 µs.
–
XDCR_C: 5 level mode example, STATE sequence; clamp-->HVP0-->HVM0->HVP0-->clamp (1 µs)-->HVP1-->HVM1-->HVP1-->HVM1-->HVP1-->HVM1->HVP1-->HVM1-->clamp, Tp=100 ns and PRF=150 µs.
–
XDCR_D: 5 level mode example, STATE sequence; clamp-->HVM0-->HVP0->HVM0-->clamp (1 µs)-->HVP1-->HVM1-->HVP1-->HVM1-->HVP1-->HVM1->HVP1-->HVM1-->clamp, Tp=100 ns and PRF=150 µs.
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Getting started
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Figure 6. Scheme of program “4”
+93
35) —V
+93
—V
;'&5B$
7S QV
+90
7S QV
+90
+93
35) —V
+93
—V
;'&5B%
7S QV
+90
7S QV
+90
+93
35) —V
+93
—V
;'&5B&
7S QV
+90
7S QV
+90
+93
35) —V
+93
—V
;'&5B'
7S QV
+90
7S QV
+90
$0Y
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Getting started
Program “5” (see Figure 7)
–
XDCR_A: Short pulses mode example, STATE sequence; TX0 switching, Clamp -> HVP0 (10 ns) --> Clamp --> HVP0 (20ns) --> Clamp --> HVP0 (30 ns) -->
Clamp --> HVM0 (10 ns) --> Clamp -->HVM0 (20 ns) --> Clamp -->HVM0 (30 ns) ->Clamp, PRF=150 µs.
–
XDCR_B: Short pulses mode example, STATE sequence; TX0//TX1 switching,
Clamp --> HVP0&1 (10 ns) --> Clamp --> HVP0&1 (20 ns) --> Clamp --> HVP0&1
(30 ns) --> Clamp --> HVM0&1 (10 ns) --> Clamp -->HVM0&1 (20 ns) --> Clamp ->HVM0&1 (30 ns) -->Clamp, PRF=150 µs.
–
XDCR_C: Short pulses mode example, STATE sequence; TX1 switching, Clamp -> HVM0 (10 ns) --> Clamp --> HVM1 (20 ns) --> Clamp --> HVM1 (30 ns) -->
Clamp --> HVP1 (10 ns) --> Clamp -->HVP1 (20 ns) --> Clamp -->HVP1 (30 ns) ->Clamp, PRF=150 µs.
–
XDCR_D: Short clamp mode example, STATE sequence; TX1 switching, Clamp -> HVP1 --> Clamp (10 ns) --> HVP1 --> Clamp --> HVP1 --> Clamp (20 ns) -->
HVP1 --> Clamp --> HVP1 --> Clamp (30 ns) --> HVP1 -->clamp--> HVM1 -->
Clamp (10 ns) --> HVM1 --> clamp -->HVM1 --> Clamp (20 ns) --> HVM1 -->
Clamp --> HVM1 -->Clamp (30 ns) --> HVM1--> Clamp.
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Getting started
AN3961
Figure 7. Scheme of program “5”
W QV
W QV
W QV
+93
35) —V
;'&5B$
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W QV
W QV
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;'&5B'
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Hardware layout and configuration
Hardware layout and configuration
The hardware block diagram (Figure 8) illustrates the main connections between the
STHV748, the FPGA, the STM32F103C8T6 and the SPI Flash memory. Figure 9 shows the
location of the connectors, LEDs and features on the board.
Figure 8. Hardware block diagram
Waveform and Data
download
High voltage block
Low voltage block
HVM
FLASH
Ch. A
Ch. D
IN A
SPI
DV
VDD
IN B
S
STHV748
48
IN C
SPI
FPGA
USB
STM32
IN D
IN4
Ch B
Ch.
Ch C
Ch.
HVP
PROGRAM
START
STOP
AM10067v1
Figure 9. STEVAL-IME003V1 board layout
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Hardware layout and configuration
3.1
AN3961
Power supply
The low voltage block of the STEVAL-IME003V1 board is designed to be powered by:
•
3.3 V DC connected to J4 to supply FPGA and SPI Flash memory
•
5 V DC through USB Mini B connector to supply the STM32 and the SPI memory
The power supply is configured by setting SW1 and J41 as described in Table 1.
Table 1. Power related jumpers
Description
For normal operation mode, to supply FPGA and
SPI Flash memory
(default setting)
SW1
For update operation mode, to supply
STM32F103 and SPI Flash memory
FPGA and SPI Flash memory are supplied by DVDD (J2).
(Not mounted on PCB)
J41
Note:
The fitting of J41 can create a voltage mismatch between J4 and J2 when one of these is
not 3.3 V.
LED D26, D27 and D28 show the power supply configuration as described in Table 2.
Table 2. Power supply LED
Color
Name
Description
D26
Red
USB ON
The USB cable is connected
D27
Red
MCU
Update operation mode, to supply power to
STM32F103 and SPI Flash memory
D28
Red
FPGA
Normal operation mode, to supply power to
FPGA and SPI Flash memory.
The high voltage block of the STEVAL-IME003V1 is designed to be powered by the
following (see Table 15 for maximum rating):
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•
DVDD: logic voltage, 0 to 3 V (J2 conn.)
•
VDDP: positive supply voltage 0 to 3 V (J2 conn.)
•
VDDM: negative supply voltage -3 V to 0 (J2 conn.)
•
GND: ground (J2 conn.)
•
HVM0: TX0 high voltage negative supply (J3 conn.)
•
HVM1:TX1 high voltage negative supply (J3 conn.)
•
GND: ground (J2 conn.)
•
HVP0:TX0 High voltage positive supply (J1 conn.)
•
HVP1:TX1 High voltage positive supply (J1 conn.)
•
GND: ground (J1 conn.)
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Hardware layout and configuration
It is recommended to follow a precise power up sequence, depending on how many levels
the user selects.
3-levels, switch on:
1.
3.3 V on J4
2.
VDDP and DVDD on J2
3.
VDDM on J2
4.
HVM0 and HVM1 on J3
5.
HVP0 and HVM1 on J1
5-levels, switch on:
1.
3.3 V on J4
2.
VDDP and DVDD on J2
3.
VDDM on J2
4.
HVM0 on J3
5.
HVP0 on J1
6.
HVM1 on J3
7.
HVP1 on J1
The same care must be taken for the power down sequence. It is the reverse of the power
up sequence.
3-levels, switch off:
1.
HVP0 and HVM1 on J1
2.
HVM0 and HVM1 on J3
3.
VDDM on J2
4.
VDDP and DVDD on J2
5.
3.3 V on J4
5-levels, switch off:
1.
HVP1 on J1
2.
HVM1 on J3
3.
HVP0 on J1
4.
HVM0 on J3
5.
VDDM on J2
6.
VDDP and DVDD on J2
7.
3.3 V on J4
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Hardware layout and configuration
3.2
AN3961
MCU
The STM32F103C8T6 is dedicated to updating the waveform and the FPGA bitstream on
the SPI Flash memory. It is already pre-programmed as a DFU (device firmware upgrade)
device, and has the ability to upgrade internal and external Flash memory. The STM32F103
manages all DFU operations, such as the authentication of the product identifier, vendor
identifier, firmware version and the alternate setting number (Target ID). It is used to
upgrade the SPI Flash memory hosted on the STEVAL-IME003V1, and makes the upgrade
more secure.
Note:
See UM1083 for further details about the upgrade through DFU.
3.3
SPI Flash memory
The STEVAL-IME003V1 hosts a Micron N25Q032 (U9), which is a 32 Mbit (4 Mb x 8) serial
Flash memory with advanced write protection mechanisms. It can be accessed through a
high speed SPI-compatible bus and provides the possibility to work in XIP (“eXecution in
Place”) mode.
The N25Q032 also supports high-performance quad I/O instructions. These instructions
allow to quadruple the transfer bandwidth for read and program, and is used by the FPGA.
If the 4 Mbyte memory it is not enough to contain the data, the user can connect an external
Flash memory to the J10 connector. When the external Flash is connected, LED D29 is on
(Table 3)
Table 3. SPI Flash memory LED
D29
Color
Name
Description
Green
EXT SPI-FLASH
The external SPI-Flash module is connected
The Flash memory is configured by setting J38 as described in Table 4.
Table 4. SPI Flash memory jumper
Description
J38
3.4
J38 should be fitted to supply power to the on-board SPI Flash memory.
Default setting: Fitted.
FPGA
The STEVAL-IME003V1 includes a Xilinx Spartan®-6 XC6SLX16 FPGA which drives the
STHV478 pulser by generating a suitable sequence of digital control signals (called
“program”). The board can store 16 programs which can be individually selected. The main
features of waveforms generated by a program are summarized in Table 5.
20/46
DocID022083 Rev 3
AN3961
Hardware layout and configuration
Table 5. Program waveforms main features
Feature
Min.
Typ.
Max.
Waveform number
-
13
-
Time resolution
-
5 ns
-
Duration
40 ns
-
20.48 µs
Cycles number
1
-
255
Infinite cycle
Defined by the program
Data required to generate a program are stored in the SPI Flash memory. When the
program starts, data are downloaded from Flash memory and stored in FPGA internal RAM
blocks. Then data is managed in order to generate the high-speed STHV748 digital control
signals.
The SPI Flash also contains the FPGA configuration data (“bit stream”) which are
automatically loaded during startup and after the FPGA reset (SW5) is pressed.
The FPGA is configured by setting jumpers as described in Table 6.
Table 6. FPGA jumpers
Description
J5
J5 is used to control FPGA I/O pull-ups during configuration. It should be fitted to enable
I/O pull-ups during FPGA configuration.
Default setting: not mounted.
Force FPGA into suspend mode
J12
J13
Allow the STM32 to control FPGA suspend mode
(default setting)
J13 is used to prevent FPGA programming from configuration source.
Fitted: disable FPGA programming.
Unfitted: enable FPGA programming.
(default setting: unfitted)
Configure J35 and J36 to set up the outputs idle state as follows:
(default setting: not mounted)
J35 and
J36
High Z
Clamp / HVR_SW
High Z
Clamp
Configure J37 to connect FPGA outputs to STHV748
(default setting: not mounted)
J37
Fitted: disconnect FPGA outputs (high Z)
Unfitted: connect FPGA outputs
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46
Hardware layout and configuration
AN3961
The LEDs associated with FPGA operations are described in Table 7.
Table 7. FPGA LEDs
3.4.1
Color
Name
Description
D2
Green
START
A program is running after START button SW5 has been
pressed.
D3
Green
STOP
The STOP button SW4 has been pressed.
D4
Green
IDLE
The FPGA state machine is in the idle state.
D5
Red
ERROR
An error has occurred during FPGA state machine
execution.
D23
Green
DONE
The FPGA has been successfully configured.
D6-D29
Yellow
PROG 0-15
The corresponding program is selected.
Stored patterns
The STEVAL-IME003V1 offers the possibility to memorize 16 patterns into on-board Flash
memory in order to show the performance achievable at the pulser outputs. Six selectable
patterns already stored in the Flash memory are preset by default, available and ready to
use. A detailed description of the preset programs is listed in the tables that follow.
Table 8. Program “0“
PW 5 pulses - HV0/1=±60 V; load: 300 pF//100 Ω
22/46
Mode
Frequency
[MHz]
Number of
pulses
Initial pulse
H-bridge
PRF
Ch A
PW
2.5
5
Positive
TX0
150 µs
Ch B
PW
2.5
5
Negative
TX0
150 µs
Ch C
PW
5
5
Positive
TX1
150 µs
CH D
PW
5
5
Negative
TX1
150 µs
DocID022083 Rev 3
AN3961
Hardware layout and configuration
Figure 10. Acquisition by program “0”
Table 9. Program “1”
PW TX0 and TX1 5 pulses - HV0/1=±60 V; load: 300 pF//100 Ω
Mode
Frequency
[MHz]
Number of
pulses
Initial pulse
H-bridge
PRF
Ch A
PW
5
5
Positive
TX0 & TX1
150 µs
Ch B
PW
5
5
Negative
TX0 & TX1
150 µs
Ch C
PW
10
5
Positive
TX0 & TX1
150 µs
CH D
PW
10
5
Negative
TX0 & TX1
150 µs
Figure 11. Acquisition by program “1”
DocID022083 Rev 3
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46
Hardware layout and configuration
AN3961
Table 10. Program “2”
Continuous wave - HV1=±10 V; load: 300 pF//100 Ω
Mode
Frequency
[MHz]
Number of pulses
Initial pulse
H-bridge
Ch A
CW
2.5
Continuous wave
Positive
TX-CW
Ch B
CW
2.5
Continuous wave
Negative
TX-CW
Ch C
CW
5
Continuous wave
Positive
TX-CW
CH D
CW
5
Continuous wave
Negative
TX-CW
Figure 12. Acquisition by program “2”
Table 11. Program “3”
Pulse cancellation - HV0/1=±60 V; load: 300 pF//100 Ω
24/46
Mode
Frequency
[MHz]
Number of
pulses
ChA
PC
2.5
ChB
PC
ChC
ChD
Initial pulse
H-bridge
PRF
3 half pulse
TX0
100 µs
5
3 half pulse
TX0
100 µs
PC
2.5
2 half pulse
Positive
1 pul TX0 and 1
pul TX1
100 µs
PC
2.5
2 half pulse
Negative
1 pul TX0 and 1
pul TX1
100 µs
DocID022083 Rev 3
AN3961
Hardware layout and configuration
Figure 13. Acquisition by program “3”
Table 12. Program “4”
Five level - HV1=±40 V, HV0=±80 V; Load: 300 pF//100 Ω
Mode
Time width per level
Number of
pulses
Initial pulse
PRF
ChA
5 level
1.5 cycle, 200 ns per level @
±80 V +4 cycles, 100 ns per
level @ 40 V
1.5+4
Positive
150 µs
ChB
5 level
1.5 cycle, 200 ns per level @
±80 V +4 cycles, 100 ns per
level @ 40 V
1.5+4
Negative
150 µs
ChC
5 level
1.5 cycle, 100 ns per level @
±80 V +4 cycles, 100 ns per
level @ 40 V
1.5+4
Positive
150 µs
ChD
5 level
1.5 cycle, 100 ns per level @
±80 V +4 cycles, 100 ns per
level @ 40 V
1.5+4
Negative
150 µs
DocID022083 Rev 3
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46
Hardware layout and configuration
AN3961
Figure 14. Acquisition by program “4”
Table 13. Program “5”
Short pulses HV0/1=±60 V; load: 300 pF//100 Ω
Mode
Time width
pulse
Number of
pulses
Initial pulse
H-bridge
PRF
Ch A
SP
10 ns 20 ns
30 ns
6 (3 pos and 3
neg)
Positive
TX0
100 µs
Ch B
SP
10 ns 20 ns
30 ns
6 (3 pos and 3
neg)
Positive
TX0 & TX1
100 µs
Ch C
SP
10 ns 20 ns
30 ns
6 (3 neg and 3
pos)
Negative
TX0
100 µs
CHD
SP to zero
10 ns 20 ns
30 ns
Clamp to 0
Positive
TX0
100 µs
Figure 15. Acquisition by program “5” CHA/C/D
26/46
DocID022083 Rev 3
AN3961
Hardware layout and configuration
Figure 16. Acquisition by program “5” CHB
A customized pattern can be uploaded by the user into remaining memory slots (through the
.DFU file - see user manual UM1083), where it can be tailored to meet the test necessities
of the final application.
3.5
STHV748 stage
The STHV748 high-voltage, high-speed pulser generator features four independent
channels. It is designed for medical ultrasound applications, but can also be used for other
piezoelectric, capacitive, or MEMS transducers.
The device contains a controller logic interface circuit, level translators, MOSFET gate
drivers, noise blocking diodes, and high-power P-channel and N-channel MOSFETs as
output stages for each channel. There is also clamping-to-ground circuitry, anti-leakage, an
anti-memory effect block, a thermal sensor, and a HV receiver switch (HVR_SW), which
guarantees a strong decoupling during the transmission phase.
Moreover, the STHV748 includes self-biasing and thermal shutdown blocks (see block
diagram in Figure 17). Each channel can support up to five active output levels with two half
bridges. The output stage of each channel is able to provide ±2 A peak output current. In
order to reduce power dissipation during continuous wave mode, the peak current is limited
to 0.6 A (a dedicated half bridge is used).
Note:
For further information, please refer to the STHV748 datasheet.
The STEVAL-IME003V1 permits the user to configure the special pins of the STHV748 (see
Table 14). In order to clarify the use and the functionality of these pins, a short explanation is
provided below:
–
INT_BIAS allows the minimizing of the power consumption. If INT_BIAS=0, the
self-voltage reference is not supplied. By supplying the reference externally, the
total power consumption is reduced.
–
THSD is a thermal flag. The output stage of the THSD pin is an NMOS channel
open-drain, so it is necessary to connect the external pull-up resistance (R58, 10
kΩ) to the positive low-voltage supply (see Figure 17). If the internal temperature
surpasses 160 °C, THSD goes down and puts all the channels into HZ state. By
DocID022083 Rev 3
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46
Hardware layout and configuration
AN3961
externally forcing THSD to a positive low-voltage supply, the thermal protection is
disabled.
–
D_CTR can be used to optimize 2nd HD performance by tuning the fall
propagation delay (TDF - see the STHV748 datasheet for further details). If
D_CTR is equal to ground, TDF has the nominal value. If D_CTR is varied from 2
V to 4.2 V, TDF can be changed from -1 ns to +600 ps, with respect to the nominal
value.
–
EXPOSED-PAD is internally connected to the substrate. It can be floating or
connected to a 100 V capacitance toward ground, in order to reduce noise during
the receiving phase.
The fixed configuration of these pins is described Table 14.
Table 14. STHV748 special pin configuration
Special pins on the demo PCB
Name
Description
Status on board
INT_BIAS
(pin 64)
With INT_BIAS=1, the IC internally generates the
reference voltages on REF_HVP1/0 (pin 7, 10, 39,
42) and REF_HVM1/0 (pin 2, 15, 34, 47). These
voltages are set VDDP below HVP and VDDP
above HVM, respectively:
REF_HVM# = HVM# + VDDP REF_HVP# = HVP#
- VDDP
When INT_BIAS=0, it is required that an external
voltage is applied to REF_HVM# and REF_HVP#
pins
Active – forced to 3 V through
R57=10 kΩ
THSD
(pin 32)
Thermal shutdown pin
Active (J24 closed between 1 to 2 –
forced to 3 V through R58=10 kΩ).
The user can monitor the THSD
status on TP3 (test point).
Moreover, the user can give the
control to FPGA by shorting J24
between 2 and 3
D_CTR
(pin 16)
Delay control pin
Not active – forced directly to
ground
EXPOSED-PAD
Substrate
Not active – connected to ground
through C82=0.22 µF
28/46
DocID022083 Rev 3
AN3961
Hardware layout and configuration
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The STHV748 output waveforms can be displayed directly for each channel Ch A/B/C/D
using an oscilloscope by connecting the scope probe to the J22, J23, J25, and J26 BNC
connectors. Also, the user can select whether or not to connect the on-board equivalent
load, a 270 pF, 200 V capacitor paralleled with a 100 Ω, 2 W resistor (through J20, J21, J27,
J28). A coaxial cable can also be used to easily connect the user’s transducer. Additionally,
four more low voltage outputs are available to receive the echo transduced signal coming
from the piezo-element through HVR_SW (J16, J17, J29, J30).
The main issues in this PCB design are the capacitance values, to ensure good filtering and
an effective decoupling between the low voltage inputs (IN1, IN2, IN3, IN4, and EN for each
channel) and the HV switching signals (XDCR, HVOUT, etc.,) which is ensured by the layer
separation used.
3.6
Operating supply conditions
Table 15. DC working supply conditions
Operating supply voltages
Symbol
Parameter
Min.
Typ.
Max.
Value
VDDP
Positive supply voltage
2.7
3
3.6
V
VDDM
Negative supply voltage
-2.7
-3
-3.6
V
VDD
Positive logic voltage
2.4
3
Min (3.6,VDDP+0.3)
V
HVP0
TX0 high voltage positive supply
95
V
HVP1
TX1 high voltage positive supply
95
V
DocID022083 Rev 3
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46
Hardware layout and configuration
AN3961
Table 15. DC working supply conditions (continued)
Operating supply voltages
Note:
Symbol
Parameter
Min.
Typ.
Max.
Value
HVM0
TX0 high voltage negative supply
-95
V
HVM1
TX1 high voltage negative supply
-95
V
The high voltage pins must be HVP0 ≥ HVP1 and HVM1 ≥ HVM0
Table 16. Current consumption in CW mode, @ 5 MHz, HVP/M1
Current consumption
Symbol
30/46
Parameter
Value
IVDDP
Positive supply current
8.6
mA
IVDDM
Negative supply current
13.5
mA
IDVDD
Positive logic current
0.11
mA
IHVP1
TX1 high voltage positive supply current
14.5
mA
IHVM1
TX1 high voltage negative supply current
11
mA
DocID022083 Rev 3
AN3961
Connectors
4
Connectors
4.1
Power supply
The STEVAL-IME003V1 board must be powered by the J4, J1, J2 and J3 connectors shown
in the illustrations below.
Figure 18. Power supply connector J4
Figure 19. Power supply connector J1
Figure 20. Power supply connector J2
Figure 21. Power supply connector J3
DocID022083 Rev 3
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46
Connectors
AN3961
The correct power-up sequence is:
4.2
1.
VDDP
2.
VDDM or VDD
3.
VDD or VDDM
4.
HVM0
5.
HVP0
6.
HVM1 or HVP1
7.
HVP1 or HVM1
MCU
Figure 22. USB mini-B connector (CN1)
Table 17. USB Mini B connector pinout
Pin number
Description
1
Vbus (power)
2
DM (STM32 PA11)
3
DP (STM32 PA12)
4
N.C.
5
Ground
Figure 23. SWD (J40)
32/46
DocID022083 Rev 3
AN3961
Connectors
Table 18. JTAG/SWD connector pinout
4.3
Pin number
Description
1
MCU_3V3
2
JTMS
3
GND
4
JTCK
5
GND
6
JTDO
7
GND
8
JTDI
9
GND
10
RESET#
SPI Flash memory
Figure 24. Memory expansion connector (J10)
Table 19. Memory expansion connector pinout
Pin number
Description
1
MCU_FPGA_PROG (not used)
2
SPI MISO3
3
SPI MISO2
4
SPI CS
5
SPI MOSI
6
SPI MISO
7
SPI CLK
8
GND
DocID022083 Rev 3
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46
Connectors
AN3961
Table 19. Memory expansion connector pinout (continued)
Pin number
Description
9
3.3V
10
CHECK
Note:
This memory is mutually exclusive with on-board Flash memory; unfit J38 before plugging in
expansion memory over J10. The relevant LED (D29) will turn on.
4.4
FPGA
Figure 25. STHV748 I/O connector (J6) not mounted on the board
Table 20. STHV748 I/O connector pinout
34/46
Pin number
Description (STHV748 pin)
Pin number
Description (STHV748 pin)
1
DATAOUT9 (IN1D)
2
GND
3
DATAOUT13
4
GND
5
DATAOUT10 (IN2D)
6
GND
7
DATAOUT14
8
GND
9
DATAOUT6 (IN1C)
10
GND
11
DATAOUT15
12
GND
f13
DATAOUT7 (IN2C)
14
DATAOUT2 (IN3A)
15
DATAOUT8 (IN3C)
16
GND
17
DATAOUT5 (IN3B)
18
GND
19
DATAOUT11 (IN3D)
20
GND
21
THSD_EN
22
GND
DocID022083 Rev 3
AN3961
Connectors
Table 20. STHV748 I/O connector pinout (continued)
Pin number
Description (STHV748 pin)
Pin number
Description (STHV748 pin)
23
DATAOUT4 (IN2B)
24
GND
25
3.3V
26
DATAOUT12 (IN4)
27
CLKOUT
28
3.3 V
29
TRIGGEROUT
30
GND
31
DATAOUT0 (IN1A)
32
GND
33
DATAOUT1 (IN2A)
34
DATAOUT3 (IN1B)
DocID022083 Rev 3
35/46
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36/46
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Figure 34. STEVAL-IME003V1 STM32 configuration
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Revision history
Revision history
Table 21. Document revision history
Date
Revision
18-Aug-2011
1
Initial release.
17-Jan-2012
2
– Modified: Figure 14 and 16
– Modified pattern sequences related to Program “4”
3
– Replaced “high voltage” with “ultrasound” in the document title.
– Modified text in the Introduction, Section 1: Board features and
Section 3: Hardware layout and configuration, and made minor
text corrections throughout the document.
– Changed caption of Figure 1 to “STHV748 ultrasound pulser
demonstration board (STEVAL-IME003V1)”.
29-Apr-2014
Changes
DocID022083 Rev 3
45/46
46
AN3961
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