AN4350
Application note
High power factor LED driver with constant voltage regulation based
on HVLED815PF
Giovanni Gritti
Introduction
The EVLHVLED815W8CV demonstration board shows how to implement a high power
factor LED driver with a constant voltage regulation, using the single-stage primary side
HVLED815PF controller.
The HVLED815PF device is an integrated power controller with primary side control to
achieve the LED current regulation within ± 5%.
It also has a primary side voltage regulation and this AN shows how to reach the high power
factor with the constant voltage (CV) regulation.
The device incorporates an 800 V avalanche rated FET and fits in a standard SO-16
package. An internal start-up circuit eliminates the need for an external start circuitry
reducing the component counts/space and increases system efficiency.
Figure 1. Demonstration board - top side view
February 2014
DocID025181 Rev 1
1/34
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Contents
AN4350
Contents
1
Features and specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Circuit description and design guidelines . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
Preliminary consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2
Transformer selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3
Output voltage control - primary side regulation . . . . . . . . . . . . . . . . . . . . . 8
2.4
High power factor implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5
Output filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.6
Voltage control loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.7
System design tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3
Schematic and bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4
Transformer specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5
PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6
Test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1
Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.2
Power factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.3
Standby power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.4
Line regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.5
Harmonic distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.6
Thermal measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7
Electromagnetic compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8
Supporting material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9
2/34
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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AN4350
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Demonstration board - top side view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Voltage and current control principle (left side) and output characteristic (right side) . . . . . 5
Voltage control principle: internal schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
HPF connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Equivalent small signal voltage control loop schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Demonstration board schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Transformer specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PCB layout - top side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PCB layout - bottom side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
System efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Power factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Power dissipation at low load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Line regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Harmonic distortion at 310 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Harmonic distortion at 275 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Harmonic distortion at 200 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Harmonic distortion at 135 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Thermal test - top side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Thermal test - bottom side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
MOSFET current at IOUTmax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
MOSFET current at IOUTmax/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Steady-state condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Startup at IOUTmax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Shutdown at IOUTmax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
COMP pin at IOUTmax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Switching frequency at IOUTmax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
EMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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Features and specification
1
AN4350
Features and specification
The main features of the demonstration board are:
Output constant voltage (CV regulation)
High power factor - PF > 0.98
High efficiency - up to 88%
Primary side regulation - no optocoupler
Fully isolated output (flyback topology)
Tight output voltage regulation < ± 3%
Low total harmonic distortion - THD < 30%
Automatic self-supply (internal high voltage startup)
Minimum component count (internal Power MOSFET)
The main electrical specification requirements of the driver are summarized in the list:
Input voltage (VIN)
230 Vrms (200 - 265 Vac)
Output voltage (VOUT)
25 V
Output voltage ripple (VOUTpk-pk)
Maximum output current (IOUTMAX)
Overcurrent protection (IOUTCC)
Maximum output power (POUTMAX)
7.8 W
LED driver efficiency ()
> 0.85%
4/34
Minimum switching frequency
Reflected voltage (VR)
(FswMIN)
< 3%
310 mA
375 mA
100 kHz
100 V
DocID025181 Rev 1
AN4350
Circuit description and design guidelines
2
Circuit description and design guidelines
2.1
Preliminary consideration
The HVLED815PF controller is specifically designed to work as a constant current (CC)
LED driver with a primary side regulation (PSR) and a high power factor (HPF) capability.
As shown on the left side of Figure 2, the HVLED815PF device incorporates two control
loops: the current control loop (constant current - CC) trough the ILED pin regulates the LED
output current (ILED = IOUTCC) and the voltage control loop (constant voltage - CV) trough
the COMP pin regulates the output voltage during the open-LED fault condition.
The voltage control loops can then be used to regulate the output voltage when the output
current is lower than the maximum deliverable current (IOUTCC) resulting in an output
characteristic showed on the right side of Figure 2.
Figure 2. Voltage and current control principle (left side) and output characteristic (right side)
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Starting from the standard application schematic (see Figure 1: “Application circuit for high
power factor LED driver - single range input” in the HVLED815PF datasheet for the details)
the constant current LED driver can be easily “converted” into
a constant voltage LED driver (CV) still keeping the high power factor and low total harmonic
distortion (THD).
The high power factor is implemented adding through the RPF resistor a contribution
proportional to the VIN input voltage on the CS pin: as a consequence the input current is
proportional to the input voltage during the line period, implementing the high power factor
correction.
In the CC LED driver the ROS resistor has been mainly used to add on the CS pin a positive
contribution proportional to the average value of the input voltage (VIN) in order to keep
a good line regulation. The second advantage of the contribution trough the ROS resistor is
to keep a good total harmonic distortion (THD) over the line range, because adding a small
offset on the CS pin the input current can go to zero when the input voltage is close to zero.
When implementing a CV LED driver the voltage control loop works to keep the output
voltage constant and independent from the input voltage, so the contribution proportional to
the average value of the input voltage is no more needed.
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Circuit description and design guidelines
AN4350
A small offset on the CS is still useful to keep a good THD and so it can be added using
a resistor from the VCC pin instead of a partitioning from the input voltage resulting in
a reduction of the dissipated power and the component count/size.
The VOUT output voltage is regulated through the CV loops and it has to be designed in
order to have system bandwidth much lower than current loop bandwidth (voltage loop BW
<< 100 Hz - 120 Hz); the current loop is instead used to set the maximum deliverable
current IOUTCC.
The design can be set defining an equivalent current sense resistor according to the
standard HVLED815PF equation for the output current setting:
Equation 1
R SENSE
EQ =
n V CLED
--- ------------------CC
2 I
OUT
where n is the transformer ratio between the primary (NP) and secondary side (NS), VCLED
is the internal equivalent reference voltage (VCLED = 0.2 V). See the HVLED815PF
datasheet for more details.
2.2
Transformer selection
The main parameters of the flyback transformer (LP, NP, NS, NAUX, LLK) have to be designed
in order to sustain the desiderated output voltage (VOUT), the maximum output power
(POUT), the device supply (VCC) and the desiderated reflected voltage on the primary side
(VR).
The transformer magnetization inductance (LP) is selected as a trade-off between the
maximum switching frequency (internally limited up to 166 kHz) and the maximum output
power, in according to Equation 2:
Equation 2
LP
MAX
Vin MIN
1
1
= ---------------------------------- --------------------- -----------------Vin
Fsw
2
I
MIN
MIN
1 + -----------------P
VR
where IP is the primary peak current and it can be estimated using Equation 3:
Equation 3
I P Vin Iout = I out
MAX
NP
VR
2 ------- 1 + -----------------------------
NS
VIN MIN
The ratio between the primary (NP) and secondary (NS) winding can be selected to reach
the desiderated reflected voltage (VR), using Equation 4:
Equation 4
NP
VR
VR
------- = ---------------------------- -------------NS
V OUT + V D V OUT
where VR is the desiderated reflected voltage, VD the forward voltage of the output diode.
6/34
DocID025181 Rev 1
AN4350
Circuit description and design guidelines
The VR reflected voltage is selected as a trade-off between efficiency (higher VR means
lower switching losses on the flyback Power MOSFET) and the absolute voltage on the
primary side switching node (higher VR means higher spike voltage on the Power
MOSFET's drain). Typical range of this parameter is between 70 V and 140 V.
Assuming a desiderated reflected voltage of 100 V the ratio becomes:
Equation 5
NP
VR
100V
------- = ---------------------------- = ------------------------------ = 3.87
NS
V OUT + V D
25V + 0.8V
The ratio between the auxiliary (NAUX) and primary (NP) winding has to be selected to
guarantee the supply voltage for the IC when the output voltage is regulated (during the
startup the IC supply voltage is generated by the internal high voltage startup).
Equation 6
NS
V OUT + V D
-------------- = ---------------------------V CC IC
N AUX
where typically the IC voltage is designed in the range of 17 V - 18 V (typ.).
In this design the IC voltage has been selected 15 V resulting in a higher secondaryauxiliary transformer turns ratio:
Equation 7
NS
25V + 0.8V
-------------- = ------------------------------ = 1.72
15V
N AUX
Assuming a transformer with NP = 125 T, the secondary and auxiliary winding turn results
NS = 33 T, NAUX = 19 T.
Putting the value of Equation 7 into Equation 3 and resolving the Equation 2, the maximum
transformer magnetization inductance can be estimated:
Equation 8
200V
1
1
L PMAX = ----------------------------- --------------------- --------------------------------------------------------------------------------------------------------------------- = 1.73mH
100kHz
100V
1 + 200V
--------------
310mA 2 3.87 1 + ------------------------------- 2
100V
0.85 200V
The selected magnetization inductance is LP = 1.4 mH.
The leakage inductor of the transformer should be minimized to reduce the voltage spike on
the drain node when the MOSFET is turned OFF - the maximum leakage inductor value is
typically selected < 3% of the primary magnetizing value (LLK < 3% LP).
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Circuit description and design guidelines
2.3
AN4350
Output voltage control - primary side regulation
The IC is specifically designed to work in a primary side regulation (PSR) and the output
voltage is sensed through a voltage partition of the auxiliary winding, as shown in Figure 3.
The signal on the DMG pin is sampled-and-held at the end of transformer demagnetization
to get an accurate image of the output voltage (VOUT) and it is compared with the internal
error amplifier reference voltage VREF (2.51 V typ.).
During the MOSFET's OFF-time the leakage inductance resonates with the drain
capacitance and a damped oscillation is superimposed on the reflected voltage. The internal
S/H logic is able to discriminate such oscillations from the real transformer demagnetization.
When the DMG logic detects the transformer demagnetization, the sampling process stops,
the information is frozen and compared with the error amplifier internal reference.
The internal error amplifier is a transconductance type and delivers on the COMP pin
a current proportional to the voltage unbalance of the two inputs: the COMP pin generates
the control voltage that is compared with the voltage across the sense resistor, thus
modulating the cycle-by-cycle peak drain current to regulate the desiderated output voltage.
Figure 3. Voltage control principle: internal schematic
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The COMP pin is used for the frequency compensation: typically an RC - CC network, which
stabilizes the overall voltage control loop, is connected between this pin and ground.
When implementing the high power factor (HPF - see Section 2.4: High power factor
implementation), the output voltage control loop must have frequency bandwidth much
lower than the “control current loop” (100/120 Hz, that is the double of line input frequency).
As a consequence the output voltage control loop has to be designed in order to have
bandwidth much lower than 100/120 Hz (i.e. BWCV < 5 - 10 Hz).
8/34
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Circuit description and design guidelines
Referring to the HVLED815PF datasheet, the average output voltage can be easily
programmed trough the RFB resistor, using Equation 9:
Equation 9
V REF
R FB = R DMG ------------------------------------------------------------N
AUX
-------------
N SEC V OUT – V REF
where NAUX and NSEC are the auxiliary and secondary turn numbers respectively and VREF
is the internal reference voltage (2.51 V typ.).
The RDMG resistor is designed to keep the line feed-forward and it can still be calculated as
shown in the HVLED815PF datasheet, considering the equivalent RSENSE_EQ resistor
defined in Equation 1:
Equation 10
N AUX
L P R FF
19T
1.4mH 45
R DMG = -------------- ---------------------------------------- = -------------- --------------------------------------- = 82k
T D R SENSE
NP
125T 100ns 1.08
EQ
where RFF and TD - the internal feed-forward resistor and the MOSFET turns OFF delay
time respectively. For more details see section 4.7: “Voltage feed-forward block” in the
HVLED815PF datasheet.
Using the calculated RDMG resistor, the RFB resistor can be calculated using Equation 9.
Equation 11
2.51V
R FB = 82k ---------------------------------------------------- = 17.3k
19T
---------- 25V – 2.51V
33T
2.4
High power factor implementation
Referring to Figure 4, the RPF resistor (R6 on the application schematic) gives a contribution
proportional to the input voltage on the CS pin: as a consequence the input current is
proportional to the input voltage during the line period, implementing a high power factor
correction.
In particular, the contribution proportional to the input voltage is generated using the
auxiliary winding - diode in series to the RPF resistor is needed to avoid any injection on the
CS pin when the auxiliary winding is positive.
As mentioned in Section 2.3, through the ROS resistor (the R14 resistor on the schematic
between the CS pin and VCC pin) a positive offset on the CS pin is added, in order to keep
a good THD. This offset can be designed using Equation 12:
Equation 12
R CS + R SENSE R PF
CV
V OS = V CC ------------------------------------------------------------------------------------------- = K V CS
R CS + R SENSE R PF + R OS
where VCSCV is the voltage on the CS pin that is imposed by the voltage control loop and
K is a constant that by experience is selected in the range of 2/3 - 3/4.
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Circuit description and design guidelines
AN4350
The voltage on the CS pin depends on the ratio between the delivered output current (IOUT)
and the maximum deliverable current (IOUT-CC) and so it can be estimated using Equation
13:
Equation 13
V CS
CV
VR
I OUT
I OUT = V CLED 1 + ----------------------------- -----------------------
V inRMS
I OUT – CC
where VR is the reflect voltage (VR = VOUT NP/NS), VinRMS is the RMS value of the input
voltage, is system efficiency and IOUT-CC is the maximum delivered current that can be
programmed trough the current control loop.
Assuming then RPF << RCS and RSENSE << RCS, Equation 13 can be simplified and the ROS
resistor results:
Equation 14
CV
R OS
V CC – K V CS
= ------------------------------------------------- R CS
CV
K V CS
where VCC is the IC supply voltage and it has been designed according to the secondary-toauxiliary winding ratio (see Equation 7).
The RCS resistor (R1 on the schematic in Figure 7) between the CS pin and SOURCE pin is
needed to add on the CS pin also the contribution proportional the output current trough the
RSENSE resistor.
The R1 resistor is typically selected in the range of 0.5 - 1.0 k in order to minimize the
internal feed-forward effect and to minimize the power dissipation on the RPF resistor.
Using the previous formulas the ROS resistor can be estimated:
Equation 15
R OS
3
100V
310mA
CV
15V – --- 0.2V 1 + ------------------------------- -------------------
V CC – K V CS
4
0.85 200V
375mA
- R CS = -------------------------------------------------------------------------------------------------------------------------------------------------
= ------------------------------------------------CV
3
100V
310mA
K V CS
--- 0.2V 1 + ------------------------------- -------------------
4
0.85 200V
375mA
1 k = 76.8k
The capacitor between the CS pin and ground could be useful when the transformer
leakage inductor cannot be minimized (voltage spike on the drain pin could be coupled from
the CS net).
The RPF resistor gives a contribution proportional to the input voltage and it can be
estimated using Equation 16, considering the maximum input voltage:
Equation 16
R PF = R CS
10/34
V inMAX 2 R OS N AUX – V CC R CS N P – 0.75 R OS N P
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------N P 0.75 R OS + V CC R CS
DocID025181 Rev 1
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Circuit description and design guidelines
Using the calculated value of NAUX, NP, ROS and RCS the RPF resistor results:
Equation 17
R PF = 1k
265V 2 76.8k 19T – 15 1k 125T – 0.75 76.8k 125T
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- = 59k
125T 0.75 76.8k + 15V 1k
Figure 4. HPF connections
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The voltage loop changes the voltage on the CS pin to keep the output voltage regulated.
Respect to the standard circuit (no high power factor implementation trough RPF and ROS),
the contributions proportional to VIN trough the RPF resistor and the offset trough the ROS
resistor give of course a modification of the voltage across the RSENSE resistor generating
a different gain between the RSENSE and CS pin.
The VOS offset voltage is basically selected to have no input current when the input voltage
is close to zero at the minimum line condition: as a consequence the voltage across the
RSENSE resistor is basically equal to the voltage generated by the RPF resistor.
The RSENSE can be estimated imposing the equality between the two ratios, in the worstcase condition (minimum line and maximum deliverable current IOUTCC):
Equation 18
V AUX 1
R CS -------------- -------
V CS
R PF
2
------------------------------- = -------------------------------------------------R SENSE EQ
R SENSE
CV
where VAUX is the voltage present at the auxiliary winding when the MOSFET is ON:
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Circuit description and design guidelines
AN4350
Equation 19
N AUX
V AUX = V IN -------------NP
Replacing Equation 1, Equation 13, and Equation 18 in Equation 17, the RSENSE resistor
results:
Equation 20
V inRMS MIN
1
1 N AUX R CS
R SENSE = --- -------------- ----------- ---------------------- ----------------------------------------------------------NS
R PF I OUT CC
2
VR
1 + -------------------------------------------
V
MIN
inRMS
The resistors RSENSE, RFB, RDMG, ROS, RCS, RPF determine the output voltage and the
maximum deliverable current setting - suggested accuracy of these parameters is 1%.
2.5
Output filter
The output filter has to be designed to respect the output voltage ripple specification
(VOUTpk-pk). In this kind of application, the single-stage high power factor, the high
frequency ripple at the switching frequency can be neglected respect to the low frequency
ripple at double line frequency (100/120 Hz).
The output capacitor value can then be estimated using Equation 21:
Equation 21
MAX
I OUT
0.4
310mA
0.4
- = -------- ------------------------------------ = 1005F
C outMIN -------- -----------------------------------------------------PK – PK
50Hz 0.75V
fline V
OUT
For this design, three output capacitors of 330 F/64 m/35 V have been selected.
2.6
Voltage control loop compensation
As mentioned in Section 2.3 the voltage control loop must have frequency bandwidth much
lower than the “control current loop” to avoid any interaction between the two loops. The
current loop “works” at the double of line input frequency (100 - 120 Hz), resulting in
suggested voltage loop bandwidth in the range of 5 - 10 Hz (BWCV < 1/10 of current loop
bandwidth).
The small signal system voltage loop gain can be estimated considering the equivalent
schematic in Figure 5.
Equation 22
Gloop_CV(s) = Gp(s) Gc(s) = [Gpwm Gps(s)] [Gea(s) Gsh(s) Gfb]
12/34
DocID025181 Rev 1
AN4350
Circuit description and design guidelines
where the previous transfer functions are:
Gpwm is the internal PWM modulator gain (Gpwm = 0.5)
Gps(s) is the power stage transfer function (transformer and output filter)
Gfp is the feedback gain between the VOUT and DMG pin
Gsh(s) is the internal sample and hold transfer function
Gea(s) is the error amplifier transfer function (COMP pin network)
Figure 5. Equivalent small signal voltage control loop schematic
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The power stage transfer function is calculated considering the transfer function of
a standard flyback converter:
Equation 23
s
s
1 + -------------------- 1 – ---------------------
z1 ps
z2 ps
Gps s = Go ps -----------------------------------------------------------------------------s
1 + ----------------
p ps
Equation 24
R OUT
1 – dP
1 NP
Go ps = --- ------- --------------------- ---------------2 N S R SENSE 1 + d P
Equation 25
1
z1 ps = --------------------------------ESR C OUT
DocID025181 Rev 1
13/34
34
Circuit description and design guidelines
AN4350
Equation 26
N P
----- N S- R OUT 1 – d P
z2 ps = -----------------------------------------------------------------LP dP
2
2
Equation 27
1 + dP
p ps = -----------------------------------R OUT C OUT
where ESR is the equivalent output capacitor resistance and dp is the primary duty-cycle
that depends on the input and output voltage and it can be estimated with Equation 28:
Equation 28
VR
d P = ------------------------------------------V R + V inRMS
The power stage presents one pole at low frequency (this pole is basically related to the
output filter time constant), and two zeros. Note that one zero is positive, resulting in
a negative contribution on the phase margin.
Replacing the component value on Equation 25, Equation 26, Equation 27 and considering
the VinRMS_typ and IOUTMAX, the frequency singularities of the power stage result:
fp_ps = 2.6 Hz
fz1_ps = 2.5 kHz
fz2_ps = 183 kHz.
The feedback gain transfer function is the ration between the output voltage and the DMG
pin, and it is calculated using Equation 29:
Equation 29
N AUX
R FB
Gfb = -------------- --------------------------------NS
R FB + R DMG
The sample and hold transfer function can be neglected because system voltage loop
bandwidth is much lower than the system switching frequency (the pole of the sample and
hold circuitry is at higher frequency than system bandwidth BWCV << FpS&H):
Equation 30
Gsh(s) 1
Typically an RC - CC series network is connected between the COMP pin and ground to
compensate the system loops, resulting in the following error amplifier transfer function:
Equation 31
s
1 + ----------------
z ea
Gea s = Gea0 --------------------------------s
Equation 32
gm
Gea0 = -------CC
14/34
DocID025181 Rev 1
AN4350
Circuit description and design guidelines
Equation 33
1
z ea = --------------------RC CC
where gm is the transconductance gain of the internal operational transconductance
amplifier (gm = 2.2 mS typ). For more details, see the HVLED815PF datasheet - Table 5:
“Electrical characteristics”.
Inserting the Equation 22 to Equation 33 in Equation 21, the small signal system control
loop transfer function results:
Equation 34
s
s
s
1 + -------------------- 1 – --------------------- 1 + -----------------
z1 ps
z2 ps
z ea
Gloop CV s = Gloop0 ------------------------------------------------------------------------------ --------------------------------s
s
1 + ----------------
p ps
Equation 35
R OUT
1 – dP
R FB
N AUX
1 1 NP
gm
Gloop0 = --- --- ------- --------------------- ---------------- -------------- --------------------------------- --------
2 2 N S R SENSE 1 + d P N S
R FB + R DMG C C
As mentioned in Section 2.3 control voltage loop bandwidth (BWCV) has to be designed at
very low frequency (i.e. 5 - 10 Hz) to avoid the interaction with the “current loop”: as
a consequence the zeros of the power stage can be typically “neglected” because they are
at much higher frequency than system bandwidth resulting in a simplified loop gain
calculation:
Equation 36
s
1 + ----------------
z
ea
1
Gloop CV s Gloop0 --- --------------------------------s
s
1 + ----------------
p ps
Equation 35 shows the simplified voltage control loop gain formula having two pole and one
zero in the frequencies range of interest.
The external compensation network (RC, CC) introduces a pole in the origin and one zero
that can be selected to both stabilize the system voltage control loop and to obtain
desiderated system bandwidth BWCV.
Considering the control loop gain estimated in Equation 36, the RC resistor and the CC
capacitor can be programmed using the following relationships:
Equation 37
2
VR
R FB + R DMG
NS
4 C OUT R SENSE
R C BW CV ------------------------------------------------------------ ---------------------------- --------------------------------- 1 + ----------------------------- =
N AUX N P
V inRMS
gm
R FB
2
4 3 330F 1.875
33T
17.3k + 82k
100V
= 5 ---------------------------------------------------------------------- ------------------------------ ----------------------------------------- 1 + ------------------------------- = 215
2.2mS
19T 125T
17.3k
0.85 230V
DocID025181 Rev 1
15/34
34
Circuit description and design guidelines
AN4350
Equation 38
1
1
C C ----------------------------------------------------- = ---------------------------------------------------------- = 74F
R C 4 BW CV
220 4 5Hz
A capacitor between the COMP pin and ground can be also added to remove the high
frequency voltage ripple without impacting on the transfer function (i.e. adding a small
capacitor in the range of few nF).
Figure 6. Transfer function
2.7
System design tips
Starting from the estimated value using Equation 11, Equation 15, Equation 17, Equation 20,
Equation 37 and Equation 38, further fine tuning on the real LED driver board could be
necessary and it can be easily done considering that:
16/34
Decreasing the RPF resistor value, the power factor effect increases
Decreasing the ROS resistor value, the input current close to zero decreases
Decreasing the RSENSE resistor value, the maximum deliverable output current
increases
Increasing the CC compensation capacitor, the system phase margin increases and
voltage loop bandwidth decreases.
Decreasing the RC compensation resistor, the voltage loop gain/bandwidth decreases
and also the ripples on the COMP pin.
DocID025181 Rev 1
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AN4350
Schematic and bill of materials
Schematic and bill of materials
Figure 7. Demonstration board schematic
17/34
34
Schematic and bill of materials
AN4350
Table 1. Bill of materials (BOM)
Ref.
Value
Part number
Vendor
Package
Description
BD1
600 V-0.8 A
HD06-T
DIODES ® INC.
Mini DIP
Bridge rectifier
C1
47 nF
B32921C3473
EPCOS
DIP 5 x 11 x 13
Input filter capacitor
C2
68 nF
B32921C3683
EPCOS
DIP 5 x 11 x 13
Input filter capacitor
C3
1 nF
C3216X7R2J102K
TDK
SMD 1206
Snubber capacitor
C4
22 F/50 V
EEUFR1H220
Panasonic
RADIAL 5 x 11.5 VCC filter capacitor
C5
1 F
C2012X5R1E105K
TDK
SMD 0805
ILED pin filtering
C6
10 F
C2012X5R0J106M
TDK
SMD 0805
CC - compensation network
C7
1 nF
SMD 0805
CP - compensation network
C8
100 nF/25 V
SMD 0805
VCC filter capacitor
C9
NC
SMD 0805
CS pin filtering
C10
1500 pF
C12A 330 F/35 V
DE1E3KX152MN5A
Murata
B41888C7337M
EPCOS
Y2 capacitor
RADIAL 10 x 16 Output capacitor
C13
NC
SMD 1206
Output MLCC capacitor
C14
NC
SMD 1206
Output MLCC capacitor
C15
330 F/35 V
B41888C7337M
EPCOS
RADIAL 10 x 16 Output capacitor
C16
330 F/35 V
B41888C7337M
EPCOS
RADIAL 10 x 16 Output capacitor
C17
NC
C18
NC
D1
1 A/600 V
D2
D3
STTH1L06
STMicroelectronics
®
1N4148
3 A/150 V
D4
STPS3150UF
STMicroelectronics
1N4148
SMD 1206
Output MLCC capacitor
SMD 1206
Output MLCC capacitor
SMB FLAT
Snubber diode
SOD-123
Self-supply diode
SMB FLAT
Output filter diode
SOD-123
PF network diode
F1
1 A -250 V
MCMSF 1 A 250 V
MULTICOMP
DIP 4 x 8
Input fuse
L1
1.5 mH
B82145A1155J000
EPCOS
DIP 6.5 x 12
Input inductor
R1
330 k
SMD 1206
Snubber resistor
R2
2.2 - 1%
SMD 1206
RSENSE resistor
R3
15 - 1%
SMD 1206
RSENSE resistor
R4
1 k- 1 %
SMD 0805
RCS resistor
R5
17.3 k - 1%
SMD 0805
RFB resistor
R6
56 k - 1%
SMD 0805
RPF resistor
R7
220
SMD 0805
RC compensation network
R8
82 k - 1%
SMD 0805
RDMG resistor
R9
2.2
SMD 0805
VCC filtering
R10
0
SMD 0603
Optional
R11
NC
SMD 0603
Optional
18/34
DocID025181 Rev 1
AN4350
Schematic and bill of materials
Table 1. Bill of materials (BOM) (continued)
Ref.
Value
Part number
Vendor
Package
Description
R12
6.8 k
SMD 0805
Minimum load
R13
6.8 k
SMD 0805
Minimum load
R14
62 k - 1%
SMD 0805
ROS resistor
T1
SRW13EP-XxxH003 TDK
TROUGH HOLE
Flyback transformer
10-pin
U1
HVLED815PF
SO-16
STMicroelectronics
DocID025181 Rev 1
IC with integrated MOS
19/34
34
Transformer specifications
4
AN4350
Transformer specifications
Figure 8. Transformer specifications
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,668(
AN4350
5
PCB layout
PCB layout
Figure 9. PCB layout - top side
Figure 10. PCB layout - bottom side
DocID025181 Rev 1
21/34
34
Test results
6
AN4350
Test results
From Figure 11 to Figure 18 are shown the main results of the demonstration boards at
nominal line input voltage (230 Vac).
6.1
Efficiency
System efficiency is higher than 80% starting from 20% of the rated maximum load (about
70 mA) and it increases up to 88% at the maximum load.
Figure 11. System efficiency
6.2
Power factor
The power factor is higher than 0.75 starting from 20% of the rated maximum load (about
70 mA) and increases up to 0.95 at maximum load.
22/34
DocID025181 Rev 1
AN4350
Test results
Figure 12. Power factor
6.3
Standby power dissipation
The power consumption of the demonstration board in standby condition (no load) is below
300 mW.
Figure 13. Power dissipation at low load
DocID025181 Rev 1
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34
Test results
6.4
AN4350
Line regulation
The average output voltage is regulated within ± 0.8% from no load to full load.
Figure 14. Line regulation
6.5
Harmonic distortion
The demonstration board respects the EC61000-3-2 Class D specification.
Figure 15. Harmonic distortion at 310 mA
24/34
DocID025181 Rev 1
AN4350
Test results
Figure 16. Harmonic distortion at 275 mA
Figure 17. Harmonic distortion at 200 mA
Figure 18. Harmonic distortion at 135 mA
DocID025181 Rev 1
25/34
34
Test results
6.6
AN4350
Thermal measurement
All component temperatures are below 50 °C - a thermal test has been performed at
ambient temperature (25 °C).
Figure 19. Thermal test - top side
Table 2. Thermal test - top side
26/34
Label
Component
A
Input capacitor C1
B
Input inductor
C
Input capacitor C2
D
Transformer
E
Output capacitor
DocID025181 Rev 1
AN4350
Test results
Figure 20. Thermal test - bottom side
Table 3. Thermal test - bottom side
Label
Component
A
Bridge diode
B
IC HVLED815PF
C
Snubber
D
Output diode
DocID025181 Rev 1
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34
Test results
6.7
AN4350
Waveforms
Figure 21. MOSFET current at IOUTmax
CH1 (brown): rectified input voltage
CH2 (purple): MOSFET drain
CH3 (blue): MOSFET source
Figure 22. MOSFET current at IOUTmax/2
CH1 (brown): rectified input voltage
CH2 (purple): MOSFET drain
CH3 (blue): MOSFET source
28/34
DocID025181 Rev 1
AN4350
Test results
Figure 23. Steady-state condition
CH3 (blue): output voltage
CH4 (green): input current
Figure 24. Startup at IOUTmax
CH1 (brown): rectified input voltage
CH3 (blue): MOSFET source
CH4 (green): output voltage
DocID025181 Rev 1
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34
Test results
AN4350
Figure 25. Shutdown at IOUTmax
CH1 (brown): rectified input voltage
CH3 (blue): MOSFET source
CH4 (green): output voltage
Figure 26. COMP pin at IOUTmax
CH1 (brown): COMP pin
CH2 (purple): CS pin
CH3 (blue): VCC pin
30/34
DocID025181 Rev 1
AN4350
Test results
Figure 27. Switching frequency at IOUTmax
CH1 (brown): rectified input voltage (on the peak)
CH2 (purple: MOSFET source
CH3 (blue): MOSFET drain
DocID025181 Rev 1
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34
Electromagnetic compatibility
7
AN4350
Electromagnetic compatibility
The demonstration board meets the EN55015 - average limits.
Figure 28. EMI
32/34
DocID025181 Rev 1
AN4350
8
Supporting material
Supporting material
Documentation
9
ST HVLED815PF datasheet, “Offline LED driver with primary-sensing and high power
factor up to 15 W”
ST AN1059, ”Design equations of high-power-factor flyback converters based on the
L6561”
ST AN1262, “Offline flyback converters design methodology with the L6590 family”.
Revision history
Table 4. Document revision history
Date
Revision
10-Feb-2014
1
Changes
Initial release.
DocID025181 Rev 1
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AN4350
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