dm00116872

AN4496
Application note
How to get a high power factor with the HVLED815PF device
Stefano Signoria
Introduction
The standard application of the HVLED8xxPF (HVLED807PF, HVLED815PF) is a constant
current (CC) LED driver. The average output current IOUT, as described in the HVLED815PF
datasheet (section 4.5 Constant current operation), does not depend on the value or the
waveform of the input voltage VIN, then can be used in standard or high power factor
implementation.
Two methods of implementing the high power factor (HPF) based on the HVLED8xxPF
family are current in use: the current sense modulation and ILED modulation. In either case
the input voltage after rectification is not smoothed and the waveform on the bulk capacitor
is a semi-sinusoidal waveform. The voltage on the bulk capacitor, VRECT, contains
information about the phase and waveform of VIN.
With the first method, the additional circuitry in Figure 1 applies a DC offset and
a modulation, both proportional to the VRECT, to the CS pin and permits to obtain an HPF.
This solution is described in detail in 1. of Section 3.
The second one, shown in Figure 2, applies a modulation of the ILED pin proportional to the
VRECT and features HPF in a single range application (refer to the AN4129 for further
details). This application note describes how to modify the basic circuit to support wide input
range applications.
1
Figure 1. CS HPF; additional components
Figure 2. ILED HPF; additional component
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Contents
AN4496
Contents
1
2
ILED pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
DC analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2
High power factor modulation analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3
High power factor implementation in wide input range application . . . . . . 6
Designing a high PF wide range LED driver
with the HVLED815PF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1
Input specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3
Transformer design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4
Drain source breakdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5
Current sense resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6
Primary inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.7
Secondary/auxiliary turn ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.8
Feed forward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.9
OVP protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.10
AC modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3
Supporting material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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1
ILED pin
ILED pin
The ILED pin voltage (VILED) is the constant current (CC) loop reference. This voltage
divided by two is used as the reference for the MOSFET's peak drain current during the CC
regulation. An external capacitor is used for filtering the ILED pin current with an appropriate
time constants (ILED >> 1 / 2 *  * fIN).
In this configuration the peak of the drain current remains constant during the semi-period
but the tON of the primary MOSFET increases when the instantaneous input voltage
decreases and with the mains near the zero-crossing the MOSFET remains in the ON state
until the mains voltage becomes enough to source the peak drain current.
Then near the zero-crossing the mains current has a peak as in Figure 3 A.
Figure 3. ILED voltage and input current waveform
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1.1
DC analysis
With a DC input voltage (VIN) and the device working in the transition mode (TM), the
voltage on the ILED, VILED, is:
Equation 1
This voltage changes in function of mains voltage to maintain constant the output current
and VILED reaches the maximum value at the minimum mains voltage.
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ILED pin
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In case of sinusoidal mains voltage, if the input current is in phase and with the same
waveform of the input voltage (i.e.: HPF and THD > 30%), the Equation 1 becomes:
Equation 2
Where VILEDavg is the average voltage on the ILED pin, obtained by integration
(ILED >> 1 / 2 *  * fIN) of the ILED current in an external capacitor.
Figure 4 shows the calculated and measured values of the voltage VILED vs. VIN with
VR = 102 V; the measurements are made on the board EVLHVLED815W10F at VOUT
nominal (22 V, VR = 102 V). The difference between the curves, when the VIN increases, is
due to increasing of switching frequency and then greater power transferred in valley
skipping (not TM) . Figure 5 shows the calculated and measured values of the voltage VILED
vs. VIN with VR = 70 V and VR = 122 V; the measurements are made on the same board
EVLHVLED815W10F changing the number of the LED and then VOUT and VR.
Figure 4. VILED at VR = 102 V (VOUT= 22 V)
Figure 5. VILED at VR = 70 V (VOUT = 15 V)
and VILED at VR = 122 V (VOUT = 26 V)
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1.2
ILED pin
High power factor modulation analysis
A solution to obtain the high power factor and low THD, as shown in Figure 2 on page 1, is
the AC coupling of the ILED pin with the rectified voltage. In this way the average of the
voltage VILEDavg is generated by the internal loop, which regulates the average output
current, while the waveform is modulated through the voltage divider by VRECT (see
Figure 3 B).
The average output voltage of an ideal single-phase full wave rectifier is:
Equation 3
Then the AC modulation is optimal when:
Equation 4
To ensure accurate regulation, the peak voltage on the ILED pin (VILEDpeak) must be smaller
than its maximum headroom voltage VILEDx (1.5 V). From Equation 2 and Equation 4 can be
estimated the maximum reflected voltage:
Equation 5
The effect of a reflected voltage greater of VRmax is the reduction of the output current when
VIN is lower than:
Equation 6
The equivalent input resistance of the ILED pin (RinILED) is 50 K when VILEDavg = 1 V and
the voltage divider must drive the ILED pin with equivalent resistance RAC << RinILED. The
phase rotation, at the input frequency, introduced from the capacitor CAC impacts on the
power factor, then the value of the capacitor must be:
Equation 7
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ILED pin
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The selected value of VR and VINmin imposes the maximum value of:
Equation 8
Where VINmin is the minimum RMS input voltage and  is the efficiency at the VIN used in
the equation.
The correct AC modulation is obtained setting the voltage divider ratio (KAC) equal to:
Equation 9
Where Vdrp is the input drop voltage between VIN and VRECT (input bridge, input filter, fuse,
etc.).
Referring Figure 2 on page 1, because KAC is >> 1, then Rp3 can be set equal to RAC:
Equation 10
Rp1 + Rp2 = Rp3 * (KAC - 1)
1.3
High power factor implementation in wide input range
application
With the value of the components chosen in the previous paragraph, the AC modulation is
optimized at the minimum input voltage. When the voltage increases, the ILED pin average
voltage decreases, but the AC modulation increases and forces to zero the primary current
for longer time near the zero crossing (see Figure 3 B). The effect is the generation on the
input current a zero crossing distortion, that initially, reduces the harmonics (and THD) of the
flyback configuration, but when the input voltage reaches a value around 1.25 * VINmin, the
distortion begins again to increase. If is desired a THD under 20 - 25%, the ratio between
the maximum and minimum of VIN must be lower than 1.5.
In Figure 6 is presented a solution that permit to cover wide-range application with THD
under 20 - 25% and high PF. The circuitry uses in the low range (USA and Japan) a different
voltage divider ratio (KAC), than in the high range (European). The transistor Qr is used to
change the voltage divider ratio between the value KACL in the US and Japanese and KACH
in the European range.
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ILED pin
Figure 6. Pin ILED modulation circuitry for wide input voltage range application
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In the low range (88 V - 132 V) the transistor Qr is open and the circuit in Figure 6 becomes
as that in Figure 7. The value of KACL is obtained from Equation 9.
Equation 11
The sum Rp1 + Rp2 + Rps can be calculated by Equation 10 that becomes:
Equation 12
Rp1 + Rp2 + Rps = Rp3 * (KACL - 1)
Where Rp3 = RAC and Rph = Rp1 + Rp2.
Rph resistor is splitted into Rp1 and Rp2 to satisfy the maximum voltage ranting of the case,
then Rp1 = Rp2, and choosing Rps = Rp1 / 3 permits to use a high value of Rpe.
Equation 13
Rp1 = Rp2 = 3 / 7 * Rp3 * (KACL - 1);
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Rps = 1 / 7 * Rp3 * (KACL - 1)
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ILED pin
AN4496
Figure 7. Equivalent pin ILED modulation circuitry in low input voltage range
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In the high range (185 V - 265 V) the transistor Qr is saturated and the circuit in Figure 6
becomes as that in Figure 8. The value of KACH is from Equation 9:
Equation 14
Where VINminH is the high range minimum RMS input voltage and the value used for  and
Vdrp are the values at the VINminH.
The value of Rpc + Rpe to obtain the selected value of KACH the will be:
Equation 15
The resistors Rr1, Rr2 and Rr3 implement a voltage divider. In parallel to the Rr3 is placed
a capacitor Cr3 that filters the voltage ripple. When this voltage is greater than the sum of Dr
Zener voltage (VZ_Dr) and the base - emitter voltage of Qr (VBE_Qr), the transistor Qr starts
to switch on. The emitter resistor reduces the gain of Qr and permits a linear transition
between the low and the high range, that allows to work without hysteresis and reduces the
THD in the transition range (132 V -175 V).
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ILED pin
Equation 16
Where VINthL is the lower transition voltage and Rr3 << (1 + hFE_Qr) * Rpe.
Figure 8. Equivalent pin ILED modulation circuitry in high input voltage range
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The higher transition voltage (VINthL ) is determined by Rpe but the base of Qr is always
biased while the collector voltage drops near to zero and modelling is not simple.
Starting from the below estimated values and the recommended value in Section 2.10 on
page 16 further fine tuning of the final application can be done assuming that:

Decreasing/increasing the Dz Zener voltage the lower transition voltage
decreases/increases

Decreasing/increasing the Rr3 resistor value the lower and the higher transition voltage
increase/decrease

Decreasing/increasing the Rr1, Rr2 resistor value the lower and the higher transition
voltage decrease/increase

Decreasing/increasing the Rpe resistor value the spread between the lower and the
higher transition voltage decreases/increases.
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Designing a high PF wide range LED driver with the HVLED815PF
2
AN4496
Designing a high PF wide range LED driver with the
HVLED815PF
Main characteristics and circuit description
The main characteristics of the LED driver are listed here:
2.1

Universal input mains range: 88 ÷ 265 VAC

Output power 10 W continuous operation

Output current: 460 mA at 22 V continuous operation

Overall efficiency up to 85%

Power factor higher than 0.95
Input specification
The following is a possible design procedure for a high power factor LED driver using the
HVLED815PF device. This design is referred to the schematics of Figure 9. First step is to
define the design specification.
Minimum mains voltage [VAC rms]:
Equation 17
VIN min = 88 V
Maximum mains voltage [VAC rms]:
Equation 18
VIN max = 265 V
Range (wide, US or European) = WIDE; in the European range maximum output power is
15 W, in an other case must be limited to 9 - 10 W. If the mains voltage range is a single
range, the switch range network can be omitted (R13, D4, D7, Q2, R21, R20, R4). In a wide
mains voltage range the network switches smoothly between the US range and European
range.
Minimum mains frequency [Hz]:
Equation 19
FIN min = 47 Hz
Mean output current [mA]:
Equation 20
IOUT = 460 mA
Output current ripple [%]:
Equation 21
IOUT = 140 %
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Designing a high PF wide range LED driver with the HVLED815PF
Mean output voltage [V]:
Equation 22
VOUT = 21.7 V
The mean voltage LED string drop is the output voltage.
Overvoltage protection [V]:
Equation 23
VOVP = 29 V
The output voltage VOUT has a ripple at twice the line frequency and whose amplitude is
proportional to the output current and reverse proportional to output capacitance. This
application has a high ripple voltage (due to the high power factor and small bulk capacitor).
With a mean output voltage of 22 V the peak is at 25 V.
For reliability the output capacitor has a rated voltage of 35 V.
The selected OVP threshold of 29 V is set between these two limits (the peak output voltage
and output capacitor rated voltage).
Supply voltage of the device [V]:
Equation 24
VCC = 12 V
In this design the supply voltage Vcc is low. That value is selected, because in this design
the output voltage is fixed to 22 V. A higher value of Vcc is recommended (until 18 - 21 V)
in case of application with variable output voltage [example: Iout = 460 mA,
Vout = 14 V ~ 22 V)].
The efficiency is better if the supply current is sourced from the auxiliary winding rather than
from the high voltage startup.
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Designing a high PF wide range LED driver with the HVLED815PF
AN4496
Figure 9. Schematic
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2.2
Designing a high PF wide range LED driver with the HVLED815PF
Operating conditions
The first step is to verify:
Maximum power output [W]:
Equation 25
POUT = IOUT * VOUT  POUT_MAX
2.3
In the European range (VIN min > 175 V)

POUT max < 15 W
In the US and Japanese range (VIN min < 175 V)

POUT max < 10 W.
Transformer design
The voltage at the ILED pin must be limited at 1.5 V.
Then for the best performance the optimal reflected voltage VRopt must be set for using all
the dynamics of the ILED pin at minimum mains.
Equation 26
Where:
2.4
_VINmin = 80%

efficiency at minimum input voltage
VILEDx = 1.5 V

pin ILED maximum voltage
Drain source breakdown
Reflected voltage can be limited by drain-source breakdown voltage.
Equation 27
VRbrk = V(BR)DSS - 2 * VINmax -VSpike - Vtol = 800 - 2 * 265 - 150 - 80 = 200 V
Where Vtol is a margin for the components tolerance.
The value of VR lower than VRopt and VRbrk is used to calculate the primary/secondary turns
ratio n:
Equation 28
Where VFsec = secondary diode forward drop voltage.
When VR is lower than VRopt, the dynamic is not optimized but the HVLED815PF device is
working without problem.
Real value used:
n = 4.52

VR = 100 V
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Designing a high PF wide range LED driver with the HVLED815PF
2.5
AN4496
Current sense resistor
Current sense resistor value is determined by the average LED current IOUT.
Equation 29
This formula is exact if:

The peak voltage on the ILED pin is smaller than the maximum headroom voltage for
all mains voltage range.

OVP protection is set 20% over the maximum output peak voltage.

Perfect transformer coupling.

The LED driver works in the TM mode for over an half of the semi-period.
For different designs, fine tuning may be needed, but once the final values are selected,
repeatability from unit to unit is excellent.
Real value used:
2.6
RS = 1 
Primary inductance
The primary inductance Lp sets the working frequency.
For the best regulation is better to limit the minimum frequency at maximum mains voltage
(265 V) to 90 KHz, in this way when the voltage is around the peak of the semi-period (and
the instantaneous power is higher), the LED driver operates in transition mode (TM). In wide
range application, at minimum mains voltage (88 V), this frequency drops to the minimum
fmin  40 KHz.
Equation 30
The increase fmin reduces the primary inductance and the transformer can be smaller. In this
case KRs can be used to compensate divergence of IOUT from the case with optimal
frequency.
Real value used:
14/18
LP = 1.5 mH
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2.7
Designing a high PF wide range LED driver with the HVLED815PF
Secondary/auxiliary turn ratio
The operating range of VCC is between 11.5 V and 23 V. The mid voltage is around 17 V.
The drop voltage on the limiting resistor Rlim (R9) and the auxiliary rectifier diode (D2) at the
nominal operating point is set to 1 V.
Equation 31
Vdrop AUX = VFaux + VRlim = VFaux + ICC * Rlim
Then is defined the secondary/auxiliary turn ratio.
Equation 32
Two conditions must be checked:
1.
In case of an open circuit the output voltage is a bit upper at the threshold VOUT OVP, in
this situation Rlim must limit the current to 25 mA.
Equation 33
The higher value of Rlim must be used in the design, if greater Rlim is determined for the
open circuit conditions, the secondary/auxiliary turn ratio to compensate the drop on
Rlim must be recalculated.
2.
If requested, wide range output voltage at the constant current VCC must be increased
to 21 V.
To demonstrate the high voltage startup functionality in this design VCC is lower, then:
Real value used:
2.8
NS / NAUX = 1.75

VCC = 12 V
Feed forward
Equation 34
Real value used:
Rdmg = 91 k
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Designing a high PF wide range LED driver with the HVLED815PF
2.9
AN4496
OVP protection
In Section 2.1 on page 10 the selected value VOUT_OVP = 29 V, then:
Equation 35
Real value used:
2.10
Rfb = 16k
AC modulation
To obtain the high power factor and low THD, a signal proportional to rectified mains is
applied to the ILED pin.
The other components of the network that switching the range can be calculated, but the
non-linear behavior of Qr due the modulation of the Qr collector requires a fine tuning of the
network; using the next recommended value for the components, the only value to be
calculated is R3 to optimize the modulation at 85 - 90 V.
Equation 36
With:
Rp1 = Rp2 = 180 k
Rps = 120 k
Rpc = 51 k
Rpe = 15 k
Rr1 = Rr2 = 120 k
Rr3 = 62 k
Cr3 = 4.7 µF
Dr = BZV55-C20
Qr = MMBTA42
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3
Supporting material
Supporting material
Documentation
4
1.
HVLED815PF - “Offline LED driver with primary-sensing and high power factor up to
15 W” datasheet.
2.
AN4129 - “STEVAL-ILL044V1: 9 W Triac dimmable, high power factor, isolated LED
driver based on the HVLED815PF (for US market)”.
Revision history
Table 1. Document revision history
Date
Revision
08-Sep-2014
1
Changes
Initial release.
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