chip

H
CAT93C46/56/57/66/86
EE
GEN FR
ALO
1K/2K/2K/4K/16K-Bit Microwire Serial EEPROM
LE
A D F R E ETM
FEATURES
■ High speed operation:
■ Power-up inadvertant write protection
■ 1,000,000 Program/erase cycles
– 93C46/56/57/66: 1MHz
– 93C86: 3MHz
■ 100 year data retention
■ Low power CMOS technology
■ Commercial, industrial and automotive
■ 1.8 to 6.0 volt operation
temperature ranges
■ Selectable x8 or x16 memory organization
■ Sequential read (except CAT93C46)
■ Self-timed write cycle with auto-clear
■ Program enable (PE) pin (CAT93C86 only)
■ Hardware and software write protection
■ “Green” package option available
DESCRIPTION
CMOS EEPROM floating gate technology. The devices
are designed to endure 1,000,000 program/erase cycles
and have a data retention of 100 years. The devices are
available in 8-pin DIP, 8-pin SOIC, 8-pin TSSOP and 8pad TDFN packages.
The CAT93C46/56/57/66/86 are 1K/2K/2K/4K/16K-bit
Serial EEPROM memory devices which are configured
as either registers of 16 bits (ORG pin at VCC) or 8 bits
(ORG pin at GND). Each register can be written (or read)
serially by using the DI (or DO) pin. The CAT93C46/56/
57/66/86 are manufactured using Catalyst’s advanced
PIN CONFIGURATION
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
NC (PE*)
VCC
NC (PE*)
ORG
CS
SK
GND
*Only For 93C86
1
2
3
4
8
7
6
5
ORG
GND
DO
DI
CS
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
CS
NC (PE*) SK
ORG
DI
GND
DO
1
2
3
4
8
7
6
5
VCC
NC (PE*)
ORG
GND
** TSSOP (U/Y) package only available for 93C46/56/57/66
PIN FUNCTIONS
Pin Name
TSSOP Package (U,Y)
SOIC Package (J,W) SOIC Package (S,V) SOIC Package (K,X)
DIP Package (P, L)
VCC
Clock Input
DI
Serial Data Input
DO
Serial Data Output
VCC
+1.8 to 6.0V Power Supply
GND
Ground
ORG
Memory Organization
NC
No Connection
PE*
Program Enable
Note: When the ORG pin is connected to VCC,
the x16 organization is selected. When it is
connected to ground, the x8 pin is selected. If
the ORG pin is left unconnected, then an internal
pullup device will select the x16 organization.
© 2003 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice.
8
7
DI
3
4
6
5
DO
VCC 8
NC 7
GND
ORG 6
Chip Select
SK
1
2
GND 5
ORG
MEMORY ARRAY
ORGANIZATION
VCC
NC
ORG
GND
TDFN Package (RD4, ZD4)
BLOCK DIAGRAM
Function
CS
SK
ADDRESS
DECODER
1 CS
CAT93C46
CAT93C56
CAT93C66
2 SK
3 DI
4 DO
Bottom View
DATA
REGISTER
OUTPUT
BUFFER
DI
CS
PE*
SK
MODE DECODE
LOGIC
CLOCK
GENERATOR
DO
Doc. No. 1023, Rev. J
93C46/56/57/66/86
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias .................. -55°C to +125°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Storage Temperature ........................ -65°C to +150°C
Voltage on any Pin with
Respect to Ground(1) ............. -2.0V to +VCC +2.0V
VCC with Respect to Ground ................ -2.0V to +7.0V
Package Power Dissipation
Capability (TA = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Reference Test Method
Min
NEND(3)
Endurance
MIL-STD-883, Test Method 1033
1,000,000
Cycles/Byte
TDR(3)
Data Retention
MIL-STD-883, Test Method 1008
100
Years
VZAP(3)
ESD Susceptibility
MIL-STD-883, Test Method 3015
2000
Volts
Latch-Up
JEDEC Standard 17
100
mA
ILTH
(3)(4)
Typ
Max
Units
D.C. OPERATING CHARACTERISTICS
VCC = +1.8V to +6.0V, unless otherwise specified.
Symbol
Parameter
Test Conditions
ICC1
Power Supply Current
(Operating Write)
ICC2
Min
Typ
Max
Units
fSK = 1MHz
VCC = 5.0V
3
mA
Power Supply Current
(Operating Read)
fSK = 1MHz
VCC = 5.0V
500
µA
ISB1
Power Supply Current
(Standby) (x8 Mode)
CS = 0V
ORG=GND
10
µA
ISB2(5)
Power Supply Current
(Standby) (x16Mode)
CS=0V
ORG=Float or VCC
0
µA
ILI
Input Leakage Current
VIN = 0V to VCC
1
µA
ILO
Output Leakage Current
(Including ORG pin)
VOUT = 0V to VCC,
CS = 0V
1
µA
VIL1
Input Low Voltage
4.5V ≤ VCC < 5.5V
-0.1
0.8
V
VIH1
Input High Voltage
4.5V ≤ VCC < 5.5V
2
VCC + 1
V
VIL2
Input Low Voltage
1.8V ≤ VCC < 4.5V
0
VCC x 0.2
V
VIH2
Input High Voltage
4.8V ≤ VCC < 4.5V
VCC x 0.7
VCC+1
V
VOL1
Output Low Voltage
4.5V ≤ VCC < 5.5V
IOL = 2.1mA
0.4
V
VOH1
Output High Voltage
4.5V ≤ VCC < 5.5V
IOH = -400µA
VOL2
Output Low Voltage
1.8V ≤ VCC < 4.5V
IOL = 1mA
VOH2
Output High Voltage
1.8V ≤ VCC < 4.5V
IOH = -100µA
2.4
V
0.2
VCC - 0.2
V
V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
(5) Standby Current (ISB2)=0µA (<900nA) for 93C46/56/57/66, (ISB2)=2µA for 93C86.
Doc. No. 1023, Rev. J
2
93C46/56/57/66/86
PIN CAPACITANCE
Symbol
COUT
Test
Conditions
Output Capacitance (DO)
Input Capacitance (CS, SK, DI, ORG)
(3)
CIN(3)
Min
Typ
Max
Units
VOUT=0V
5
pF
VIN=0V
5
pF
INSTRUCTION SET
Instruction Device
Type
READ
ERASE
WRITE
EWEN
EWDS
ERAL
WRAL
Start Opcode
Bit
Address
x8
x16
Data
x8
x16
PE(2)
Comments
93C46
93C56(1)
93C66
93C57
93C86
1
1
1
1
1
10
10
10
10
10
A6-A0
A8-A0
A8-A0
A7-A0
A10-A0
A5-A0
A7-A0
A7-A0
A6-A0
A9-A0
Read Address AN–A0
93C46
93C56(1)
93C66
93C57
93C86
1
1
1
1
1
11
11
11
11
11
A6-A0
A8-A0
A8-A0
A7-A0
A10-A0
A5-A0
A7-A0
A7-A0
A6-A0
A9-A0
Clear Address AN–A0
93C46
93C56(1)
93C66
93C57
93C86
1
1
1
1
1
01
01
01
01
01
A6-A0
A8-A0
A8-A0
A7-A0
A10-A0
A5-A0
A7-A0
A7-A0
A6-A0
A9-A0
93C46
93C56
93C66
93C57
93C86
1
1
1
1
1
00
00
00
00
00
11XXXXX
11XXXX
11XXXXXXX
11XXXXXX
11XXXXXXX
11XXXXXX
11XXXXXX
11XXXXX
11XXXXXXXXX 11XXXXXXXX
Write Enable
93C46
93C56
93C66
93C57
93C86
1
1
1
1
1
00
00
00
00
00
00XXXXX
00XXXX
00XXXXXXX
00XXXXXX
00XXXXXXX
00XXXXXX
00XXXXXX
00XXXXX
00XXXXXXXXX 00XXXXXXXX
Write Disable
93C46
93C56
93C66
93C57
93C86
1
1
1
1
1
00
00
00
00
00
10XXXXX
10XXXX
10XXXXXXX
10XXXXXX
10XXXXXXX
10XXXXXX
10XXXXXX
10XXXXX
10XXXXXXXXX 10XXXXXXXX
Clear All Addresses
93C46
93C56
93C66
93C57
93C86
1
1
1
1
1
00
00
00
00
00
01XXXXX
01XXXX
01XXXXXXX
01XXXXXX
01XXXXXXX
01XXXXXX
01XXXXXX
01XXXXX
01XXXXXXXXX 01XXXXXXXX
X
I
D7-D0
D7-D0
D7-D0
D7-D0
D7-D0
D15-D0
D15-D0
D15-D0
D15-D0
D15-D0
Write Address AN–A0
I
X
X
I
D7-D0
D7-D0
D7-D0
D7-D0
D7-D0
D15-D0
D15-D0
D15-D0
D15-D0
D15-D0
Write All Addresses
I
Note:
(1) Address bit A8 for 256x8 ORG and A7 for 128x16 ORG are "Don't Care" bits, but must be kept at either a "1" or "0" for READ, WRITE
and ERASE commands.
(2) Applicable only to 93C86
(3) This parameter is tested initially and after a design or process change that affects the parameter.
3
Doc. No. 1023, Rev. J
93C46/56/57/66/86
A.C. CHARACTERISTICS (93C46/56/57/66)
Limits
VCC =
1.8V-6V
VCC =
2.5V-6V
VCC =
4.5V-5.5V
Test
SYMBOL PARAMETER
Conditions
Min
Max
Min
Max
Min
Max
Units
tCSS
CS Setup Time
200
100
50
ns
tCSH
CS Hold Time
0
0
0
ns
tDIS
DI Setup Time
400
200
100
ns
tDIH
DI Hold Time
400
200
100
ns
tPD1
Output Delay to 1
tPD0
Output Delay to 0
CL = 100pF
(3)
1
0.5
0.25
µs
1
0.5
0.25
µs
400
200
100
ns
10
10
10
ms
tHZ(1)
Output Delay to High-Z
tEW
Program/Erase Pulse Width
tCSMIN
Minimum CS Low Time
1
0.5
0.25
µs
tSKHI
Minimum SK High Time
1
0.5
0.25
µs
tSKLOW
Minimum SK Low Time
1
0.5
0.25
µs
tSV
Output Delay to Status Valid
SKMAX
Maximum Clock Frequency
1
DC
0.5
250
DC
500
DC
0.25
µs
1000
kHz
A.C. CHARACTERISTICS (93C86)
Limits
VCC =
1.8V-6V
Test
SYMBOL PARAMETER
Conditions
Min
Max
VCC =
2.5V-6V
Min
Max
VCC =
4.5V-5.5V
Min
Max
Units
tCSS
CS Setup Time
200
100
50
ns
tCSH
CS Hold Time
0
0
0
ns
tDIS
DI Setup Time
200
100
50
ns
tDIH
DI Hold Time
200
100
50
ns
tPD1
Output Delay to 1
tPD0
Output Delay to 0
tHZ(1)
Output Delay to High-Z
tEW
Program/Erase Pulse Width
tCSMIN
Minimum CS Low Time
1
0.5
0.15
µs
tSKHI
Minimum SK High Time
1
0.5
0.15
µs
tSKLOW
Minimum SK Low Time
1
0.5
0.15
µs
tSV
Output Delay to Status Valid
SKMAX
Maximum Clock Frequency
1
0.5
0.15
µs
CL = 100pF
1
0.5
0.15
µs
(3)
400
200
100
ns
5
5
5
ms
1
DC
500
0.5
DC
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. 1023, Rev. J
4
1000
DC
0.1
µs
3000
kHz
93C46/56/57/66/86
POWER-UP TIMING (1)(2)
SYMBOL
PARAMETER
Max
Units
tPUR
Power-up to Read Operation
1
ms
tPUW
Power-up to Write Operation
1
ms
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
(3) The input levels and timing reference points are shown in “AC Test Conditions” table.
A.C. TEST CONDITIONS
Input Rise and Fall Times
≤ 50ns
Input Pulse Voltages
0.4V to 2.4V
4.5V ≤ VCC ≤ 5.5V
Timing Reference Voltages
0.8V, 2.0V
4.5V ≤ VCC ≤ 5.5V
Input Pulse Voltages
0.2VCC to 0.7VCC
1.8V ≤ VCC ≤ 4.5V
Timing Reference Voltages
0.5VCC
1.8V ≤ VCC ≤ 4.5V
5
Doc. No. 1023, Rev. J
93C46/56/57/66/86
DEVICE OPERATION
the DI pin on the rising edge of the clock (SK). The DO
pin is normally in a high impedance state except when
reading data from the device, or when checking the
ready/busy status after a write operation.
The CAT93C46/56(57)66/86 is a 1024/2048/4096/
16,384-bit nonvolatile memory intended for use with
industry standard microprocessors. The CAT93C46/56/
57/66/86 can be organized as either registers of 16 bits
or 8 bits. When organized as X16, seven 9-bit instructions for 93C46; seven 10-bit instructions for 93C57;
seven 11-bit instructions for 93C56 and 93C66; seven
13-bit instructions for 93C86; control the reading, writing
and erase operations of the device. When organized as
X8, seven 10-bit instructions for 93C46; seven 11-bit
instructions for 93C57; seven 12-bit instructions for
93C56 and 93C66: seven 14-bit instructions for 93C86;
control the reading, writing and erase operations of the
device. The CAT93C46/56/57/66/86 operates on a single
power supply and will generate on chip, the high voltage
required during any write operation.
The ready/busy status can be determined after the start
of a write operation by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that
the device is ready for the next instruction. If necessary,
the DO pin may be placed back into a high impedance
state during chip select by shifting a dummy “1” into the
DI pin. The DO pin will enter the high impedance state on
the falling edge of the clock (SK). Placing the DO pin into
the high impedance state is recommended in applications where the DI pin and the DO pin are to be tied
together to form a common DI/O pin.
Instructions, addresses, and write data are clocked into
Figure 1. Sychronous Data Timing
tSKLOW
tSKHI
tCSH
SK
tDIS
tDIH
VALID
DI
VALID
tCSS
CS
tDIS
tPD0,tPD1
DO
tCSMIN
DATA VALID
93C46/56/57/66/86 F03
Figure 2a. Read Instruction Timing (93C46)
SK
tCSMIN
CS
STANDBY
AN
DI
DO
1
1
AN—1
A0
0
HIGH-Z
tPD0
tHZ
HIGH-Z
0
DN
DN—1
D1
D0
93C46/56/57/66/86 F04
Doc. No. 1023, Rev. J
6
93C46/56/57/66/86
increment to the next address and shift out the next data
word in a sequential READ mode. As long as CS is
continuously asserted and SK continues to toggle, the
device will keep incrementing to the next address
automatically until it reaches to the end of the address
space, then loops back to address 0. In the sequential
READ mode, only the initial data word is preceeded by
a dummy zero bit. All subsequent data words will follow
without a dummy zero bit.
The format for all instructions sent to the device is a
logical "1" start bit, a 2-bit (or 4-bit) opcode, 6-bit (93C46)/
/7-bit (93C57)/ 8-bit (93C56 or 93C66)/10-bit (93C86)
(an additional bit when organized X8) and for write
operations a 16-bit data field (8-bit for X8 organizations).
Note: This note is applicable only to 93C86. The Write,
Erase, Write all and Erase all instructions require PE=1.
If PE is left floating, 93C86 is in Program Enabled mode.
For Write Enable and Write Disable instruction PE=don’t
care.
Write
After receiving a WRITE command, address and the
data, the CS (Chip Select) pin must be deselected for a
minimum of tCSMIN. The falling edge of CS will start the
self clocking clear and data store cycle of the memory
location specified in the instruction. The clocking of the
SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the
CAT93C46/56/57/66/86 can be determined by selecting
the device and polling the DO pin. Since this device
features Auto-Clear before write, it is NOT necessary to
erase a memory location before it is written into.
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93C46/
56/57/66/86 will come out of the high impedance state
and, after sending an initial dummy zero bit, will begin
shifting out the data addressed (MSB first). The output
data bits will toggle on the rising edge of the SK clock and
are stable after the specified time delay (tPD0 or tPD1).
For the CAT93C56/57/66/86, after the initial data word
has been shifted out and CS remains asserted with the
SK clock continuing to toggle, the device will automatically
Figure 2b. Read Instruction Timing (93C56/57/66/86)
SK
1
1
1
1
1
AN
AN–1
1
1
1
1
1
1
1
1
1
1
CS
Don't Care
DI
1
1
A0
0
HIGH-Z
DO
Dummy 0
D15 . . . D0
or
D7 . . . D0
Address + 1
D15 . . . D0
or
D7 . . . D0
Address + 2
D15 . . . D0
or
D7 . . . D0
Address + n
D15 . . .
or
D7 . . .
Figure 3. Write Instruction Timing
SK
tCSMIN
AN
DI
1
0
AN-1
A0
DN
D0
1
tSV
DO
STANDBY
STATUS
VERIFY
CS
tHZ
BUSY
HIGH-Z
READY
HIGH-Z
tEW
93C46/56/57/66/86 F05
7
Doc. No. 1023, Rev. J
93C46/56/57/66/86
Erase
Erase All
Upon receiving an ERASE command and address, the
CS (Chip Select) pin must be deasserted for a minimum
of tCSMIN. The falling edge of CS will start the self clocking
clear cycle of the selected memory location. The clocking
of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of
the CAT93C46/56/57/66/86 can be determined by
selecting the device and polling the DO pin. Once
cleared, the content of a cleared location returns to a
logical “1” state.
Upon receiving an ERAL command, the CS (Chip Select)
pin must be deselected for a minimum of tCSMIN. The
falling edge of CS will start the self clocking clear cycle
of all memory locations in the device. The clocking of the
SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the
CAT93C46/56/57/66/86 can be determined by selecting
the device and polling the DO pin. Once cleared, the
contents of all memory bits return to a logical “1” state.
Write All
Erase/Write Enable and Disable
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN. The falling edge of CS will start the self clocking
data write to all memory locations in the device. The
clocking of the SK pin is not necessary after the device
has entered the self clocking mode. (Note 1.) The ready/
busy status of the CAT93C46/56/57/66/86 can be
determined by selecting the device and polling the DO
pin. It is not necessary for all memory locations to be
cleared before the WRAL command is executed.
The CAT93C46/56/57/66/86 powers up in the write
disable state. Any writing after power-up or after an
EWDS (write disable) instruction must first be preceded
by the EWEN (write enable) instruction. Once the write
instruction is enabled, it will remain enabled until power
to the device is removed, or the EWDS instruction is
sent. The EWDS instruction can be used to disable all
CAT93C46/56/57/66/86 write and clear instructions,
and will prevent any accidental writing or clearing of the
device. Data can be read normally from the device
regardless of the write enable/disable status.
Figure 4. Erase Instruction Timing
SK
STATUS VERIFY
CS
AN
DI
1
1
tCS
A0
AN-1
STANDBY
1
tSV
tHZ
HIGH-Z
DO
BUSY
READY
HIGH-Z
tEW
93C46/56/57/66/86 F06
Doc. No. 1023, Rev. J
8
93C46/56/57/66/86
Figure 5. EWEN/EWDS Instruction Timing
SK
STANDBY
CS
DI
1
0
0
*
* ENABLE=11
DISABLE=00
93C46/56/57/66/86 F07
Figure 6. ERAL Instruction Timing
SK
CS
STATUS VERIFY
STANDBY
tCS
DI
1
0
0
1
0
tSV
tHZ
HIGH-Z
DO
BUSY
READY
HIGH-Z
tEW
93C46/56/57/66/86 F08
Figure 7. WRAL Instruction Timing
SK
CS
STATUS VERIFY
STANDBY
tCSMIN
DI
1
0
0
0
DN
1
D0
tSV
tHZ
DO
BUSY
READY
HIGH-Z
tEW
93C46/56/57/66/86 F09
9
Doc. No. 1023, Rev. J
93C46/56/57/66/86
ORDERING INFORMATION
Prefix
CAT
Optional
Company ID
Device #
93C46
Product
Number
93C46: 1K
93C56: 2K
93C57: 2K
93C66: 4K
93C86: 16K
Suffix
S
I
Temperature Range
Blank = Commercial (0° - 70°C)
I = Industrial (-40° - 85°C)
A = Automotive (-40° - 105°C)
E = Extended (-40°C to + 125°C)
Package
P = PDIP
S = SOIC (JEDEC)
J = SOIC (JEDEC)
K = SOIC (EIAJ)
U = TSSOP*
RD4 = TDFN (3x3mm)
ZD4 = TDFN (3x3mm, Lead free, Halogen free)
L = PDIP (Lead free, Halogen free)
V = SOIC, JEDEC (Lead free, Halogen free)
W= SOIC, JEDEC (Lead free, Halogen free)
X = SOIC, EIAJ (Lead free, Halogen free)
Y = TSSOP (Lead free, Halogen free)*
-1.8
TE13
Tape & Reel
TE13: 2000/Reel
Operating Voltage
Blank (Vcc=2.5 to 6.0V)
1.8 (Vcc=1.8 to 6.0V)
*CAT93C46/56/57/66 only
Notes:
(1) The device used in the above example is a 93C46SI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating Voltage,
Tape & Reel)
(2) TSSOP (U/Y) package only available for 93C46/56/57/66
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™
AE2 ™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.catalyst-semiconductor.com
Doc. No. 1023, Rev. J
Publication #:
Revison:
Issue date:
Type:
10
1023
J
6/23/03
Final
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Catalyst / ON Semiconductor:
CAT93C56XA CAT93C56SI-1.8 CAT93C46KI-1.8 CAT93C56SA CAT93C86PI-1.8 CAT93C46SI-TE13
CAT93C46P CAT93C57U CAT93C66KI-1.8 CAT93C86P-1.8 CAT93C46JI-1.8 CAT93C66K-1.8 CAT93C86PA
CAT93C56J CAT93C66YI-1.8 CAT93C66XI-1.8 CAT93C56W-1.8 CAT93C57U-1.8 CAT93C66U-1.8 CAT93C46X1.8 CAT93C66S CAT93C46PA CAT93C57UI CAT93C46J-1.8 CAT93C66KA CAT93C56PA CAT93C66X-1.8
CAT93C66S-1.8 CAT93C56Y-1.8 CAT93C57WI-1.8 CAT93C57Y CAT93C56P CAT93C57JI-1.8 CAT93C86V-TE13
CAT93C57V-1.8 CAT93C46SI-1.8 CAT93C57YI-1.8 CAT93C57J CAT93C66Y-1.8 CAT93C66LA CAT93C57J-1.8
CAT93C56UI-1.8 CAT93C46W CAT93C66YI-TE13E CAT93C46K CAT93C57KI-1.8 CAT93C86L-1.8 CAT93C57S1.8 CAT93C56SI CAT93C46W-1.8 CAT93C66KI CAT93C57V CAT93C57YI CAT93C66L-1.8 CAT93C46SA
CAT93C56P-1.8 CAT93C66U CAT93C56LI CAT93C56V-1.8 CAT93C56S-1.8 CAT93C57JA CAT93C56L
CAT93C56PI-1.8 CAT93C46X CAT93C56YI CAT93C66UI CAT93C56VI CAT93C57L-1.8 CAT93C66PA
CAT93C66WA CAT93C66V CAT93C86LA CAT93C57UI-1.8 CAT93C57KI CAT93C46PI-1.8 CAT93C46UI
CAT93C56Y CAT93C57XI-1.8 CAT93C46YI CAT93C46J CAT93C66P-1.8 CAT93C57W-1.8 CAT93C46Y-1.8
CAT93C46JA CAT93C66JI-1.8 CAT93C46KA CAT93C46P-1.8 CAT93C46K-1.8 CAT93C66VI-1.8 CAT93C46S-1.8
CAT93C66J CAT93C46KI CAT93C66UI-1.8 CAT93C66SI-1.8 CAT93C57JI CAT93C46SI CAT93C86S
CAT93C66P CAT93C46Y CAT93C66K
Similar pages