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M41ST87W
5.0 and 3.3/3.0 V secure serial RTC and NVRAM supervisor with
tamper detection and 128 bytes of clearable NVRAM
Datasheet - production data
•
•
28-pin, (300 mil)
SOX28, embedded crystal
•
•
•
•
•
SSOP20
Features
•
•
•
•
•
•
5.0, 3.3, or 3.0 V operation
2
400 kHz I C bus
NVRAM supervisor to non-volatize external
LPSRAM
2.5 to 5.5 V oscillator operating voltage
Automatic switchover and deselect circuitry
Choice of power-fail deselect voltages
−
M41ST87Y: (not recommended for new
design, contact ST sales office for
availability)
THS = 1: VPFD≈ 4.63 V;
VCC = 4.75 to 5.5 V
THS = 0: VPFD≈ 4.37 V;
VCC = 4.5 to 5.5 V
−
M41ST87W:
THS = 1: VPFD ≈ 2.9 V;
VCC = 3.0 to 3.6 V
THS = 0: VPFD ≈ 2.63 V;
VCC = 2.7 to 3.6 V
May 2016
•
•
•
Two independent power-fail comparators
(1.25 V reference)
Counters for tenths/hundredths of seconds,
seconds, minutes, hours, day, date, month,
year, and century
128 bytes of clearable, general purpose
NVRAM
Programmable alarm and interrupt function
(valid even during battery backup mode)
Programmable watchdog timer
Unique electronic serial number (8-byte)
32 kHz frequency output available upon
power-on
Microprocessor power-on reset output
Battery low flag
Ultra-low battery supply current of 500 nA
(typ)
Security features
•
•
•
•
Tamper indication circuits with timestamp
and RAM clear
LPSRAM clear function (TPCLR)
Packaging includes a 28-lead, embedded
crystal SOIC and a 20-lead SSOP
Oscillator stop detection
DocID9497 Rev 11
This is information on a product in full production.
1/54
www.st.com
Contents
M41ST87W
Contents
1
Description....................................................................................... 6
2
Operating modes ........................................................................... 12
2.1
2-wire bus characteristics ................................................................ 13
2.1.1
Bus not busy ..................................................................................... 13
2.1.2
Start data transfer ............................................................................. 13
2.1.3
Stop data transfer ............................................................................. 13
2.1.4
Data valid .......................................................................................... 13
2.1.5
Acknowledge .................................................................................... 13
2.2
READ mode .................................................................................... 15
2.3
WRITE mode................................................................................... 17
2.4
Data retention mode........................................................................ 17
2.5
Tamper detection circuit .................................................................. 18
2.6
Tamper register bits (tamper 1 and tamper 2) ................................. 18
2.6.1
Tamper enable bits (TEB1 and TEB2) ............................................. 18
2.6.2
Tamper bits (TB1 and TB2) .............................................................. 18
2.6.3
Tamper interrupt enable bits (TIE1 and TIE2) .................................. 19
2.6.4
Tamper connect mode bit (TCM1 and TCM2) ................................. 19
2.6.5
Tamper polarity mode bits (TPM1 and TPM2) ................................. 19
2.6.6
Tamper detect sampling (TDS1 and TDS2) ..................................... 21
2.6.7
Tamper current high/tamper current low (TCHI/1 and
TCHI/2).................................................................................................... 21
2.6.8
RAM clear (CLR1 and CLR2) ........................................................... 21
2.6.9
RAM clear external (CLR1EXT and CLR2EXT) - available in SOX28
package only .................................................................................................... 21
3
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2.7
Tamper detection operation ............................................................ 25
2.8
Sampling ......................................................................................... 25
2.9
Internal tamper pull-up/down current............................................... 26
2.10
Avoiding inadvertent tampers (normally closed configuration) ........ 26
2.11
Tamper event time-stamp ............................................................... 27
Clock operation ............................................................................. 28
3.1
Power-down time-stamp ................................................................. 28
3.2
TIMEKEEPER® registers................................................................. 29
3.3
Calibrating the clock ........................................................................ 31
3.4
Setting alarm clock registers ........................................................... 32
3.5
Watchdog timer ............................................................................... 34
DocID9497 Rev 11
M41ST87W
Contents
3.6
Square wave output ........................................................................ 35
3.7
Full-time 32 kHz square wave output .............................................. 36
3.8
Power-on reset ................................................................................ 36
3.9
Reset inputs ( and ) ................................................ 36
3.10
3.11
Power-fail comparators (1 and 2) .................................................... 37
Power-fail outputs ........................................................................... 37
3.12
Century bits ..................................................................................... 38
3.13
Output driver pin.............................................................................. 38
3.14
Battery low warning ......................................................................... 38
3.15
trec bit ............................................................................................... 39
3.16
Electronic serial number .................................................................. 39
3.17
Oscillator stop detection .................................................................. 39
3.18
Initial power-on defaults .................................................................. 40
4
Maximum ratings ........................................................................... 41
5
DC and AC parameters ................................................................. 42
6
Package information ..................................................................... 46
7
8
9
6.1
SOX28 package information ........................................................... 46
6.2
SSOP20 package information ......................................................... 48
Packing information ...................................................................... 49
7.1
SOX28 carrier tape ......................................................................... 49
7.2
SSOP20 carrier tape ....................................................................... 50
7.3
Reel information for SOX28 and SSOP20 ...................................... 51
Part numbering .............................................................................. 52
Revision history ............................................................................ 53
DocID9497 Rev 11
3/54
List of tables
M41ST87W
List of tables
Table 1: Signal names ................................................................................................................................ 9
2
Table 2: I C slave address ........................................................................................................................ 12
Table 3: AC characteristics ....................................................................................................................... 15
Table 4: Tamper detection truth table ....................................................................................................... 20
Table 5: Tamper detection current (normally closed - TCMX = '0') .......................................................... 22
Table 6: Tamper detect timing .................................................................................................................. 24
Table 7: Calculated cutoff frequency for typical capacitance and resistance values ............................... 26
®
Table 8: TIMEKEEPER register map ...................................................................................................... 29
Table 9: Alarm repeat modes ................................................................................................................... 33
Table 10: Square wave output frequency ................................................................................................. 35
Table 11: Reset AC characteristics .......................................................................................................... 37
Table 12: Century bits examples .............................................................................................................. 38
Table 13: trec definitions ........................................................................................................................... 39
Table 14: Default values ........................................................................................................................... 40
Table 15: Default values ........................................................................................................................... 40
Table 16: Absolute maximum ratings ....................................................................................................... 41
Table 17: DC and AC measurement conditions ....................................................................................... 42
Table 18: Capacitance .............................................................................................................................. 42
Table 19: DC characteristics ..................................................................................................................... 43
Table 20: Crystal electrical characteristics ............................................................................................... 44
Table 21: Power down/up AC characteristics ........................................................................................... 45
Table 22: SOX28 – 28-lead plastic small outline, 300 mils, embedded crystal package mechanical data
.................................................................................................................................................................. 47
Table 23: SSOP20 – 20-lead, shrink, small outline package mechanical data ........................................ 48
Table 24: Carrier tape dimensions for SOX28 package ........................................................................... 49
Table 25: Reel dimensions for 24 mm carrier tape (SOX28 package) and 16 mm carrier tape (SSOP20
package) ................................................................................................................................................... 51
Table 26: Ordering information scheme ................................................................................................... 52
Table 27: Document revision history ........................................................................................................ 53
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DocID9497 Rev 11
M41ST87W
List of figures
List of figures
Figure 1: Logic diagram .............................................................................................................................. 7
Figure 2: 28-pin, 300 mil SOIC connections ............................................................................................... 8
Figure 3: 20-pin, SSOP connections .......................................................................................................... 8
Figure 4: Block diagram ............................................................................................................................ 10
Figure 5: Hardware hookup ...................................................................................................................... 11
Figure 6: Serial bus data transfer sequence ............................................................................................. 14
Figure 7: Acknowledgement sequence..................................................................................................... 14
Figure 8: Bus timing requirements sequence ........................................................................................... 14
Figure 9: Slave address location .............................................................................................................. 16
Figure 10: READ mode sequence ............................................................................................................ 16
Figure 11: Alternate READ mode sequence ............................................................................................ 16
Figure 12: WRITE mode sequence .......................................................................................................... 17
Figure 13: WRITE cycle timing: RTC and external SRAM control signals ............................................... 17
Figure 14: Tamper detect connection options .......................................................................................... 19
Figure 15: Basic tamper detect options .................................................................................................... 20
Figure 16: Tamper detect output options .................................................................................................. 20
Figure 17: Tamper detect sampling options ............................................................................................. 22
Figure 18: Tamper current options ........................................................................................................... 23
Figure 19: Tamper output timing (with CLR1EXT or CLR2EXT = '1') - available in SOX28 package only
.................................................................................................................................................................. 23
Figure 20: RAM clear hardware hookup (SOX28 package only) ............................................................. 24
Figure 21: Low-pass filter implementation for noise immunity.................................................................. 26
Figure 22: Crystal accuracy across temperature ...................................................................................... 32
Figure 23: Calibration waveform ............................................................................................................... 32
Figure 24: Alarm interrupt reset waveform ............................................................................................... 33
Figure 25: Backup mode alarm waveform ................................................................................................ 34
Figure 26:  and  timing waveforms .................................................................................. 36
Figure 27: AC testing input/output waveforms .......................................................................................... 42
Figure 28: Power down/up mode AC waveforms ..................................................................................... 45
Figure 29: SOX28 – 28-lead plastic small outline, 300 mils, embedded crystal package outline ............ 46
Figure 30: SSOP20 – 20-lead, shrink, small outline package outline ...................................................... 48
Figure 31: Carrier tape for SOX28 package ............................................................................................. 49
Figure 32: Carrier tape for SSOP20 package ........................................................................................... 50
Figure 33: Reel schematic ........................................................................................................................ 51
DocID9497 Rev 11
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Description
1
M41ST87W
Description
The M41ST87Y/W secure serial RTC and NVRAM supervisor is a low power 1280-bit,
static CMOS SRAM organized as 160 bytes by 8 bits. A built-in 32.768 kHz oscillator
(internal crystal-controlled) and 8 bytes of the SRAM are used for the clock/calendar
function and are configured in binary coded decimal (BCD) format.
An additional 11 bytes of RAM provide calibration, status/control of alarm, watchdog,
tamper, and square wave functions. 8 bytes of ROM and finally 128 bytes of user RAM are
2
also provided. Addresses and data are transferred serially via a two line, bidirectional I C
interface. The built-in address register is incremented automatically after each WRITE or
READ data byte. The M41ST87Y/W has a built-in power sense circuit which detects power
failures and automatically switches to the battery supply when a power failure occurs. The
energy needed to sustain the SRAM and clock operations can be supplied by a small
lithium button-cell supply when a power failure occurs.
Functions available to the user include a non-volatile, time-of-day clock/calendar, alarm
interrupts, tamper detection, watchdog timer, and programmable square wave output.
Other features include a power-on reset as well as two additional debounced inputs
(RSTIN1 and RSTIN2) which can also generate an output reset (RST). The eight clock
address locations contain the century, year, month, date, day, hour, minute, second and
tenths/hundredths of a second in 24-hour BCD format. Corrections for 28, 29 (leap year),
30 and 31 day months are made automatically.
Security features
Two fully independent tamper detection Inputs allow monitoring of multiple locations within
the system. User programmable bits provide both normally open and normally closed
switch monitoring. Time stamping of the tamper event is automatically provided. There is
also an option allowing data stored in either internal memory (128 bytes), and/or external
memory to be cleared, protecting sensitive information in the event tampering occurs. By
embedding the 32 kHz crystal in the SOX28 package, the clock is completely isolated from
external tampering. An oscillator fail bit (OF) is also provided to ensure correct operation of
the oscillator.
The M41ST87Y/W is supplied in a 28-pin, 300 mil SOIC package which includes an
embedded 32 kHz crystal and a 20-pin SSOP package for use with an external crystal.
The SOIC and SSOP packages are shipped in plastic anti-static tubes or in tape and reel
form.
The 300 mil, embedded crystal SOIC requires only a user-supplied battery to provide nonvolatile operation.
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DocID9497 Rev 11
M41ST87W
Description
Figure 1: Logic diagram
VCC
XI
VBAT
(4)
XO
VOUT
(4)
IRQ/OUT
(1)
SCL
SQW/FT
SDA
EX
(3)
ECON
RSTIN1
RST
(3)
RSTIN2
WDI
(3)
M41ST87Y
M41ST87W
(3)
(1)
F32k
(1)
PFI 1
PFO 1
PFI 2
PFO 2
TP1 IN
(2)
(2)
(2)
(3)
TPCLR
TP2 IN
VSS
1.
2.
3.
4.
Open drain output.
Programmable output (open drain or full-CMOS). Defaults to open drain on first
power-up.
Available in SOX28 package only.
Available in SSOP package only.
DocID9497 Rev 11
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Description
M41ST87W
Figure 2: 28-pin, 300 mil SOIC connections
NF
NF
NF
NF
NC
NC
PFO 2
SQW/FT
WDI
RSTIN1
RSTIN2
PFO 1
PFI 2
V SS
1
2
3
4
5
6
7
M41ST87Y
8 M41ST87W
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V CC
EX
IRQ/OUT
V OUT
TP2 IN
PFI 1
SCL
F 32k
TP1 IN
RST
TP CLR
S DA
E CON
V B AT
Note: No function (NF) and no connect (NC) pins should be tied to VSS. Pins 1, 2, 3, and 4
are internally shorted together.
Figure 3: 20-pin, SSOP connections
V CC
XI
XO
NC
PFO 2
SQW/FT
RSTIN1
PFO 1
PFI 2
V SS
1
2
3
4
5 M41ST87Y
6 M41ST87W
7
8
9
10
Note: No connect (NC) pin should be tied to VSS.
8/54
DocID9497 Rev 11
20
19
18
17
16
15
14
13
12
11
IRQ/OUT
V OUT
TP2 IN
PFI 1
SCL
F 32k
TP1 IN
RST
S DA
V B AT
M41ST87W
Description
Table 1: Signal names
XI
(1)
Oscillator input
(1)
XO
Oscillator output
E̅CON
(2)
EX
Conditioned chip enable output
(2)
External chip enable
IRQ/OUT
(3)
PFI1
PFI2
Interrupt/out output (open drain)
Power fail input 1
Power fail input 2
PFO1
PFO2
(4)
Power fail output 1
(4)
Power fail output 2
(3)
RST
RSTIN1
RSTIN2
Reset output (open drain)
Reset 1 input
(2)
SCL
Reset 2 input
Serial clock input
SDA
Serial data input/output
(4)
SQW/FT
(2)
Square wave output/frequency test
WDI
Watchdog input
VCC
Supply voltage
VOUT
Voltage output
VSS
Ground
(3)
F32k
32 kHz square wave output (open drain)
TP1IN
Tamper pin 1 input
TP2IN
Tamper pin 2 input
(2)
TPCLR
Tamper pin RAM clear
VBAT
Positive battery pin input
(5)
No function
(5)
No connect
NF
NC
Notes:
(1)
(2)
(3)
(4)
(5)
Available in SSOP package only.
Available in SOX28 package only.
Open drain output.
Programmable output (open drain or full-CMOS).
Should be connected to VSS.
DocID9497 Rev 11
9/54
Description
M41ST87W
Figure 4: Block diagram
REAL TIME CLOCK
CALENDAR
128 BYTES
USER RAM
SDA
I2C
INTERFACE
8 BYTES ROM
OFIE
RTC w/ALARM
& CALIBRATION
SCL
Crystal
VOUT
(4)
XI
XO
WATCHDOG
32KHz
OSCILLATOR
(3)
TPXIN
WDS
SQUARE WAVE
TAMPER
IRQ/OUT
TIEX
CLRX
WDI
2
AFE
CLRX EXT
(1)
SQW/FT (2)
TPCLR(3)
VOUT
VCC
VBAT
F32k(1)
VSS
VBL
COMPARE
VSO
COMPARE
VPFD
COMPARE
BL
POR
RST (1)
RSTIN1
(3)
RSTIN2
(3)
(3)
ECON
EX
PFI1
COMPARE
PFO1(2)
COMPARE
PFO2(2)
1.25V
(Internal)
PFI2
1.25V
(Internal)
1.
2.
3.
4.
10/54
Open drain output.
Programmable output (open drain or full-CMOS); if open drain option is selected and if
pulled-up to supply other than VCC, this supply must be equal to, or less than VBAT
when VCC = 0 V (during battery backup mode).
Available in SOX28 package only.
Crystal is external on SSOP package and internal for the SOX28 package.
DocID9497 Rev 11
M41ST87W
Description
Figure 5: Hardware hookup
M41ST87Y/W
Unregulated
Voltage
VIN
VCC
5V
Regulator
(1)
VCC
TPCLR
(1)
ECON
TP2IN
EX
VCC
3.3V
Regulator
VIN
VCC
VOUT
TP1IN
E
(1)
Low-Power
SRAM
SCL
(1)
For monitoring
of additional
voltage sources
R1
Pushbutton
Reset
R3
WDI
SDA
RSTIN1
RST
RSTIN2
To LED Display
To NMI
PFO2
PFI2
VSS
R4
1.
SQW/FT
PFO1
PFI1
R2
(1)
To Microprocessor
VBAT
IRQ/OUT
F32k
To INT
To 32kHz
Available in SOX28 package only.
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Operating modes
2
M41ST87W
Operating modes
The M41ST87Y/W clock operates as a slave device on the serial bus. Access is obtained
by implementing a start condition followed by the correct slave address (D0h).
2
Table 2: I C slave address
2
7-bit I C slave address
0x68
Write: 0xD0
2
8-bit I C slave address
Read: 0xD1
The 160 bytes contained in the device can then be accessed sequentially in the following
order:
00h.
Tenths/hundredths of a second register
01h.
Seconds register
02h.
Minutes register
03h.
Century/hours register
04h.
Day register
05h.
Date register
06h.
Month register
07h.
Year register
08h.
Control register
09h.
Watchdog register
0Ah-0Eh. Alarm registers
0Fh.
Flag register
10h-12h.
Reserved
13h.
Square wave
14h.
Tamper register 1
15h.
Tamper register 2
16h-1Dh.
Serial number (8 bytes)
1Eh-1Fh.
Reserved (2 bytes)
20h-9Fh.
User RAM (128 bytes)
The M41ST87Y/W clock continually monitors VCC for an out-of-tolerance condition. Should
VCC fall below VPFD, the device terminates an access in progress and resets the device
address counter. Inputs to the device will not be recognized at this time to prevent
erroneous data from being written to the device from a an out-of-tolerance system. When
VCC falls below VSO, the device automatically switches over to the battery and powers down
into an ultra low current mode of operation to conserve battery life. As system power
returns and VCC rises above VSO, the battery is disconnected, and the device is switched to
external VCC.
Write protection continues until trec (min) elapses after VCC reaches VPFD (min).
For more information on battery storage life refer to application note AN1012.
12/54
DocID9497 Rev 11
M41ST87W
2.1
Operating modes
2-wire bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a
clock signal (SCL) and a bidirectional data signal (SDA). The SDA line must be connected
to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
•
•
•
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is high.
Changes in the data line, while the clock line is high, will be interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
2.1.1
Bus not busy
Both data and clock lines remain high.
2.1.2
Start data transfer
A change in the state of the data line, from high to low, while the clock is high, defines the
START condition.
2.1.3
Stop data transfer
A change in the state of the data line, from low to high, while the clock is high, defines the
STOP condition.
2.1.4
Data valid
The state of the data line represents valid data when, after a start condition, the data line is
stable for the duration of the high period of the clock signal. The data on the line may be
changed during the low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a start condition and terminated with a stop condition.
The number of data bytes transferred between the start and stop conditions is not limited.
The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition a device that gives out a message is called “transmitter,” the receiving device
that gets the message is called “receiver.” The device that controls the message is called
“master.” The devices that are controlled by the master are called “slaves.”
2.1.5
Acknowledge
Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low
level put on the bus by the receiver whereas the master generates an extra acknowledge
related clock pulse. A slave receiver which is addressed is obliged to generate an
acknowledge after the reception of each byte that has been clocked out of the transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge clock
pulse in such a way that the SDA line is a stable low during the high period of the
acknowledge related clock pulse. Of course, setup and hold times must be taken into
account. A master receiver must signal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that has been clocked out of the slave. In this
case the transmitter must leave the data line high to enable the master to generate the
STOP condition.
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Operating modes
M41ST87W
Figure 6: Serial bus data transfer sequence
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
START
CONDITION
CHANGE OF
DATA ALLOWED
STOP
CONDITION
Figure 7: Acknowledgement sequence
CLOCK PULSE FOR
ACKNOWLEDGEMENT
S TAR T
SCL FROM
MASTER
1
DATA OUTPUT
BY TRANSMITTER
2
MSB
8
9
LSB
DATA OUTPUT
BY RECEIVER
Figure 8: Bus timing requirements sequence
SDA
tBUF
tHD:STA
tR
tHD:STA
tF
SCL
tHIGH
P
14/54
S
tLOW
tSU:DAT
tHD:DAT
DocID9497 Rev 11
SR
tSU:STA
P
tSU:STO
M41ST87W
Operating modes
Table 3: AC characteristics
Symbol
Parameter
(1)
f SCL
SCL clock frequency
tBUF
Time the bus must be free before a new transmission can start
(2)
tEXPD
tF
tHD:DAT
Min
Max
Unit
0
400
kHz
1.3
M41ST87Y
EX to E̅CON propagation delay
10
ns
15
ns
300
ns
M41ST87W
SDA and SCL fall time
(3)
µs
Data hold time
0
µs
START condition hold time
(after this period the first clock pulse is generated)
600
ns
tHIGH
Clock high period
600
ns
tLOW
Clock low period
1.3
µs
tHD:STA
tR
SDA and SCL rise time
300
ns
tSU:DAT
Data setup time
100
ns
tSU:STA
START condition setup time
(only relevant for a repeated start condition)
600
ns
tSU:STO
STOP condition setup time
600
ns
Notes:
(1)
(2)
(3)
Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 4.5 to 5.5 V or 2.7 to 3.6 V (except where noted).
Available in SOX28 package only.
Transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of the falling edge of SCL.
2.2
READ mode
In this mode the master reads the M41ST87Y/W slave after setting the slave address (see
Figure 9: "Slave address location"). Following the WRITE mode control bit (R/W̅ =0) and the
acknowledge bit, the word address 'An' is written to the on-chip address pointer. Next the
START condition and slave address are repeated followed by the READ mode control bit
(R/W̅ =1). At this point the master transmitter becomes the master receiver.
The data byte which was addressed will be transmitted and the master receiver will send
an acknowledge bit to the slave transmitter. The address pointer is only incremented on
reception of an acknowledge clock. The M41ST87Y/W slave transmitter will now place the
data byte at address An+1 on the bus, the master receiver reads and acknowledges the
new byte and the address pointer is incremented to An+2.
This cycle of reading consecutive addresses will continue until the master receiver sends a
STOP condition to the slave transmitter (see Figure 10: "READ mode sequence").
The system-to-user transfer of clock data will be halted whenever the address being read is
a clock address (00h to 07h). The update will resume either due to a stop condition or
when the pointer increments to a non-clock or RAM address.
Note: This is true both in READ mode and WRITE mode.
An alternate READ mode may also be implemented whereby the master reads the
M41ST87Y/W slave without first writing to the (volatile) address pointer. The first address
that is read is the last one stored in the pointer (see Figure 11: "Alternate READ mode
sequence").
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Operating modes
M41ST87W
Figure 9: Slave address location
R/W
SLAVE ADDRESS
1
A
LSB
MSB
START
1
0
1
0
0
0
ACK
DATA n+1
ACK
DATA n
S
ACK
BUS ACTIVIT Y:
R/W
START
R/W
WORD
ADDRESS (An)
S
ACK
SDA LINE
ACK
BUS ACTIVIT Y:
MASTER
START
Figure 10: READ mode sequence
SLAVE
ADDRESS
STOP
SLAVE
ADDRESS
P
NO ACK
DATA n+X
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STOP
DocID9497 Rev 11
P
NO ACK
SLAVE
ADDRESS
DATA n+X
ACK
BUS ACTIVITY:
DATA n+1
ACK
DATA n
ACK
S
ACK
SDA LINE
R/W
BUS ACTIVITY:
MASTER
START
Figure 11: Alternate READ mode sequence
M41ST87W
2.3
Operating modes
WRITE mode
In this mode the master transmitter transmits to the M41ST87Y/W slave receiver. Bus
protocol is shown in Figure 12: "WRITE mode sequence". Following the START condition
and slave address, a logic '0' (R/W̅ = 0) is placed on the bus and indicates to the
addressed device that word address An will follow and is to be written to the on-chip
address pointer. The data word to be written to the memory is strobed in next and the
internal address pointer is incremented to the next memory location within the RAM on the
reception of an acknowledge clock. The M41ST87Y/W slave receiver will send an
acknowledge clock to the master transmitter after it has received the slave address (see
Figure 9: "Slave address location") and again after it has received the word address and
each data byte.
STOP
R/W
DATA n+X
P
ACK
DATA n+1
ACK
BUS ACTIVIT Y:
DATA n
ACK
WORD
ADDRESS (An)
S
ACK
SD A LINE
ACK
BUS ACTIVIT Y:
MASTER
START
Figure 12: WRITE mode sequence
SL AVE
ADDRESS
Figure 13: WRITE cycle timing: RTC and external SRAM control signals
EX
(1)
t EXPD
t EXPD
ECON
1.
2.4
(1)
Available in SOX28 package only.
Data retention mode
With valid VCC applied, the M41ST87Y/W can be accessed as described above with READ
or WRITE cycles. Should the supply voltage decay, the M41ST87Y/W will automatically
deselect, write protecting itself (and any external SRAM) when VCC falls between VPFD
(max) and VPFD (min) (see Figure 28: "Power down/up mode AC waveforms", Table 21:
"Power down/up AC characteristics"). This is accomplished by internally inhibiting access
to the clock registers. At this time, the reset pin (RST) is driven active and will remain active
until VCC returns to nominal levels. External RAM access is inhibited in a similar manner by
forcing E̅CON to a high level. This level is within 0.2 volts of the VBAT. E̅CON will remain at this
level as long as VCC remains at an out-of-tolerance condition. When VCC falls below the
battery backup switchover voltage (VSO), power input is switched from the VCC pin to the
battery, and the clock registers and external SRAM are maintained from the attached
battery supply.
All signal outputs become high impedance. The VOUT pin is capable of supplying 100 µA of
current to the attached memory with less than 0.3 volts drop under this condition. On power
up, when VCC returns to a nominal value, write protection continues for trec by inhibiting
DocID9497 Rev 11
17/54
Operating modes
M41ST87W
E̅CON. The RST signal also remains active during this time (see Figure 28: "Power down/up
mode AC waveforms").
Note: Most low power SRAMs on the market today can be used with the M41ST87Y/W
RTC SUPERVISOR. There are, however some criteria which should be used in making the
final choice of an SRAM to use. The SRAM must be designed in a way where the chip
enable input disables all other inputs to the SRAM. This allows inputs to the M41ST87Y/W
and SRAMs to be “Don’t Care” once VCC falls below VPFD(min). The SRAM should also
guarantee data retention down to VCC = 2.0 volts. The chip enable access time must be
sufficient to meet the system needs with the chip enable output propagation delays
included. If the SRAM includes a second chip enable pin (E2), this pin should be tied to
VOUT.
If data retention lifetime is a critical parameter for the system, it is important to review the
data retention current specifications for the particular SRAMs being evaluated. Most
SRAMs specify a data retention current at 3.0 volts. Manufacturers generally specify a
typical condition for room temperature along with a worst case condition (generally at
elevated temperatures). The system level requirements will determine the choice of which
value to use. The data retention current value of the SRAMs can then be added to the IBAT
value of the M41ST87Y/W to determine the total current requirements for data retention.
The available battery capacity for the battery of your choice can then be divided by this
current to determine the amount of data retention available.
For a further more detailed review of lifetime calculations, please see application note
AN1012.
2.5
Tamper detection circuit
The M41ST87Y/W provides two independent input pins, the tamper pin 1 input (TP1IN) and
tamper pin 2 input (TP2IN), which can be used to monitor two separate signals which can
result in the associated setting of the tamper bits (TB1 and/or TB2, in flag register 0Fh) if
the tamper enable bits (TEB1 and/or TEB2) are enabled, for the respective tamper 1 or
tamper 2 channels. The TP1IN pin or TP2IN pin may be set to indicate a tamper event has
occurred by either 1) closing a switch to ground or VOUT (normally open), or by 2) opening a
switch that was previously closed to ground or VOUT (normally closed), depending on the
state of the TCMX bits and the TPMX bits in the tamper register (14h and/or 15h).
2.6
Tamper register bits (tamper 1 and tamper 2)
2.6.1
Tamper enable bits (TEB1 and TEB2)
When set to a logic '1,' this bit will enable the tamper detection circuit. This bit must be set
to '0' in order to clear the associated tamper bits (TBX, in 0Fh).
Note: TEBX should be cleared then set again whenever the tamper detect condition is
modified.
When servicing a tamper interrupt, the TEBx bits must be cleared to clear the TBx bits, then
set to 1 to again enable the tamper detect circuits.
2.6.2
Tamper bits (TB1 and TB2)
If the TEBX bit is set, and a tamper condition occurs, the TBX bit will be set to '1.' This bit is
“Read-only” and is reset only by setting the TEBX bit to '0.' These bits are located in the
flags register 0Fh.
18/54
DocID9497 Rev 11
M41ST87W
2.6.3
Operating modes
Tamper interrupt enable bits (TIE1 and TIE2)
If this bit is set to a logic '1,' the IRQ/OUT pin will be activated when a tamper event occurs.
This function is also valid in battery backup if the ABE bit (alarm in battery backup) is also
set to '1' (see Figure 15: "Basic tamper detect options").
Note: In order to avoid an inadvertent activation of the IRQ/OUT pin due to a prior tamper
event, the flag register (0Fh) should be read prior to clearing and again setting the TEBX
bit.
2.6.4
Tamper connect mode bit (TCM1 and TCM2)
This bit indicates whether the position of the external switch selected by the user is in the
normally open (TCMX = '1') or normally closed (TCMX = '0') position (see Figure 14:
"Tamper detect connection options" and Figure 16: "Tamper detect output options").
2.6.5
Tamper polarity mode bits (TPM1 and TPM2)
The state of this bit indicates whether the tamper pin input will be taken high (to VOUT if
TPMX = '1') or low (to VSS if TPMX = '0') to trigger a tamper event (see Figure 14: "Tamper
detect connection options" and Figure 16: "Tamper detect output options").
Figure 14: Tamper detect connection options
TAMPER LO
(TPM X = 0)
TAMPER HI
(TPM X = 1)
I.
II.
V OUT
NORMAL LY
OPEN
(TCM X = 1)
TP IN
III.
IV.
V OUT
(2)
V CC
TP IN
NORMAL LY
CLOSED
(TCM X = 0)
(1)
TP IN
TCHI/TCLO = 1
V OUT (Int)
(3)
TCHI/TCLO = 0
TCHI/TCLO = 1
TCHI/TCLO = 0
Note: These options are summarized in Table 4: "Tamper detection truth table".
1.
2.
3.
If the CLRXEXT bit is set, a second tamper to VOUT (TPM2 = '1') during tCLR will not be
detected.
If the CLRXEXT bit is set, a second tamper to VOUT (TPM2 = '1') will trigger
automatically.
Optional external resistor to VCC allows the user to bypass sampling when power is
“on.”
DocID9497 Rev 11
19/54
Operating modes
M41ST87W
Table 4: Tamper detection truth table
Option
Mode
TCMX
TPMX
I
(1)
Normally open/tamper to GND
1
0
II
Normally open/tamper to
(1)
VOUT
1
1
III
Normally closed/tamper to GND
0
0
IV
Normally closed/tamper to VOUT
0
1
Notes:
(1)
No battery current drawn during battery backup.
Figure 15: Basic tamper detect options
Triggering Event
Tamper Event Output
VCC (VOUT)
TCMX, TPMX = 1,1
VCC (VOUT)
TIEX
TAMPER HI,
NORMALLY OPEN
TCMX, TPMX = 0,0
User
Configuration
TAMPER LO,
NORMALLY CLOSED
CLRXEX T
TCMX, TPMX = 1,0
CLRX
TAMPER LO,
NORMALLY OPEN
VCC (VOUT)
IRQ - Interrupt the
processor on tamper
TPCLR - Clearexternal
RAM on tamper(1)
CLR - Clear internal
RAM on tamper
TCMX ,TPMX
Time stamp tamper
event
TCMX, TPMX = 0,1
TAMPER HI,
NORMALLY, CLOSED
1.
Available in SOX28 package only.
Figure 16: Tamper detect output options
User
Configuration
IRQ - Interrupt the
processor on tamper
TIE1
TPCLR - Clear external
RAM on tamper (1)
CLR1 EXT
TP1
CLR1
(other reset sources)
TEB1
RESET OUT
CLR - Clear 128 bytes
internal RAM on tamper
Time stamp tamper
event (to RTC)
TIE2
TP2
CLR2 EXT
TEB2
CLR2
1.
20/54
Available in SOX28 package only.
DocID9497 Rev 11
M41ST87W
2.6.6
Operating modes
Tamper detect sampling (TDS1 and TDS2)
This bit selects between a 1 Hz sampling rate or constant monitoring of the tamper input
pin(s) to detect a tamper event when the normally closed switch mode is selected. This
allows the user to reduce the current drain when the TEBX bit is enabled while the device is
in battery backup (see Table 5: "Tamper detection current (normally closed - TCMX = '0')"
and Figure 17: "Tamper detect sampling options"). Sampling is disabled if the TCMX bit is
set to logic '1' (Normally Open). In this case the state of the TDSX bit is a “Don’t care.”
Note: The crystal oscillator must be “on” for sampling to function. If the oscillator is stopped,
the tamper detect circuit will revert to continuous monitoring.
2.6.7
Tamper current high/tamper current low (TCHI/1 and TCHI/2)
This bit selects the strength of the internal pull-up or pull-down used during the sampling of
the normally closed condition. The state of the TCHI/TCLOX bit is a “Don’t care” for normally
open (TCMX = '1') mode (see Figure 18: "Tamper current options").
2.6.8
RAM clear (CLR1 and CLR2)
When either CLR1 or CLR2 and the TEBX bit are set to a logic '1,' the internal 128 bytes of
user RAM (see Figure 15: "Basic tamper detect options") will be cleared to all zeros in the
event of a tamper condition. Furthermore, the 128 bytes of user RAM will be deselected
(inaccessible) until the corresponding TEBX bit is reset to '0.' Any data read during this time
will be invalid. (ie. the cleared RAM values cannot be accessed.)
2.6.9
RAM clear external (CLR1EXT and CLR2EXT) - available in SOX28
package only
When either CLR1EXT or CLR2EXT is set to a logic '1' and the TEBX bit is also set to logic '1,'
the TPCLR signal will be asserted for clearing external RAM, and the RST output asserted
upon detection of a tamper event (see Figure 15: "Basic tamper detect options" and Figure
20: "RAM clear hardware hookup (SOX28 package only)").
Note: The reset output resulting from a tamper event will be the same as a reset resulting
from a power-down condition, a watchdog time-out, or a manual reset (RSTIN1 or RSTIN2);
the RST output will be asserted for trec seconds.
This is accomplished by forcing TPCLR high, which if used to control the inhibit pin of the DC
regulator (see Figure 20: "RAM clear hardware hookup (SOX28 package only)") will also
switch off VOUT, depriving the external SRAM of power to the VCC pin. VOUT will
automatically be disconnected from the battery if the tamper occurs during battery back-up
(see Figure 19: "Tamper output timing (with CLR1EXT or CLR2EXT = '1') - available in
SOX28 package only"). By inhibiting the DC regulator, the user will also prevent other
inputs from sourcing current to the external SRAM, which would allow it to retain data
otherwise.
The user may optionally connect an inverting charge pump to the VCC pin of the external
SRAM (see Figure 20: "RAM clear hardware hookup (SOX28 package only)"). Depending
on the process technology used for the manufacturing of the external SRAM, clearing the
memory may require varying durations of negative potential on the VCC pin. This device
configuration will allow the user to program the time needed for their particular application.
Control Bits CLRPW0 and CLRPW1 determine the duration TPCLR will be enabled (see
Figure 19: "Tamper output timing (with CLR1EXT or CLR2EXT = '1') - available in SOX28
package only" and Table 6: "Tamper detect timing").
Note: When using the inverting charge pump, the user must also provide isolation in the
form of two additional small-signal power MOSFETs. These will isolate the VOUT pin from
both the negative voltage generated by the charge pump during a tamper condition, and
DocID9497 Rev 11
21/54
Operating modes
M41ST87W
from being pulled to ground by the output of the charge pump when it is in shut-down mode
(SHDN = logic low). The gates of both MOSFETs should be connected to TPCLR as shown
in Figure 20: "RAM clear hardware hookup (SOX28 package only)". One n-channel
enhancement MOSFET should be placed between the output of the inverting charge pump
and the VOUT of the M41ST87. The other MOSFET should be an enhancement mode pchannel, and placed between VOUT of the M41ST87 and VCC of the external SRAM. When
TPCLR goes high after a tamper condition occurs, the n-channel MOSFET will turn on and
the p-channel will turn off. During normal operating conditions, TPCLR will be low and the pchannel will be on, while the n-channel will be off.
Table 5: Tamper detection current (normally closed - TCMX = '0')
Tamper circuit mode
Current at 3.0 V (typ)
(1)(2)
TDSX
TCHI/X
0
0
Continuous monitoring / 10 MW pull-up/-down
0.3
µA
0
1
Continuous monitoring / 1 MW pull-up/-down
3.0
µA
1
0
Sampling (1 Hz) / 10 MW pull-up/-down
0.3
nA
1
1
Sampling (1 Hz) / 1 MW pull-up/-down
3.0
nA
Notes:
(1)
Per tamper detect input
(2)
When calculating battery lifetime, this current should be added to IBAT current listed in Table 19: "DC characteristics".
Figure 17: Tamper detect sampling options
VCC (VOUT)
CONTINUOUS
MONITORING
TAMPER HI,
NORMALLY OPEN
VCC (VOUT)
CONTINUOUS
MONITORING
SAMPLED
MONITORING
TAMPER LO,
NORMALLY, CLOSED
TDSX = 0
User
Configuration
TDSX = 1
TCMX, TPMX
CONTINUOUS
MONITORING
TAMPER LO,
NORMALLY OPEN
VCC (VOUT)
CONTINUOUS
MONITORING
TAMPER HI,
NORMALLY CLOSED
22/54
SAMPLED
MONITORING
DocID9497 Rev 11
TDSX = 0
TDSX = 1
Unit
M41ST87W
Operating modes
Figure 18: Tamper current options
V CC (V OU T )
CONTINUOUS
MONI TORING
TAMPER HI ,
NORMAL LY OPEN
V CC (V OU T )
CONTINUOUS
MONI TORING
TAMPER LO,
NORMAL LY CLOSED
TCHI/TCLO = 1
TCHI/TCLO = 0
SAMPLED
MONI TORING
TDS X = 0
User
Configuration
TDS X = 1
TCM X , TPM X
User Configuration
TP X (TP1, TP2)
CONTINUOUS
MONI TORING
V CC (V OU T )
TAMPER LO,
NORMAL LY OPEN
User Configuration
TCHI/TCLO = 1
TCHI/TCLO = 0
CONTINUOUS
MONI TORING
SAMPLED
MONI TORING
TAMPER HI,
NORMAL LY CLOSED
TDS X = 0
TDS X = 1
Figure 19: Tamper output timing (with CLR1EXT or CLR2EXT = '1') - available in SOX28
package only
TPCLR
t CLRD
t CLR
trec
RST
VOUT
IRQ/OUT
(1)
High-Z
(2)
(3)
(4)
High-Z
ECON
Tamper
Event
(TB Bit set)
1.
2.
3.
4.
If connected to a negative charge pump device, this pin must be isolated from the
charge pump by using both n-channel and p-channel MOSFETs as illustrated in
Figure 20: "RAM clear hardware hookup (SOX28 package only)".
If the device is in battery back-up; NOT on VCC (see Section 2.6.9: "RAM clear
external (CLR1EXT and CLR2EXT) - available in SOX28 package only"). VOUT is
forced to GND during a tamper event when on VCC.
If TIEX = '1.'
If ABE = '1' and device is in battery backup mode.
DocID9497 Rev 11
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Operating modes
M41ST87W
Table 6: Tamper detect timing
Symbol
Parameter
(1)
tCLRD
CLRPW1
Tamper RAM clear ext delay
tCLR
Tamper clear timing
CLRPW0
Min
1.0
Typ
Max
Unit
1.5
2.0
ms
(2)
X
X
0
0
1
s
0
1
4
s
1
0
8
s
1
1
16
s
Notes:
(1)
With input capacitance = 70 pF and resistance = 50 Ω.
(2)
If the OF bit is set, tCLRD(min) = 0.5 ms.
Figure 20: RAM clear hardware hookup (SOX28 package only)
Inverting
Charge
Pump
IN
Negative Output
(–1 x VIN)
OUT
SHDN
Inhibit
VIN
VCC
5V
Regulator
(1)
M41ST87Y/W
VCC
TPCLR
CAP+ CAP–
TP1IN
(2)
TP2IN
VOUT
VCC
SCL
ECON
E
WDI
SDA
RSTIN1
RST
RSTIN2
SQW/FT
EX
Pushbutton
Reset
PFO1
PFI1
Low-Power
SRAM
To RST
To LED Display
To NMI
PFO2
PFI2
VSS
VBAT
1.
2.
24/54
IRQ/OUT
F32k
To INT
To 32kHz
Most inverting charge pumps drive OUT to ground when device shut down is enabled
(SHDN = logic low). Therefore, an n-channel enhancement mode MOSFET should be
used to isolate the OUT pin from the VOUT of the M41ST87.
In order to avoid turning on an on-chip parasitic diode when driving VOUT negative, a pchannel enhancement mode MOSFET should be used to isolate the VOUT pin from the
negative voltage generated by the inverting charge pump.
DocID9497 Rev 11
M41ST87W
2.7
Operating modes
Tamper detection operation
The tamper pins are triggered based on the state of an external switch. Two switch mode
options are available, normally open or normally closed, based on the setting of the tamper
connect mode bit (TCMX). If the selected switch mode is normally open (TCMX = '1'), the
tamper pin will be triggered by being connected to VSS (if the TPMX bit is set to '0') or to VCC
(if the TPMX bit is set to '1'), through the closing of the external switch. When the external
switch is closed, the tamper bit (TBx) will be immediately set, allowing the user to determine
if the device has been physically tampered with. If the selected switch mode is normally
closed (TCMX = '0'), the tamper pin will be triggered by being pulled to VSS or to VOUT
(depending on the state of the TPMX bit), through an internal pull-up/pull-down resistor as a
result of opening the external switch.
When a tamper event occurs, the tamper bits (TB1 and/or TB2) will be immediately set if
TEBX = '1.'
If the tamper interrupt enable bit (TIEX) is set to a '1,' the IRQ/OUT pin will also be
activated. The IRQ/OUT output is cleared by a READ of the flags register (as seen in
Figure 24: "Alarm interrupt reset waveform"), a reset of the TIE bit to '0,' or the RST output
is asserted.
Note: In order to avoid an inadvertent activation of the IRQ/OUT pin due to a prior tamper
event, the flag register (0Fh) should be read prior to resetting the TEBX bit.
The tamper bits are “read only” bits and are reset only by writing the tamper enable bit
(TEBX) to '0.' Thus, when servicing a tamper interrupt, the user should read the flags
register to clear the IRQ pin, then clear the TEBx bit to clear the TBx flag, followed by setting
TEBx to again enable the tamper circuit.
The tamper detect function operates both under normal power, and in battery backup. Even
if the trigger event occurs during a power-down condition, the tamper flag bit(s) will be set
correctly.
2.8
Sampling
As the switch mode normally closed (TCMX = '0') requires a greater amount of current to
maintain constant monitoring, the M41ST87Y/W offers a programmable tamper detect
sampling bit (TDSX) to reduce the current drawn on VCC or VBAT (see Figure 17: "Tamper
detect sampling options"). When enabled, the sampling frequency is once per second
(1Hz), for a duration of approximately 1 ms.
When TEBX is disabled, no current will be drawn by the tamper detection circuit. After a
tamper event has been detected, no additional current will be drawn.
Note: The oscillator must be running for tamper detection to operate in the sampling mode.
If the oscillator is stopped, the tamper detection circuit will revert to constant monitoring.
Note: Sampling in the tamper high mode (TPMX = '1') may be bypassed while on VCC by
connecting the TPxIN pin to VCC through an external resistor. This will allow constant
monitoring when VCC is “on” and revert to sampling when in battery backup (see Figure 14:
"Tamper detect connection options").
DocID9497 Rev 11
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Operating modes
2.9
M41ST87W
Internal tamper pull-up/down current
Depending on the capacitive and resistive loading of the tamper pin input (TPXIN), the user
may require more or less current from the internal pull-up/down used when monitoring the
normally closed switch mode. The state of the tamper current hi/tamper current low bit
(TCHI/TCLOX) determines the sizing of the internal pull-up/-down. TCHI/TCLOX = '1' uses a
1 MΩ pull-up/-down resistor, while TCHI/TCLOX = '0' uses a 10 MΩ pull-up/-down resistor
(see Figure 18: "Tamper current options").
2.10
Avoiding inadvertent tampers (normally closed
configuration)
In some applications it may be necessary to use a low pass filter to reduce electrical noise
on the tamper input pin when the TCMX bit = 0 (normally closed). This is especially true if
the tamper detect switch is located some distance (> 6”) from the tamper input pin. A low
pass filter can prevent unwanted, higher frequency noise from inadvertently being detected
as a tamper condition caused by the “antenna-effect” (produced by a longer signal wire or
mesh). This low pass filter can be constructed using a series resistor (R) in conjunction with
a capacitor (C) on the tamper input pin.
The cut-off frequency fc is determined according to the formula:
fc = 1/(2 • Pi • R • C)
Figure 21: Low-pass filter implementation for noise immunity
TPIN
To Tamper Detect Switch
R
C
Table 7: Calculated cutoff frequency for typical capacitance and resistance values
26/54
R (Ω)
C (F)
fc
1/fc (s)
1000
1.00E-09
15.9 MHz
6.28 µs
1000
1.00E-06
159.2 Hz
6.28 ms
5000
1.00E-09
31.8 kHz
31.4 µs
5000
1.00E-06
31.8 Hz
31.4 ms
10000
1.00E-09
15.9 kHz
62.8 µs
10000
1.00E-06
15.9 Hz
62.8 ms
DocID9497 Rev 11
M41ST87W
2.11
Operating modes
Tamper event time-stamp
Regardless of which tamper occurs first, not only will the appropriate tamper bit be set, but
the event will also be automatically time-stamped. This is accomplished by freezing the
normal update of the clock registers (00h through 07h) immediately following a tamper
event. Thus, when tampering occurs, the user may first read the time registers to determine
exactly when the tamper event occurred, then re-enable the clock update to the current
time (and reset the tamper bit, TBX) by resetting the tamper enable bit (TEBX).
The time update will then resume and the clock can be read to determine the current time.
Both tamper enable bits (TEBX) must always be set to '0' in order to read the current time.
In the event of multiple tampers, the time-stamp will reflect the initial tamper event.
Note: If the TEBX bit is set, the tamper event time-stamp will take precedence over the
power down time-stamp (see Section 3.1: "Power-down time-stamp") and the HT bit (halt
update) will not be set during the power-down event. If both are needed, the power down
time-stamp may be accomplished by writing the time into the general purpose RAM
memory space when PFO is asserted.
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Clock operation
3
M41ST87W
Clock operation
The eight byte clock register (see Table 8: "TIMEKEEPER® register map") is used to both
set the clock and to read the date and time from the clock, in a binary coded decimal
format. Tenths/hundredths of seconds, seconds, minutes, and hours are contained within
the first four registers.
Note: A WRITE to any clock register (addresses 0 to 7h) will result in the tenths/hundredths
of seconds being reset to “00.” Furthermore, the tenths/hundredths of seconds cannot be
written to any value other than “00.”
Bits D6 and D7 of clock register 03h (century/hours register) contain the CENTURY bit 0
(CB0) and CENTURY bit 1 (CB1). Bits D0 through D2 of register 04h contain the day (day
of week). Registers 05h, 06h, and 07h contain the date (day of month), month, and years.
The ninth clock register is the control register (this is described in the clock calibration
section). Bit D7 of register 01h contains the STOP bit (ST). Setting this bit to a '1' will cause
the oscillator to stop. If the device is expected to spend a significant amount of time on the
shelf, the oscillator may be stopped to reduce current drain. When reset to a '0' the
oscillator restarts within one second (typical).
Note: A WRITE to ANY location within the first eight bytes of the clock register (00h-07h),
including the OFIE bit, CLRPW0 bit, CLRPW1 bit, THS bit, and so forth, will result in an
update of the system clock and a reset of the divider chain. This could result in a significant
corruption of the current time, especially if the HT bit (see Section 3.1: "Power-down timestamp") has not been previously reset. These non-clock related bits should be written prior
to setting the clock, and remain unchanged until such time as a new clock time is also
written.
The eight clock registers may be read one byte at a time, or in a sequential block. The
control register (address location 08h) may be accessed independently. The M41ST87 will
periodically copy the time/date counters to the user registers thus updating them. This
process is suspended when any of these 8 registers is being accessed. It is also
suspended during backup mode. Suspending the updates ensures that the clock data
being read does not change during the READ.
3.1
Power-down time-stamp
Upon power-down following a power failure, the halt update bit (HT) will automatically be
set to a '1.' This will prevent the clock from updating the user registers, and will allow the
user to read the time of the power-down event.
Note: When the HT bit is set or a tamper event occurs, the tenths/hundredths of a second
register (00h) will automatically be reset to a value of “00.” All other date and time registers
(01h - 07h) will retain the value last updated prior to the power-down or tamper event. The
internal clock remains accurate and no time is lost as a result of the zeroing of the
tenth/hundredths of a second register. When updates are resumed (due to resetting the HT
bit or TEB bit), the correct time will be displayed.
Resetting the HT bit to a '0' will allow the clock to update the user registers with the current
time.
Note: If the TEB bit is set, the power down time-stamp will be disabled, and the tamper
event time-stamp will take precedence (see Section 2.7: "Tamper detection operation").
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Clock operation
®
3.2
TIMEKEEPER registers
The M41ST87Y/W offers 22 internal registers which contain clock, control, alarm,
watchdog, flag, square wave, and tamper data. The 8 clock registers are memory locations
which contain external (user accessible) and internal copies of the data (usually referred to
™
as BiPORT TIMEKEEPER cells). The external copies are independent of internal
functions except that they are updated periodically by the simultaneous transfer of the
incremented internal copy. The internal divider (or clock) chain will be reset upon the
completion of a WRITE to any clock address (00h to 07h).
The system-to-user transfer of clock data will be halted whenever the address being
accessed is a clock address (00h to 07h). The updates will resume either due to a stop
condition or when the pointer increments to a non-clock or RAM address.
TIMEKEEPER and alarm registers store data in BCD format. Control, watchdog and
square wave registers store data in binary format.
®
Table 8: TIMEKEEPER register map
Data
Function/range
Addr
D7
00h
D6
D5
D4
D3
D2
0.1 seconds
D1
D0
BCD format
0.01 seconds
10s/100s
seconds
00-99
01h
ST
10 seconds
Seconds
Seconds
00-59
02h
OFIE
10 minutes
Minutes
Minutes
00-59
03h
CB1
CB0
Hours (24-hour format)
Century/
Hours
0-1/
00-23
04h
TR
THS
CLRP
W1
Day
01-7
05h
PFOD
0
10 date
Date: day of month
Date
01-31
06h
0
0
0
Month
Month
01-12
Year
00-99
08h
OUT
FT
S
09h
WDS
BMB4
BMB3
BMB2
0Ah
AFE
SQWE
ABE
Al 10M
0Bh
RPT4
RPT5
AI 10
date
0Ch
RPT3
HT
AI 10
hour
0Dh
RPT2
0Eh
RPT1
0Fh
WDF
AF
0
BL
0
OF
TB1
TB2
Flags
10h
0
0
0
0
0
0
0
0
Reserved
11h
0
0
0
0
0
0
0
0
Reserved
12h
0
0
0
0
0
0
0
0
Reserved
13h
RS3
RS2
RS1
RS0
SQWOD
0
0
0
SQW
TCHI/
CLR
1EXT
CLR1
Tamper1
07h
14h
10 hours
CLRP
W0
32kE
Day of week
10M
10 Years
TEB1
Year
Calibration
BMB1
BMB0
Control
RB1
RB0
Al month
01-12
Al date
01-31
Alarm hour
Al hour
00-23
Alarm 10 minutes
Alarm minutes
Al min
00-59
Alarm 10 seconds
Alarm seconds
Al sec
00-59
TIE1
TCM1
Alarm month
Watchdog
Alarm
date
TPM1
TDS1
TCLO1
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Clock operation
M41ST87W
Data
Function/range
Addr
15h
D7
D6
D5
D4
D3
TEB2
TIE2
TCM2
TPM2
TDS2
16h1Dh
ROM
1Eh1Fh
Reserved
D2
D1
D0
TCHI/
CLR
2EXT
CLR2
TCLO2
BCD format
Tamper2
Serial number
8-byte
2-byte
20h9Fh
128 user bytes
Keys:
0 = Must be set to zero
RB0-RB1 = Watchdog resolution bits
32kE = 32 kHz output enable bit
RPT1-RPT5 = Alarm repeat mode bits
ABE = Alarm in battery backup mode enable bit
RS0-RS3 = SQW frequency
AF = Alarm flag (read only)
S = Sign bit
AFE = Alarm flag enable bit
SQWE = Square wave enable
BL = Battery low flag (read only)
SQWOD = Square wave open drain bit
BMB0-BMB4 = Watchdog multiplier bits
ST = Stop bit
CB0-CB1 = Century bits
TB (1 and 2) = Tamper bits (read only)
CLR (1 and 2) = RAM clear bits
TCHI/TCLO (1 and 2) = Tamper current hi/tamper
current low bits
CLR (1 and 2)EXT = RAM clear external bits
TCM (1 and 2) = Tamper connect mode bits
CLRPW0 = RAM clear pulse width 0 bit
TDS (1 and 2) = Tamper detect sampling bits
CLRPW1 = RAM clear pulse width 1 bit
TEB (1 and 2) = Tamper enable bits
FT = Frequency test bit
THS = Threshold bit
HT = Halt update bit
TIE (1 and 2) = Tamper interrupt enable bits
OF = Oscillator fail bit
TPM (1 and 2) = Tamper polarity mode bits
OFIE = Oscillator fail interrupt enable bit
TR = trec bit
OUT = Output level
WDS = Watchdog steering bit
PFOD = Power-fail output open drain bit
WDF = Watchdog flag (read only)
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3.3
Clock operation
Calibrating the clock
The M41ST87Y/W is driven by a quartz controlled oscillator with a nominal frequency of
32,768 Hz. The devices are tested to not exceed ±35 ppm (parts per million) oscillator
°
frequency error at 25 C, with ±20 ppm crystals, which translates to about ±1.53 minutes
per month. Even better accuracy can be achieved with higher accuracy crystals. When the
calibration circuit is properly employed, accuracy can be improved to better than ±2 ppm at
25 °C.
The oscillation rate of crystals changes with temperature (see Figure 22: "Crystal accuracy
across temperature"). Therefore, the M41ST87Y/W design employs periodic counter
correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit
at the divide by 256 stage, as shown in Figure 23: "Calibration waveform". The number of
times pulses which are blanked (subtracted, negative calibration) or split (added, positive
calibration) depends upon the value loaded into the five calibration bits found in the control
register. Adding counts speeds the clock up, subtracting counts slows the clock down.
The calibration bits occupy the five lower order bits (D4-D0) in the control register (08h).
These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a
sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration
occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute,
have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary
'1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified;
if a binary 6 is loaded, the first 12 will be affected, and so on.
Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator
cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or –2.034 ppm of
adjustment per calibration step in the calibration register. Assuming that the oscillator is
running at exactly 32,768 Hz, each of the 31 increments in the calibration byte would
represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or
–2.75 minutes per month.
Two methods are available for ascertaining how much calibration a given M41ST87Y/W
may require.
The first involves setting the clock, letting it run for a month and comparing it to a known
accurate reference and recording deviation over a fixed period of time. Calibration values,
including the number of seconds lost or gained in a given period, can be found in
®
application note AN934, “TIMEKEEPER calibration.” This allows the designer to give the
end user the ability to calibrate the clock as the environment requires, even if the final
product is packaged in a non-user serviceable enclosure. The designer could provide a
simple utility that accesses the calibration byte.
The second approach is better suited to a manufacturing environment, and involves the
use of the SQW/FT pin. The pin will toggle at 512 Hz, when the stop bit (ST) is '0,' the
frequency test bit (FT) is '1,' and SQWE is '0.'
Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at
the test temperature. For example, a reading of 512.010124 Hz would indicate a +20 ppm
oscillator frequency error, requiring a –10 (XX001010) to be loaded into the calibration byte
for correction. Note that setting or changing the calibration byte does not affect the
frequency test output frequency.
If the SQWOD bit = '1,' the SQW/FT pin is an open drain output which requires a pull-up
resistor to VCC for proper operation. A 500 to 10 kΩ resistor is recommended in order to
control the rise time. The FT bit is cleared on power-down.
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Clock operation
M41ST87W
Figure 22: Crystal accuracy across temperature
Frequency (ppm)
20
0
–20
–40
–60
F
–80
= K x (T – T O )
2
2
K = –0.036 ppm/ °C ± 0.006 ppm/ °C
–100
2
T O = 25 °C ± 5 °C
–120
–140
–160
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
Temperature °C
Figure 23: Calibration waveform
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
3.4
Setting alarm clock registers
Address locations 0Ah-0Eh contain the alarm settings. The alarm can be configured to go
off at a prescribed time on a specific month, date, hour, minute, or second, or repeat every
year, month, day, hour, minute, or second. It can also be programmed to go off while the
M41ST87Y/W is in the battery back-up to serve as a system wake-up call.
Bits RPT5–RPT1 put the alarm in the repeat mode of operation. Table 9: "Alarm repeat
modes" shows the possible configurations. Codes not listed in the table default to the once
per second mode to quickly alert the user of an incorrect alarm setting.
When the clock information matches the alarm clock settings based on the match criteria
defined by RPT5–RPT1, the AF (alarm flag) is set. If AFE (alarm flag enable) is also set,
the alarm condition activates the IRQ/OUT pin as shown in Figure 25: "Backup mode alarm
waveform". To disable the alarm, write '0' to the alarm date register and to RPT5–RPT1.
If the address pointer is allowed to increment to the flag register address, an alarm
condition will not cause the interrupt/flag to occur until the address pointer is moved to a
different address. It should also be noted that if the last address written is the “alarm
seconds,” the address pointer will increment to the flag address, causing this situation to
occur. Thus the user should not leave the address pointer at 0Fh if using the alarm
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Clock operation
interrupt function. This is easily handled by simply reading past the flags registers before
teminating a read sequence.
The IRQ/OUT output is cleared by a READ to the flags register. A subsequent READ of the
flags register is necessary to see that the value of the alarm flag has been reset to '0.'
The IRQ/OUT pin can also be activated in the battery backup mode. The IRQ/OUT will go
low if an alarm occurs and both ABE (alarm in battery backup mode enable) and AFE are
set. The ABE and AFE bits are reset during power-up, therefore an alarm generated during
power-up will only set AF. The user can read the flag register at system boot-up to
determine if an alarm was generated while the M41ST87Y/W was in the deselect mode
during power-up. Figure 25: "Backup mode alarm waveform" illustrates the backup mode
alarm timing.
Figure 24: Alarm interrupt reset waveform
ADDRESS POINTER
0Eh
0Fh
10h
ACTIVE FLAG
HIGH-Z
IRQ/OU T
Table 9: Alarm repeat modes
RPT5
RPT4
RPT3
RPT2
RPT1
Alarm setting
1
1
1
1
1
Once per second
1
1
1
1
0
Once per minute
1
1
1
0
0
Once per hour
1
1
0
0
0
Once per day
1
0
0
0
0
Once per month
0
0
0
0
0
Once per year
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Clock operation
M41ST87W
Figure 25: Backup mode alarm waveform
V CC
V PFD
V SO
trec
ABE, AFE Bits in Interrupt Register
AF bit in Flags Register
IRQ/OUT
HIGH-Z
HIGH-Z
3.5
Watchdog timer
The watchdog timer can be used to detect an out-of-control microprocessor. The user
programs the watchdog timer by setting the desired amount of time-out into the watchdog
register, address 09h. Bits BMB4-BMB0 store a binary multiplier and the two lower order
bits RB1-RB0 select the resolution, where 00=1/16 second, 01=1/4 second, 10=1 second,
and 11=4 seconds. The amount of time-out is then determined to be the multiplication of
the five-bit multiplier value with the resolution. (For example: writing 00001110 in the
watchdog register = 3*1 or 3 seconds).
Note: The accuracy of the timer is within ± the selected resolution.
If the processor does not reset the timer within the specified period, the M41ST87Y/W sets
the WDF (watchdog flag) and generates either a watchdog interrupt or a microprocessor
reset.
The most significant bit of the watchdog register is the watchdog steering bit (WDS). When
set to a '0,' the watchdog will activate the IRQ/OUT pin when timed-out. When WDS is set
to a '1,' the watchdog will output a negative pulse on the RST pin for trec. The watchdog
register, FT, AFE, ABE and SQWE bits will reset to a '0' at the end of a watchdog time-out
when the WDS bit is set to a '1.'
The watchdog timer can be reset by two methods: 1) a transition (high-to-low or low-tohigh) can be applied to the watchdog input pin (WDI) or 2) the microprocessor can perform
a WRITE of the watchdog register. The time-out period then starts over.
Note: The WDI pin should be tied to VSS if not used and is only available in the SOX28
package.
In order to perform a software reset of the watchdog timer, the original time-out period can
be written into the watchdog register, effectively restarting the count-down cycle.
Should the watchdog timer time-out, and the WDS bit is programmed to output an interrupt,
either a transition of the WDI pin, or a value of 00h needs to be written to the watchdog
register in order to clear the IRQ/OUT pin. This will also disable the watchdog function until
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Clock operation
it is again programmed correctly. A READ of the flags register will reset the watchdog flag
(bit D7; register 0Fh) but does not clear the IRQ/OUT pin.
The watchdog function is automatically disabled upon power-up and the watchdog register
is cleared.
3.6
Square wave output
The M41ST87Y/W offers the user a programmable square wave function which is output
on the SQW/FT pin. RS3-RS0 bits located in 13h establish the square wave output
frequency. These frequencies are listed in Table 10: "Square wave output frequency".
Once the selection of the SQW frequency has been completed, the SQW/FT pin can be
turned on and off under software control with the square wave enable bit (SQWE) located
in register 0Ah.
The SQW/FT output is programmable as an N-channel, open drain output driver, or a fullCMOS output driver. By setting the square wave open drain bit (SQWOD) to a '1,' the
output will be configured as an open drain (with IOL as specified in Table 19: "DC
characteristics"). When SQWOD is set to '0,' the output will be configured as full-CMOS
(sink and source current as specified in Table 19: "DC characteristics").
Note: When configured as open drain (SQWOD = '1'), the SQW/FT pin requires an external
pull-up resistor.
Table 10: Square wave output frequency
Square wave bits
Square wave
RS3
RS2
RS1
RS0
Frequency
Units
0
0
0
0
None
–
0
0
0
1
32.768
kHz
0
0
1
0
8.192
kHz
0
0
1
1
4.096
kHz
0
1
0
0
2.048
kHz
0
1
0
1
1.024
kHz
0
1
1
0
512
Hz
0
1
1
1
256
Hz
1
0
0
0
128
Hz
1
0
0
1
64
Hz
1
0
1
0
32
Hz
1
0
1
1
16
Hz
1
1
0
0
8
Hz
1
1
0
1
4
Hz
1
1
1
0
2
Hz
1
1
1
1
1
Hz
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Clock operation
3.7
M41ST87W
Full-time 32 kHz square wave output
The M41ST87Y/W offers the user a special 32 kHz square wave function which defaults to
output on the F32k pin (pin 21) as long as VCC ≥ VSO, and the oscillator is running
(ST bit = '0'). This function is available within one second (typ) of initial power-up and can
only be disabled by setting the 32 kE bit to '0' or the ST bit to '1.' If not used, the F32k pin
should be disconnected and allowed to float.
Note: The F32k pin is an open drain which requires an external pull-up resistor.
3.8
Power-on reset
The M41ST87Y/W continuously monitors VCC. When VCC falls to the power fail detect trip
point, the RST pulls low (open drain) and remains low on power-up for trec after VCC passes
VPFD(max). The RST pin is an open drain output and an appropriate pull-up resistor should
be chosen to control rise time.
Note: A power-on reset will result in resetting the following control bits to '0': OFIE, AFE,
ABE, SQWE, FT, WDS, BMB0-BMB4, RB0, RB1, TIE1, and TIE2 (see ).
3.9
Reset inputs ( and )
The M41ST87Y/W provides two independent inputs which can generate an output reset.
The function of these resets is identical to a reset generated by a power cycle. Table 11:
"Reset AC characteristics" and Figure 26: "RSTIN1 and RSTIN2 timing waveforms"
illustrate the AC reset characteristics of this function. Pulses shorter than tR1 and tR2 will not
generate a reset condition. RSTIN1 and RSTIN2 are each internally pulled up to VCC
through a 100 kΩ resistor. Note that RSTIN1 triggers on the falling edge while RSTIN2
triggers on the rising edge.
Note: 2 is available only in the SOX28 package.
RSTIN1
Figure 26:  and  timing waveforms
tR1
RSTIN2
tR2
Hi-Z
Hi-Z
RST
trec
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trec
M41ST87W
Clock operation
Table 11: Reset AC characteristics
Symbol
tR1
(2)
tR2
(2)
(3)
trec
Notes:
Parameter
(1)
Min
Max
Unit
RSTIN1 low to RST low (min pulse width)
100
200
ns
100
200
ns
RSTIN1 or RSTIN2 high to RST high
96
98
(3)
ms
RSTIN2 low to RSTIN2 high (min pulse width)
(1)
Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 4.5 to 5.5 V or 2.7 to 3.6 V (except where
noted).
(2)
(3)
3.10
Pulse widths of less than 100 ns will result in no RESET (for noise immunity).
Programmable (see Table 13: "trec definitions"). Same function as power-on reset.
Power-fail comparators (1 and 2)
Two power-fail inputs (PFI1 and PFI2) are compared to an internal reference voltage (1.25
V). If either PFI1 or PFI2 is less than the power-fail threshold (VPFI), the associated powerfail output (PFO1 or PFO2) will go low. This function is intended for use as an under-voltage
detector to signal a failing power supply. Typically PFI1 and PFI2 are connected through
external voltage dividers (see Figure 5: "Hardware hookup") to either the unregulated DC
input (if it is available) or the regulated output of the VCC regulator. The voltage divider can
be set up such that the voltage at PFI1 or PFI2 falls below VPFI several milliseconds before
the regulated VCC input to the M41ST87Y/W or the microprocessor drops below the
minimum operating voltage, thus providing an early warning of power failure.
During battery back-up, the power-fail comparator turns off and PFO1 and PFO2 go (or
remain) low. This occurs after VCC drops below VPFD(min). When power returns, PFO1 and
PFO2 are forced high, irrespective of VPFI for the write protect time (trec), which is the time
from VPFD(max) until the inputs are recognized. At the end of this time, the power-fail
comparator is enabled and PFO1 and PFO2 follow PFI1 and PFI2. If the comparator is
unused, PFI1 or PFI2 should be connected to VSS and the associated PFO1 or PFO2 left
unconnected.
3.11
Power-fail outputs
The PFO1 and PFO2 outputs are programmable as N-channel, open drain output drivers, or
full-CMOS output drivers. By setting the power-fail output open drain bit (PFOD) to a '1,' the
output will be configured as open drain (with IOL as specified in Table 19: "DC
characteristics"). When PFOD is set to '0,' the outputs will be configured as full-CMOS (sink
and source current as specified in Table 19: "DC characteristics").
Note: When configured as open drain (PFOD = '1'), PFO1 and PFO2 will require an external
pull-up resistor.
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Clock operation
3.12
M41ST87W
Century bits
These two bits will increment in a binary fashion at the turn of the century, and handle leap
years correctly. Refer to Table 12: "Century bits examples". These bits represent the next
higher order bits of the years register (07h), and should be set accordingly. For example,
for the year 2100, they would be set to 1 (D7 = 0 and D6 = 1), and for the year 2300, they
would be set to 3 (D7 = 1 and D6 = 1). Once set, they will increment every 100 years.
Provided they are set as described above, the date register (05h) will properly manage leap
day at the turn of any century. Leap day does not occur in turn-of-century years except for
those which are multiples of 400. Thus, with CB1 and CB0 properly set, the device will omit
leap day from the appropriate turn-of-century years.
Table 12: Century bits examples
CB1
CB0
Leap year?
Example
0
0
Yes
2000
0
1
No
2100
1
0
No
2200
1
1
No
2300
(1)
Notes:
(1)
Leap year occurs every four years (for years evenly divisible by four), except for years evenly divisible by 100.
The only exceptions are those years evenly divisible by 400 (the year 2000 was a leap year, year 2100 is not).
3.13
Output driver pin
When the TIE bit, OFIE bit, AFE bit, and watchdog register are not set to generate an
interrupt, the IRQ/OUT pin becomes an output driver that reflects the contents of D7 of the
control register. In other words, when D7 (OUT bit) is a '0,' then the IRQ/OUT pin will be
driven low. With the ABE bit set to '1,' the OUT pin will continue to be driven low in battery
backup.
3.14
Note: The IRQ/OUT pin is an open drain which requires an external pull-up resistor.
Battery low warning
The M41ST87Y/W automatically performs battery voltage monitoring upon power-up and at
factory-programmed time intervals of approximately 24 hours. The battery low (BL) bit, bit
D4 of flags register 0Fh, will be set if the battery voltage is found to be less than
approximately 2.5 V. The BL bit will remain set until completion of battery replacement and
subsequent battery low monitoring tests, either during the next power-up sequence or the
next scheduled 24-hour interval.
If a battery low is generated during a power-up sequence, this indicates that the battery is
below approximately 2.5 volts and may not be able to maintain data integrity in the SRAM.
Data should be considered suspect and verified as correct. A fresh battery should be
installed.
If a battery low indication is generated during the 24-hour interval check, this indicates that
the battery is near end of life. However, data is not compromised due to the fact that a
nominal VCC is supplied. In order to ensure data integrity during subsequent periods of
battery back-up mode, the battery should be replaced. The battery should be replaced
while VCC is applied to the device.
The M41ST87Y/W only monitors the battery when a nominal VCC is applied to the device.
Thus applications which require extensive durations in the battery back-up mode should be
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Clock operation
powered-up periodically (at least once every few months) in order for this technique to be
beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon
power-up via a checksum or other technique.
3.15
trec bit
Bit D7 of clock register 04h contains the trec bit (TR). trec refers to the automatic continuation
of the deselect time after VCC reaches VPFD. This allows for a voltage settling time before
WRITEs may again be performed to the device after a power-down condition. The trec bit
will allow the user to set the length of this deselect time as defined by Table 13: "trec
definitions".
Table 13: trec definitions
trec time
trec bit (TR)
STOP bit (ST)
0
0
96
98
0
1
40
200
ms
1
X
50
2000
µs
Min
Units
Max
(1)
ms
Notes:
(1)
3.16
Default setting.
Electronic serial number
The M41ST87Y/W has a unique 8-byte lasered serial number with parity. This serial
number is “read only” and is generated such that no two devices will contain an identical
number.
3.17
Oscillator stop detection
If the oscillator fail (OF) bit is internally set to a '1,' this indicates that the oscillator has
either stopped, or was stopped for some period of time, and can be used to judge the
validity of the clock and date data. This bit will be set to '1' any time the oscillator stops.
The following conditions can cause the OF bit to be set:
•
•
•
The first time power is applied (defaults to a '1' on power-up).
The voltage present on VCC or battery is insufficient to support oscillation.
The ST bit is set to '1.'
If the oscillator fail interrupt enable bit (OFIE) is set to a '1,' the IRQ/OUT pin will also be
asserted. The IRQ/OUT output is cleared by resetting the OF bit to '0,' resetting the OFIE
bit to '0,' or if the RST output is asserted (but is NOT cleared by reading the flag register).
The OF bit will remain set to '1' until written to logic '0.' The oscillator must start and have
run for at least 4 seconds before attempting to reset the OF bit to '0.' This function operates
both under normal power and in battery backup. If the trigger event occurs during a powerdown condition, this bit will be set correctly.
Note: The ABE bit must be set to '1' for the IRQ/OUT pin to be activated in battery backup.
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Clock operation
3.18
M41ST87W
Initial power-on defaults
Table 14: Default values
Condition
Initial power-up
(3)(4)
Subsequent power-up (with battery backup)
TR
ST
OF
OFIE
HT
0
0
1
0
UC
UC
UC
0↑
(1)
(2)
Out
FT
AFE
ABE
SQWE
SQWOD
PFOD
Watchdog register
1
1
0
0
0
0
1
1
0
0↓
UC
0↓
0↑
0↑
0↑
UC
UC
0↓
Notes:
(1)
When TEBX is set to '1,' the HT bit will not be set on power-down (tamper time-stamp will have precedence).
(2)
WDS, BMB0-BMB4, RB0, RB1.
(3)
↑ = VCC rising; ↓ = VCC falling.
(4)
UC = unchanged.
Table 15: Default values
Condition
32kE
Initial power-up
1
Subsequent power-up
(2)
(with battery backup)
UC
(1)
THS
TEB1
and 2
TCM1
and 2
TPM1
and 2
TDS1
and 2
0
0
0
0
0
UC
UC
UC
UC
UC
Notes:
(1)
(2)
32 kHz output valid only on VCC.
UC = unchanged.
Note: All other control bits are undetermined.
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DocID9497 Rev 11
TCHI/
1 and
2
CLR1
and 2
TIE1
and 2
CLRPW0
CLRPW1
CLR1EXT and
CLR2EXT
0
0
0
0
0
0
UC
UC
0↑
UC
UC
UC
M41ST87W
4
Maximum ratings
Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 16: Absolute maximum ratings
Symbol
TSTG
Parameter
Storage temperature (VCC off, oscillator off)
TSLD
Lead solder temperature for 10 seconds
VIO
Input or output voltage
VCC
Supply voltage
IO
Output current
PD
Power dissipation
SSOP20
SOX28
Thermal resistance, junction to ambient
Tj
Max. operating junction temperature
Unit
–55 to 125
°C
260
(1)
°C
240
(2)
°C
–0.3 to VCC+0.3
V
M41ST87Y
–0.3 to 7.0
V
M41ST87W
–0.3 to 4.6
V
20
mA
1
W
83.0
°C/W
SSOP20
θJA
Value
SOX28
°C/W
SSOP20
SOX28
125
°C
Notes:
(1)
(2)
Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds.
Reflow at peak temperature of 240 °C. The time above 235°C must not exceed 20 seconds.
Caution: Negative undershoots below –0.3 V are not allowed on any pin while in the
battery backup mode.
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DC and AC parameters
5
M41ST87W
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC
and AC characteristics of the device. The parameters in the following DC and AC
characteristic tables are derived from tests performed under the measurement conditions
listed in the relevant tables. Designers should check that the operating conditions in their
projects match the measurement conditions when using the quoted parameters.
Table 17: DC and AC measurement conditions
Parameter
M41ST87Y
M41ST87W
VCC supply voltage
4.5 to 5.5 V
2.7 to 3.6 V
Ambient operating temperature
–40 to 85 °C
–40 to 85 °C
Load capacitance (CL)
100 pF
50 pF
Input rise and fall times
≤ 50 ns
≤ 50 ns
Input pulse voltages
0.2 to 0.8VCC
0.2 to 0.8VCC
Input and output timing ref. voltages
0.3 to 0.7VCC
0.3 to 0.7VCC
Note: Output high Z is defined as the point where data is no longer driven.
Figure 27: AC testing input/output waveforms
0.8VCC
0.7VCC
0.3VCC
0.2VCC
Table 18: Capacitance
Symbol
CIN
COUT
(3)
tLP
Parameter
(1)(2)
Min
Max
Unit
Input capacitance
7
pF
Output capacitance
10
pF
Low-pass filter input time constant (SDA and SCL)
50
ns
Notes:
(1)
(2)
(3)
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At 25 °C, f = 1 MHz.
Effective capacitance measured with power supply at 5 V. Sampled only, not 100% tested.
Outputs are deselected.
DocID9497 Rev 11
M41ST87W
DC and AC parameters
Table 19: DC characteristics
Sym
IBAT
(2)
Parameter
Battery current OSC
ON
Battery current OSC
OFF
M41ST87Y
Test condition
(1)
M41ST87W
Unit
Min
TA = 25 °C,
VCC = 0 V,
VBAT = 3 V
Typ
Max
500
700
Min
50
Typ
Max
500
700
50
nA
nA
ICC1
Supply current
f = 400 kHz
1.4
0.75
mA
ICC2
Supply current
(standby)
SCL, SDA ≥
VCC– 0.3 V
1
0.50
mA
0V ≤ VIN ≤ VCC
±1
±1
µA
25
nA
Input leakage current
ILI
(3)
ILO
(4)
IOUT1
(5)
IOUT2
Input leakage current
(PFI)
–25
2
25
–25
2
Output leakage
current
0V ≤ VIN ≤ VCC
±1
±1
µA
VOUT current (active)
VOUT1 > VCC –
0.3 V
175
100
mA
VOUT current (battery
backup)
VOUT2 > VBAT –
0.3 V
100
100
µA
VIH
Input high voltage
0.7VCC
VCC +
0.3
0.7VCC
VCC +
0.3
V
VIL
Input low voltage
–0.3
0.3VCC
–0.3
0.3VCC
V
Battery voltage
2.5
VCC
2.5
VCC
V
VBAT
(6)
VOH
(7)
VOHB
Output high voltage
IOH = –1.0 mA
Pull-up supply voltage
(open drain)
IRQ/OUT, RST,
F32k
VOH (battery backup)
3.0
2.4
3.0
2.4
V
5.5
IOUT2 = –1.0 µA
3.6
2.9
(8)
2.9
V
V
Output low voltage
IOL = 3.0 mA
0.4
0.4
V
VOL
Output low voltage
(9)
(open drain)
IOL = 10 mA
0.4
0.4
V
VPFD
Power fail deselect
VPFI1,
VPFI2
PFI input threshold
PFI hysteresis
VSO
Battery backup
switchover
RSW
External switch
resistance on tamper
pin
THS bit = 0
4.20
4.35
4.50
2.55
2.62
2.70
V
THS bit = 1
4.50
4.60
4.75
2.80
2.88
3.00
V
VCC = 5 V (Y)
1.225
1.250
1.275
1.225
1.250
1.275
V
20
70
mV
VCC = 3 V (W)
PFI rising
20
70
2.5
V
2.5
500
V
500
Ω
Notes:
(1)
(2)
Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 4.5 to 5.5 V or 2.7 to 3.6 V (except where noted).
Measured with VOUT and E̅CON open. Not including tamper detection current (see Table 5: "Tamper detection current
(normally closed - TCMX = '0')").
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DC and AC parameters
M41ST87W
(3)
RSTIN1 and RSTIN2 internally pulled up to VCC through 100 kΩ resistor. WDI internally pulled-down to VSS through 100 kΩ
resistor.
(4)
(5)
(6)
(7)
Outputs deselected.
External SRAM must match RTC supervisor chip VCC specification.
For PFO1 and PFO2 (if PFOD = '0'), SQW/FT (if SQWOD = '0'), and TPCLR pins (CMOS).
Conditioned output (E̅CON) can only sustain CMOS leakage current in the battery backup mode. Higher leakage currents will
reduce battery life.
(8)
(9)
TPCLR output can source –300 µA (typ) for VBAT = 2.9 V.
For IRQ/OUT, SQW/FT (if SQWOD = '1'), PFO1 and PFO2 (if PFOD = '1'), RST, SDA, and F32k pins (open drain).
Table 20: Crystal electrical characteristics
Symbol
fO
Parameter
(1)
Min
Resonant frequency
RS
Series resistance
CL
Load capacitance
Typ
Max
32.768
kHz
65
12.5
Units
(2)
kΩ
pF
Notes:
(1)
Load capacitors are integrated within the M41ST87. Circuit board layout considerations for the 32.768 kHz crystal of minimum
trace lengths and isolation from RF generating signals should be taken into account.
(2)
TA = –40 to 85 °C (guaranteed by design).
Note: Crystal: user supplied for the 20-lead SSOP package. STMicroelectronics
recommends the KDS DT-38 (3 x 8 mm) for thru-hole, or the KDS DMX-26S for surfacemount, tuning fork-type quartz crystals.
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DocID9497 Rev 11
M41ST87W
DC and AC parameters
Figure 28: Power down/up mode AC waveforms
VCC
VPFD (max)
VPFD (min)
VSO
tF
t FB
tPD
tR
t RB
t rec
PFO
VALID
VALID
INPUTS
DON'T CARE
RECOGNIZED
RECOGNIZED
RST
HIGH-Z
OUTPUTS
VALID
VALID
(PER CONTRO L INPUT)
ECON
1.
(PER CONTRO L INPUT)
(1)
E̅CON available in the SOX28 package only.
Table 21: Power down/up AC characteristics
Symbol
tF
(2)
Parameter
(1)
Min
Typ
Max
Unit
VPFD(max) to VPFD(min) VCC fall time
300
µs
(3)
tFB
VPFD(min) to VSS VCC fall time
10
µs
tPD
EX at VIH before power down
0
µs
tR
PFI to PFO propagation delay
VPFD(min) to VPFD(max) VCC rise time
10
tRB
VSS to VPFD(min) VCC rise time
1
tPFD
trec
15
Power-up deselect time
96
25
µs
µs
µs
98
(4)
ms
Notes:
(1)
Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 4.5 to 5.5 V or 2.7 to 3.6 V (except where noted).
(2)
VPFD(max) to VPFD(min) fall time of less than tF may result in deselection/write protection not occurring until 200 µs after VCC
passes VPFD(min).
(3)
(4)
VPFD(min) to VSS fall time of less than tFB may cause corruption of RAM data.
Programmable (see Table 13: "trec definitions")
DocID9497 Rev 11
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Package information
6
M41ST87W
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
6.1
SOX28 package information
Figure 29: SOX28 – 28-lead plastic small outline, 300 mils, embedded crystal package outline
7456166_F
Note: Drawing is not to scale.
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DocID9497 Rev 11
M41ST87W
Package information
Table 22: SOX28 – 28-lead plastic small outline, 300 mils, embedded crystal package
mechanical data
millimeters
inches
Symbol
Typ
Min
Max
A
2.44
A1
Min
Max
2.69
0.096
0.106
0.15
0.31
0.006
0.012
A2
2.29
2.39
0.090
0.094
B
0.41
0.51
0.016
0.020
c
0.20
0.31
0.008
0.012
D
17.91
18.01
0.705
0.709
E
7.57
7.67
0.298
0.302
–
–
–
–
E1
10.16
10.52
0.400
0.414
L
0.51
0.81
0.020
0.032
0°
8°
0°
8°
e
1.27
α
N
28
Typ
0.050
28
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Package information
6.2
M41ST87W
SSOP20 package information
Figure 30: SSOP20 – 20-lead, shrink, small outline package outline
0061436_C
Table 23: SSOP20 – 20-lead, shrink, small outline package mechanical data
mm
in
Sym
Min
Typ
A
Min
Typ
2.000
A1
0.050
A2
1.650
b
Max
0.079
0.002
1.850
0.065
0.220
0.380
0.009
0.015
c
0.090
0.250
0.004
0.010
D
6.900
7.200
7.500
0.272
E
7.400
7.800
8.200
E1
5.000
5.300
5.600
e
L
k
ddd
1.750
0.550
0.750
4d
0.073
0.295
0.291
0.307
0.323
0.197
0.209
0.220
0.026
0.950
0.022
1.250
0d
0.069
0.283
0.650
L1
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Max
0.030
0.037
0.049
8d
0.100
DocID9497 Rev 11
0d
4d
8d
0.004
M41ST87W
Packing information
7
Packing information
7.1
SOX28 carrier tape
Figure 31: Carrier tape for SOX28 package
P0
E
P2
D
T
A0
F
TOP COVER
TAPE
W
B0
P1
CENTER LINES
OF CAVITY
K0
USER DIRECTION OF FEED
Table 24: Carrier tape dimensions for SOX28 package
Package
W
D
E
P0
P2
F
A0
B0
K0
P1
T
Unit
SOX28
24.00
±0.30
1.50
+0.10/
–0.00
1.75
±0.10
4.00
±0.10
2.00
±0.10
11.50
±0.10
12.70
±0.10
18.20
±0.10
3.20
±0.10
16.00
±0.10
0.30
±0.05
mm
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Bulk
Qty
1000
Packing information
7.2
M41ST87W
SSOP20 carrier tape
Figure 32: Carrier tape for SSOP20 package
Note: All dimensions in millimeters.
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DocID9497 Rev 11
M41ST87W
7.3
Packing information
Reel information for SOX28 and SSOP20
Figure 33: Reel schematic
T
40 mm min.
access hole
at slot location
B
D
C
N
A
G measured at hub
Full radius
Tape slot
in core for
tape start
2.5 mm min. width
Table 25: Reel dimensions for 24 mm carrier tape (SOX28 package) and 16 mm carrier tape
(SSOP20 package)
A
B
(max)
(min)
24 mm (SOX28)
330 mm
(13-inch)
1.5 mm
16 mm (SSOP20)
330 mm
(13-inch)
1.5 mm
Carrier tape
D
N
(min)
(min)
13 mm
± 0.2 mm
20.2 mm
60 mm
24.4 mm
+ 2/–0 mm
30.4 mm
13 mm
± 0.2 mm
20.2 mm
60 mm
16.4 mm
+ 2/–0 mm
22.4 mm
C
G
T
(max)
Note: The dimensions given in the table above incorporate tolerances that cover all
variations on critical parameters.
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Part numbering
8
M41ST87W
Part numbering
Table 26: Ordering information scheme
Example:
M41ST
87Y
MX
6
TR
Device type
M41ST
Supply voltage and write protect voltage
87Y = VCC = 4.75 to 5.5 V
(1)
THS bit = '1': 4.50 V ≤ VPFD ≤ 4.75 V
VCC = 4.5 to 5.5 V
THS bit = '0': 4.20 V ≤ VPFD ≤ 4.50 V
87W = VCC = 3.0 to 3.6 V;
THS bit = '1': 2.80 V ≤ VPFD ≤ 3.00 V
VCC = 2.7 to 3.6 V;
THS bit = '0': 2.55 V ≤ VPFD ≤ 2.70 V
Package
MX = SOX28
(2)(3)
SS = SSOP20
(4)
Temperature range
6 = –40 to 85 °C
Shipping method
For SOX28:
®
Blank = ECOPACK package, tubes (Not for new design - use TR)
(1)
®
TR = ECOPACK package, tape and reel
For SSOP20:
®
F = ECOPACK package, tape and reel
Notes:
(1)
(2)
(3)
(4)
Not recommended for new design. Contact ST sales office for availability.
Lead-free second level interconnect and RoHS compliant (by exemption).
The SOX28 package includes an embedded 32,768 Hz crystal.
Available in 3.3 V (W) version only.
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
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M41ST87W
9
Revision history
Revision history
Table 27: Document revision history
Date
Revision
Changes
May-2002
1
First issue.
23-Apr-2003
2
Document promoted to preliminary data.
10-Jul-2003
2.1
Update tamper information (Figure 4, 5, 14, 15, 16; Table 17, 4, 12).
11-Sep-2003
2.2
Update electrical, charge pump, and clock information (Table 17;
Figure 5, 19, 20).
15-Jun-2004
3
Reformatted; added lead-free information; updated characteristics
(Figure 2; Table 1, 14, 17, 24).
7-Sep-2004
4
Update maximum ratings (Table 14).
29-Jun-2005
5
Clarify NC connections, add inadvertent tamper, update MX attribute
(Figure 2, 21; Table 1, 6, 24).
28-Mar-2006
6
Update to “Avoiding inadvertent tamper paragraph“ paragraph.
10-Sep-2008
7
Reformatted document and title change; updated cover page,
Figure 4, 15, 20, Section 6: Package mechanical data.
31-Mar-2010
8
Added SSOP 20-pin package (updated cover page, Section 1.1,
Figure 1, 4, 5, 13, 28, Table 1, 2, Section 3.4, Section 3.8, added
Figure 3, 30, Table 18, 21, Section 8); updated Table 11, 14, 17, 18,
24, Figure 10, 11, Figure 15.16, 19, 24, 27, 28, text in Section 1,
Section 2, Section 2.1, Section 2.1.5, Section 2.4, Section 2.5,
Section 2.6.1, Section 2.6.3, Section 2.6.5, Section 2.6.6,
Section 2.6.8, Section 2.6.9, Section 2.7, Section 2.8, Section 3,
Section 3.0.1, Section 3.1, Section 3.2, Section 3.3, Section 3.4,
Section 3.8, Section 3.9, Section 3.11, Section 3.13, Section 3.16,
Section 3.17, Section 6; reformatted document.
25-Jan-2011
9
5.0 V version of device (M41ST87Y) is not recommended for new
design (updated cover page, Table 24); added tape and reel
specifications (Figure 31, 32, 33, Table 22, 23).
03-Oct-2011
10
Updated Table 24: Ordering information scheme as the shipping
method in tubes is not recommended for new design.
19-May-2016
11
Updated Figure 3: "20-pin, SSOP connections"
Added Table 2: "I2C slave address"
Added Tj to Table 16: "Absolute maximum ratings"
Revised presentation of Section 6.1: "SOX28 package information"
Removed section entitled “References”
DocID9497 Rev 11
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M41ST87W
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST
products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the
design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2016 STMicroelectronics – All rights reserved
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