Data Sheet

Freescale Semiconductor
Technical Data
Document Number: MC33661
Rev. 8.0, 4/2013
Local Interconnect Network
(LIN) Enhanced Physical
Interface with Selectable SlewRate
33661
LIN PHYSICAL INTERFACE
Local interconnect network (LIN) is a serial communication protocol
designed to support automotive networks in conjunction with controller
area network (CAN). As the lowest level of a hierarchical network, LIN
enables cost-effective communication with sensors and actuators
when all the features of CAN are not required. This device is powered
by SMARTMOS technology.
The 33661 is a physical layer component dedicated to automotive
LIN sub-bus applications. It offers slew-rate selection for optimized
operation at 10 kbps and 20 kbps, fast baud rate (above 100 kbps) for
test and programming modes, excellent radiated emission
performance, and safe behavior in the event of LIN bus short-to-ground
or LIN bus leakage during low power mode.
The 33661 is compatible with LIN Protocol Specification 2.0.
EF SUFFIX (PB-FREE)
98ASB42564B
8-PIN SOICN
Features
• Operational from VSUP 6.0 V to 18 V DC, functional up to 27 V DC,
and handles 40 V during load dump
• Active bus waveshaping offering excellent radiated emission
performance
• 5.0 kV ESD on LIN bus pin
• 30 k internal pull-up resistor
• LIN bus short-to-ground or high leakage in Sleep mode
• -18 V to +40 V DC voltage at LIN pin
• 8.0 A in Sleep mode
• Local and remote wake-up capability reported by INH and RXD pins
• 5.0 V and 3.3 V compatible digital inputs without any external 
components required
ORDERING INFORMATION
Device
(For Tape and
Reel, add an R2
Suffix)
Temperature
Range (TA)
Package
MC33661PEF
- 40 to 125°C
8 SOICN
VPWR
33661
WAKE
INH
VDD
Regulator
12 V
5.0 V
VSUP
EN
MCU
RXD
LIN
TXD
GND
Figure 1. 33661 Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications,
as may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2006 - 2013. All rights reserved.
LIN Bus
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VSUP
WAKE
20 A
INH
Control
EN
INH
Control
RXD
30 k
LIN
Receiver
TXD
Slope
Control
GND
Figure 2. 33661 Simplified Internal Block Diagram
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Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
RXD
1
8
INH
EN
2
7
VSUP
WAKE
3
6
LIN
TXD
4
5
GND
Figure 3. 33661 8-SOICN Pin Connections
Table 1. 33661 8-SOICN Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page page 12.
Pin
Pin Name
Formal Name
Definition
1
RXD
Data Output
2
EN
Enable Control
3
WAKE
Wake Input
High-voltage input used to wake-up the device from Sleep mode.
4
TXD
Data Input
MCU interface to control the state of the LIN output.
5
GND
Ground
Device ground pin.
6
LIN
LIN Bus
Bidirectional pin that represents the single-wire bus transmitter and receiver.
7
VSUP
Power Supply
Device power supply pin.
8
INH
Inhibit Output
This pin can have two main functions: controlling an external switchable voltage
regulator having an inhibit input or driving a bus external resistor in the master node
application.
MCU interface that reports the state of the LIN bus voltage.
Controls the operation mode of the interface.
33661
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
ELECTRICAL RATINGS
Power Supply Voltage
VSUP
V
Continuous Supply Voltage
27
Transient Voltage (Load Dump)
40
WAKE DC and Transient Voltage (Through a 33 k Serial Resistor)
VWAKE
-18 to 40
V
Logic Voltage (RXD, TXD, EN Pins)
VLOG
- 0.3 to 5.5
V
LIN Bus Voltage
VBUS
DC Voltage
V
-18 to 40
Transient (Coupled Through 1.0 nF Capacitor)
-150 to 100
INH Voltage / Current
DC Voltage
VINH
- 0.3 to VSUP + 0.3
V
DC Current
IINH
40
mA
ESD Voltage (1)
VESD1
V
Human Body Model
All Pins
± 2000
LIN Pin with Respect to Ground
± 5000
Machine Model
VESD2
± 200
Ambient
TA
- 40 to 125
Junction
TJ
- 40 to 150
TSTG
- 55 to 150
C
RJA
150
°C/W
TPPRT
Note 3
°C
Thermal Shutdown Temperature
TSHUT
150 to 200
°C
Thermal Shutdown Hysteresis Temperature
THYST
8.0 to 20
°C
THERMAL RATINGS
Operating Temperature
C
Storage Temperature
Thermal Resistance, Junction to Ambient
Peak Package Reflow Temperature During Reflow
(2), (3)
Notes
1. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ), ESD2 testing is performed in
accordance with the Machine Model (CZAP = 220 pF, RZAP = 0 ).
2.
3.
Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL),
Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.
MC33xxxD enter 33xxx), and review parametrics.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 7.0 V  VSUP  18 V, - 40C  TA  125 C, GND = 0 V, unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
VSUP PIN (DEVICE POWER SUPPLY)
Supply Voltage
V
VSUP
Nominal DC
7.0
13.5
18.0
Functional DC, TA  25 °C
6.0
—
—
A
Supply Current in Sleep Mode
VSUP  13.5 V, Recessive State
IS1
—
8.0
12
13.5 V < VSUP < 1.0 V
IS2
—
—
200
VSUP  13.5 V, Dominant State or Shorted to GND
IS3
—
300
—
MA
Supply Current in Normal, Slow, or Fast Mode
Bus Recessive, Excluding INH Output Current
IS(REC)
—
4.0
6.0
IS(DOM)
—
6.0
8.0
0.0
—
0.9
VEN = 5.0 V, IOUT  250 A
4.25
—
5.25
VEN = 3.3 V, IOUT  250 A
3.0
—
3.5
Bus Dominant, Total Bus Load > 500 , Excluding INH Output
Current
RXD OUTPUT PIN (LOGIC)
Low Level Output Voltage
VOL
IIN  1.5 mA
High Level Output Voltage
V
VOH
V
TXD INPUT PIN (LOGIC)
Low Level Input Voltage
VIL
—
—
1.2
V
High Level Input Voltage
VIH
2.5
—
—
V
VINHYST
100
300
800
mV
- 60
- 35
- 20
Input Threshold Voltage Hysteresis
Pull-up Current Source
A
IPU
VEN = 5.0 V, 1.0 V < VTXD < 3.5 V
EN INPUT PIN (LOGIC)
Low Level Input Voltage
VIL
—
—
1.2
V
High Level Input Voltage
VIH
2.5
—
—
V
VINHYST
100
300
800
mV
5.0
20
30
—
20
40
Input Voltage Threshold Hysteresis
Low Level Input Current
High Level Input Current
VIN = 4.0 V
A
IIL
VIN = 1.0 V
A
IIH
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Analog Integrated Circuit Device Data
Freescale Semiconductor
5
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 7.0 V  VSUP  18 V, - 40C  TA  125 C, GND = 0 V, unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
—
—
1.4
Unit
LIN PIN (VOLTAGE EXPRESSED VERSUS VSUP VOLTAGE)
Low Level Bus Voltage (Dominant State)
VDOM
External Bus Pull-up 500 
High Level Bus Voltage (Recessive State)
V
VREC
TXD HIGH, IOUT = 1.0 A
V
VSUP - 1.0
—
—
Internal Pull-up Resistor to VSUP (Normal mode)
RPU
20
30
47
k
Internal Pull-up Current Source (Sleep mode)
IPU
—
20
—
A
IOV-CUR
50
75
150
mA
0
3.0
20
A
- 1.0
—
1.0
mA
—
1.0
10
A
0.0 VSUP
—
0.4 VSUP
0.6 VSUP
—
VSUP
0.475 VSUP
0.5 VSUP
0.525 VSUP
—
—
0.175 VSUP
VLINWU
—
0.5 VSUP
—
V
INHON
—
35
70

0
—
5.0
HIGH-to-LOW Transition
0.3 VSUP
0.43 VSUP
0.55 VSUP
LOW-to-HIGH Transition
0.4 VSUP
0.55 VSUP
0.65 VSUP
0.1 VSUP
0.16 VSUP
0.2 VSUP
—
1.0
5.0
Overcurrent Shutdown Threshold
Leakage Current to GND
ILEAK
Recessive State, 8.0 V  VSUP  18 V, 8.0 V  VLIN  18 V
GND Disconnected, VGND = VSUP, VLIN at - 18 V
VSUP Disconnected, VLIN at +18 V
LIN Receiver, Low Level Input Voltage
VLINL
TXD HIGH, RXD LOW
LIN Receiver, High Level Input Voltage
VLINH
TXD HIGH, RXD HIGH
LIN Receiver Threshold Center
V
VLINHYST
VLINH - VLINL
LIN Wake-up Threshold Voltage
V
VLINTH
(VLINH - VLINL) / 2
LIN Receiver Input Voltage Hysteresis
V
V
INH OUTPUT PIN
Driver ON Resistance (Normal mode)
Leakage Current (Sleep mode)
A
ILEAK
0.0 V < VINH < VSUP
WAKE INPUT PIN
Typical Wake-up Threshold Voltage (EN = 0 V, 7.0 V  VSUP  18 V) (5)
Wake-up Threshold Voltage Hysteresis
WAKE Input Current
VWAKE < 27 V
VWUTH
VWUHYST
V
V
A
IWU
Notes
4. This parameter is guaranteed by design; however, it is not production tested.
5. When VSUP > 18 V, the wake-up voltage thresholds remain identical to the wake-up thresholds at 18 V.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 7.0 V  VSUP  18 V, - 40C  TA  125C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Measurement Threshold (50% TXD to 58.1% VSUP)
t DOM (MIN)
—
—
50
Measurement Threshold (50% TXD to 28.4% VSUP)
t DOM (MAX)
—
—
50
Measurement Threshold (50% TXD to 42.2% VSUP)
t REC (MIN)
—
—
50
Measurement Threshold (50% TXD to 74.4% VSUP)
t REC (MAX)
—
—
50
t DOM (MIN) to t REC (MAX)
dt1
- 10.44
—
8.12
t DOM (MAX) to t REC (MIN)
dt2
- 10.44
—
8.12
Measurement Threshold (50% TXD to 61.6% VSUP)
t DOM (MIN)
—
—
100
Measurement Threshold (50% TXD to 25.1% VSUP)
t DOM (MAX)
—
—
100
Measurement Threshold (50% TXD to 38.9% VSUP)
t REC (MIN)
—
—
100
Measurement Threshold (50% TXD to 77.8% VSUP)
t REC (MAX)
—
—
100
t DOM (MIN) to t REC (MAX)
dt1S
- 21.88
—
17.44
t DOM (MAX) to t REC (MIN)
dt 2S
- 21.88
—
17.44
Unit
LIN OUTPUT TIMING CHARACTERISTICS FOR NORMAL MODE
Dominant Propagation Delay Time TXD to LIN (6)
s
Recessive Propagation Delay Time TXD to LIN (6)
s
Propagation Delay Time Symmetry
s
LIN OUTPUT TIMING CHARACTERISTICS FOR SLOW MODE
Dominant Propagation Delay Time TXD to LIN (6)
s
Recessive Propagation Delay Time TXD to LIN (6)
s
Propagation Delay Time Symmetry
s
LIN OUTPUT DRIVER FAST MODE
LIN Fast Slew Rate (Programming Mode)
dv/dt fast
Fast Slew Rate
V/s
—
15
—
—
10
—
—
3.5
6.0
LIN PIN
Over-current Shutdown Delay Time (7)
t OV-DELAY
s
LIN RECEIVER CHARACTERISTICS
Receiver Dominant Propagation Delay Time (8)
Receiver Recessive Propagation Delay Time (8)
s
t RH
LIN HIGH to RXD HIGH
Receiver Propagation Delay Time Symmetry
s
t RL
LIN LOW to RXD LOW
—
3.5
6.0
- 2.0
—
2.0
s
t R-SYM
t RL - t RH
Notes
6. 7.0 V  VSUP  18 V. Bus load R0 and C0: 1.0 nF / 1.0 k, 6.8 nF / 660 , 10 nF / 500 .
7.
8.
This parameter is guaranteed by design; however, it is not production tested.
Measured between LIN signal threshold VLINL or VLINH and 50% of RXD signal.
33661
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 7.0 V  VSUP  18 V, - 40C  TA  125C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
t LWUE
—
5.0
15
s
t WF
10
—
70
s
t WUF
40
70
120
s
50
—
—
SLEEP MODE AND WAKE-UP TIMINGS
EN Pin Wake-up Time (9)
WAKE Pin Filter Time
(10)
LIN Pin Wake-up Filter Time (LIN Bus Wake-Up)
Sleep Mode Delay Time
(11)
(12)
Delay for INH Turning off When Device Enters in Sleep Mode(16), (17)
Delay Time Between First TXD after Device Mode Selection (13), (14)
s
tSD_INH
EN HIGH-to-LOW and INH HIGH-to-LOW
Delay Time Between EN and TXD for Mode Selection (13), (14)
s
t SD
EN HIGH-to-LOW
—
—
50
t D_MS
5.0
—
—
s
t D_COM
50
—
—
s
—
—
35
—
—
5.0
FAST BAUD RATE TIMING
Delay Entering Fast Baud Rate Using Toggle Function (15)
Delay on EN Pin Resetting Fast Baud Rate to Previous Baud Rate (15)
EN LOW to EN HIGH
Notes
9.
10.
11.
12.
13.
14.
15.
16.
17.
s
t1
EN LOW to EN HIGH
s
t2
See Figures 7 and 8, 10.
See Figures 9 and 10, 10.
See Figures 11 and 12, 11.
See Figure 14a, 11.
See Figures 7 through 12, pp. 10–11.
This parameter is guaranteed by design; however, it is not production tested.
See Figure 13, 11.
No capacitor is connected to the INH pin. Measurement is done between the EN HIGH-to-LOW transition at 80% of INH voltage.
See Figure 14b, 11.
33661
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
TXD
Recessive State
VREC
t REC(MAX)
LIN
74.4% VSUP
58.1% VSUP
t DOM(MIN)
40% VSUP
60% VSUP
42.2% VSUP
28.4% VSUP
VDOM
t DOM(MAX)
Dominant State
t REC(MIN)
RXD
tRH
tRL
Figure 4. Normal Mode Bus Timing Characteristics
TXD
Recessive State
t REC(MAX)
VREC
LIN
77.8% VSUP
61.6% VSUP
t DOM(MIN)
40% VSUP
t DOM(MAX)
25.1% VSUP
VDOM
60% VSUP
38.9% VSUP
Dominant State
t REC(MIN)
RXD
t RL
t RH
Figure 5. Slow Mode Bus Timing Characteristics
33661
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
ELECTRICAL CHARACTERISTICS
FUNCTIONAL DIAGRAMS
VSUP
VSUP
TXD
R0
LIN
RXD
GND
C0
Note R0 and C0: 1.0 k/1.0 nF, 660 /6.8 nF, and 500 /10 nF.
Figure 6. Test Circuit for Timing Measurements
FUNCTIONAL DIAGRAMS
EN
WAKE
t WF
INH
INH
t LWUE
EN
TXD
t D_MS
TXD
t D_COM
LIN
RXD
t D_MS
t D_COM
LIN
RXD
(High Z)
Figure 7. EN Pin Wake-up and
Normal Baud Rate Selection (1.0 kbps to 20 kbps)
(High Z)
Figure 9. WAKE Pin Wake-up and
Normal Baud Rate Selection (1.0 kbps to 20 kbps)
WAKE
EN
t WF
INH
INH
t LWUE
EN
TXD
TXD
t D_MS
t D_COM
t D_MS
t D_COM
LIN
LIN
RXD (High Z)
RXD (High Z)
Figure 8. EN Pin Wake-up and
Slow Baud Rate Selection (1.0 kbps to 10 kbps)
Figure 10. WAKE Pin Wake-up and
Slow Baud Rate Selection (1.0 kbps to 10 kbps)
33661
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
FUNCTIONAL DIAGRAMS
Wake-up Frame
LIN
LIN
0.4 VSUP
Wake-Up Frame
0.4 VSUP
t WUF
tWUF
INH
INH
EN
EN
TXD
TXD
RXD
t D_MS
t D_COM
t D_MS t D_COM
(High Z)
(High Z)
RXD
Figure 11. LIN Bus Wake-up and
Normal Baud Rate Selection (1.0 kbps to 20 kbps)
Figure 12. LIN Bus Wake-up and
Slow Baud Rate Selection (1.0 kbps to 10 kbps)
EN = HIGH and TXD = HIGH
EN
EN
TXD
t 2 (5.0 s)
EN = LOW and TXD = HIGH
Toggle
t 1 (35 s)
Reset to Previous Baud Rate
Figure 13. Fast Baud Rate Selection (Toggle Function)
EN
TXD
Device in Communication Mode
Preparation to Sleep Mode
Sleep Mode
t SD
Figure 14a
EN
Preparation to Sleep Mode
INH
Normal or Slow Mode
t SD_INH
Sleep Mode
Figure 14b
Figure 14. Sleep Mode Enter
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Analog Integrated Circuit Device Data
Freescale Semiconductor
11
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33661 is a Physical Layer component dedicated to
automotive LIN sub-bus applications.
The 33661 features include slew rate selection for
optimized operation at 10 kbps and 20 kbps, fast baud rate
for test and programming modes, excellent radiated emission
performance, and safe behavior in case of LIN bus short-toground or LIN bus leakage during low power mode.
Digital inputs are 5.0 V and 3.3 V compatible without any
external component required.
The INH output may be used to control an external voltage
regulator or to drive a LIN bus pull-up resistor.
FUNCTIONAL PIN DESCRIPTION
POWER SUPPLY PIN (VSUP)
DATA INPUT PIN (TXD)
The VSUP supply pin is the power supply pin for the
33661. The pin is connected to a battery through a serial
diode for reverse battery protection. The DC operating
voltage is from 7.0 V to 27 V. This pin sustains standard
automotive voltage conditions such as 27 V DC during jumpstart conditions and 40 V during load dump. Supply current in
the Sleep mode is typically 8.0 A.
The TXD input pin is the MCU interface to control the state
of the LIN output. When TXD is LOW, LIN output is LOW;
when TXD is HIGH, the LIN output transistor is turned OFF.
The threshold is 3.3 V and 5.0 V compatible. The baud rate
selection (normal or Slow mode) is done at device wake-up
by the state of the TXD pin prior to a HIGH level at the EN pin
(see Figures 7 through 12).
GROUND PIN (GND)
DATA OUTPUT PIN (RXD)
In case of a ground disconnection at the module level, the
33661 does not have significant current consumption on the
LIN bus pin when in the recessive state. (Less than 100 µA is
sourced from LIN bus pin, which creates 100 mV drop
voltage from the 1.0 k LIN bus pull-up resistor.)
The RXD output pin is the MCU interface, which reports
the state of the LIN bus voltage. LIN HIGH (recessive) is
reported by a high-voltage on RXD; LIN LOW (dominant) is
reported by a low-voltage on RXD. The RXD output structure
is a CMOS-type push-pull output stage.
The low level is fixed. The high level is dependant on the
EN voltage. If EN is set at 3.3 V, RXD VOH is 3.3 V. If EN is
set at 5.0 V, RXD VOH is 5.0 V.
In the Sleep mode, RXD is high impedance. When a wakeup event is recognized from WAKE pin or from the LIN bus
pin, RXD is pulled LOW to report the wake-up event. An
external pull-up resistor may be needed.
LIN BUS PIN (LIN)
This I/O pin represents the single-wire bus transmitter and
receiver.
Transmitter Characteristics
The LIN driver is a low-side MOSFET with internal
overcurrent thermal shutdown. An internal pullup resistor with
a serial diode structure is integrated so no external pullup
components are required for the application in a slave node.
An additional pullup resistor of 1.0 k must be added when
the device is used in the master node.
Voltage can go from - 18 V to 40 V without current other
than the pull-up resistance. The LIN pin exhibits no reverse
current from the LIN bus line to VSUP, even in the event of
GND shift or VPWR disconnection.
The transmitter has two slew rate selections: 20 kbps
(normal slew rate) and 10 kbps (slow slew rate). The slow
slew rate can be used to improve radiated emissions.
Receiver Characteristics
The receiver thresholds are ratiometric with the device
supply pin.
ENABLE INPUT PIN (EN)
The EN input pin controls the operation mode of the
interface. If EN = 1, the interface is in Normal mode, with
transmission path from TXD to LIN and from LIN to RXD both
active. The threshold is 3.3 V and 5.0 V compatible. The high
level at EN defines the VOH at RXD. The Sleep mode is
entered by setting EN LOW while TXD is HIGH. Sleep mode
is active after the t SD filter time (see Figure 14).
INHIBIT OUTPUT PIN (INH)
The INH output pin may have two main functions. It may
be used to control an external switchable voltage regulator
having an inhibit input. The high drive capability also allows it
to drive the bus external resistor in the master node
application. This is illustrated in Figures 18 and 19.
In Sleep mode, INH is turned OFF. If a voltage regulator
inhibit input is connected to INH, the regulator will be
disabled. If the master node pull-up resistor is connected to
INH, the pull-up resistor will be disabled from the LIN bus.
33661
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Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
WAKE INPUT PIN (WAKE)
The WAKE pin is a high-voltage input used to wake-up the
device from the Sleep mode. WAKE is usually connected to
an external switch in the application. The typical wake
thresholds are VSUP / 2.
The WAKE pin has a special design structure and allows
wake-up from both High-to-Low or Low-to-High transitions.
When entering into Sleep mode, the LIN monitors the state of
the WAKE pin and stores it as a reference state. The opposite
state of this reference state will be the wake-up event used
by the device to enter again into Normal mode.
An internal filter is implemented (40 s typical filtering time
delay). WAKE pin input structure exhibits a high-impedance,
with extremely low input current when voltage at this pin is
below 14 V. When voltage at the WAKE pin exceeds 14 V,
input current starts to sink into the device. A serial resistor
should be inserted in order to limit the input current mainly
during transient pulses. Recommended resistor value is
33 k.
Important The WAKE pin should not be left open. If the
wake-up function is not used, WAKE should be connected to
ground to avoid false wake-up.
33661
Analog Integrated Circuit Device Data
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13
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
As described in the following, and as depicted in Figure 15
and Table 5, the 33661 has two operational modes, Normal
and Sleep. Normal mode may be adjusted to improve
radiated emissions by changing the slew rate of the LIN bus
output to Fast or Slow mode. In addition, there are two
transitional modes: Awake mode, which allows the device to
go in Normal or Slow mode, and Wait Slow mode, which is a
temporary state before the device enters the Slow mode.
NORMAL MODE
In the Normal mode, the 33661 has slew rate and timing
compatible with the LIN protocol specification, and operates
from 1.0 kbps to 20 kbps. This mode is selected after Sleep
mode by setting the TXD pin High prior to setting EN from
Low to High. Once Normal mode is selected, it is impossible
to select the Slow mode unless the 33661 is set into Sleep
mode.
Slow Mode
In the Slow mode, the slew rate is around half the normal
slew rate, and bus speed operation ranges from 1.0 kbps to
10 kbps. The radiated emission is significantly reduced
compared to the already excellent emission level of the
Normal mode. Slow mode is entered after Sleep mode by
setting the TXD pin Low prior to setting EN from Low to High.
Once the Slow mode is selected, it is impossible to select the
Normal mode unless the device is set to Sleep mode.
SLEEP MODE
In the Sleep mode, the transmission path is disabled and
the 33661 is in Low Power mode. Supply current from VSUP
is very low. Wake-up can occur from LIN bus activity from
node internal wake-up through the EN pin and from the
WAKE input pin.
In the Sleep mode, the 33661 has an internal 20 A pullup source to VSUP. This avoids the high current path from
the battery to ground in the event the bus is shorted to
ground. (Refer to succeeding paragraphs describing wakeup behavior.)
DEVICE POWER-UP (AWAKE TRANSITIONAL
MODE)
At power-up (VSUP rises from zero), the 33661
automatically switches to the Awake transitional mode. It
switches the INH pin to High state and RXD to Low state. The
MCU of the application will then confirm Normal or Slow
mode by setting the TXD and EN pins appropriately.
DEVICE WAKE-UP EVENTS
The 33661 can be awakened from Sleep mode by three
wake-up events:
• Remote wake-up via LIN bus activity
• Internal node wake-up via the EN pin
• Toggling the WAKE pin
Fast Mode
Remote Wake from LIN Bus (Awake Transitional Mode)
In the Fast mode, the slew rate is around 10 times faster
than the Normal mode. This allows very fast data
transmission (> 100 kbps) — for instance, for electronic
control unit (ECU) tests and microcontroller program
download. The bus pull-up resistor might be reduced to
ensure a correct RC time constant in line with the high baud
rate used.
Fast mode can be selected from either Normal or Slow
mode. Fast mode is entered via a special sequence (called
toggle function) as follows: TXD and EN pins set Low, then
TXD pulled High, and at the EN pin Low-to-High transition,
the device enters into the Fast Baud rate. The duration of this
sequence must be less than 35 µs. The toggle function is
described in Figure 13. Once in the Fast mode, two different
procedures will bring the device back to the previously
selected mode (Normal or Slow):
• The toggle function already described.
• A glitch on EN where t 2 < 5.0 µs also resets the device to
the previously selected mode (Normal or Slow)
(Figure 13).
The LIN bus wake-up is recognized by a recessive-todominant transition, followed by a dominant level with a
duration greater than 70 s, followed by a dominant-torecessive transition. This is illustrated in Figures 11 and 12.
Once the wake-up is detected, the 33661 enters the Awake
Transitional mode, with INH High and RXD pulled Low.
Wake-up from Internal Node Activity (Normal or Wait
Slow Mode)
The 33661 can wake-up by internal node activity through
a Low-to-High transition of the EN pin. When EN is switched
from Low-to-High, the device is awakened and enters either
the Normal or the Wait Slow transitional mode depending on
the level of TXD input. The MCU must set the TXD pin LOW
or HIGH prior to waking up the device through the EN pin.
Wake-up from WAKE Pin (Awake Transitional Mode)
If the WAKE input pin is toggled, the 33661 enters the
Awake transitional mode, with INH High and RXD pulled Low.
33661
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Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Power-up
TXD High and EN Low > t1 (35 s)
Fast
(10 x)
TXD High and EN Low to
High
Toggle Function
LIN Bus or WAKE Pin
Wake-up
Sleep
TXD High and EN Low to High
Awake
TXD Low and EN
Low to High
TXD High
Wait Slow
TXD Low and EN Low to High
Normal
1.0 to 20
kbps
EN Low for t 2 < 5.0 s,
then High
EN Low for t 2 < 5.0 s,
then High
EN Low for t 2 < 5.0 s,
then High
Slow
1.0 to 10
kbps
Toggle Function
TXD High and EN Low > t1 (35 s)
EN Low for t 2 < 5.0 s, then High
Fast
(10 x)
Note Refer to Table 5 for explanation.
Figure 15. Operational and Transitional Modes State Diagram
Table 5. Explanation of Operational and Transitional Modes State Diagram
Operational/
Transitional
LIN
INH
EN
TXD
RXD
Sleep Mode
Recessive state, driver off. 20 A
pull-up current source.
Low
Low
X
High-impedance. High if external
pull-up to VDD.
Awake
Recessive state, driver off. 30 k
pull-up active.
High
Low
X
Low. If external pull-up, High-toLow transition reports wake-up.
Driver active. 30 k pull-up
active. Slew rate normal
(20 kbps).
High
High
High to enter Normal mode. Once
in Normal mode: Low to drive LIN
bus in dominant, High to drive
LIN bus in recessive.
Wait Slow
Recessive state. Driver off. 30 k
pull-up active.
High
High
Low
Slow
Driver active. 30 k pull-up
active. Slew rate slow (10 kbps).
High
High
Low to enter Slow mode. Once in
Slow mode: Low to drive LIN bus
in dominant, High to drive LIN
bus in recessive.
Report LIN bus level:
• Low LIN bus dominant
• High LIN bus recessive
Fast
Driver active. 30 k pull-up
active. Slew rate fast
(>100 kbps).
High
High
Low to drive LIN bus in dominant,
High to drive LIN bus in
recessive.
Report LIN bus level:
• Low LIN bus dominant
• High LIN bus recessive
Normal Mode
Report LIN bus level:
• Low LIN bus dominant
• High LIN bus recessive
High
X = Don’t care.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
15
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
ELECTROMAGNETIC COMPATIBILITY
RADIATED EMISSION IN NORMAL AND SLOW
MODES
The 33661 has been tested for radiated emission
performances. Figures 16 and 17 show the results in the
frequency range 100 kHz to 2.0 MHz. Test conditions are in
accordance with CISPR25 recommendations, bus length of
1.5 meters, device loaded with 10 nF and 500  bus
impedance.
Figure 16 displays the results when the device is set in the
Normal mode, optimized for baud rate up to 20 kbps.
Figure 17 displays the results when the device is set in the
Slow mode, optimized for baud rate up to 10 kbps. The level
of emissions is significantly reduced compared to the already
excellent level of the Normal mode.
Figure 16. Radiated Emission in Normal Mode
Figure 17. Radiated Emission in Slow Mode
33661
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Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
The 33661 can be configured in several applications.
Figures 18 and 19 show master and slave node applications.
An additional pull-up resistor of 1.0 k in series with a diode
must be added when the device is used in the master node.
VPWR
33661
> 33 k
External
Switch
WAKE
VSUP
20 A
INH
Control
Master Node
Pull-up
EN
I/O
VDD
INH
Control
MCU
*
VDD
Regulator
12 V
1.0 k
RXD
RXD
30 k
VDD
LIN
Receiver
LIN Bus
5.0 V
TXD
TXD
GND
Slope
Control
* Optional
Figure 18. Master Node Typical Application
VPWR
33661
> 33 k
External
Switch
WAKE
VSUP
20 A
INH
Control
EN
I/O
INH
VDD
Control
MCU
Regulator
*
VDD
12 V
RXD
RXD
VDD
30 k
Receiver
LIN
LIN Bus
5.0 V
INH
TXD
TXD
Slope
Control
GND
* Optional
Figure 19. Slave Node Typical Application
33661
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
PACKAGING
PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
Important For the most current revision of the package, visit www.freescale.com and do a keyword search on the
98ASB42564B drawing number below.Dimensions shown are provided for reference ONLY.
EF SUFFIX (PB-FREE)
8-PIN SOIC NARROW BODY
98ASB42564B
ISSUE V
33661
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Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGE DIMENSIONS
EF SUFFIX (PB-FREE)
8-PIN SOIC NARROW BODY
98ASB42564B
ISSUE V
33661
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
REFERENCE DOCUMENTS
PACKAGE DIMENSIONS
REFERENCE DOCUMENTS
Table 6. Reference Documents
Title
Local Interconnect Network (LIN) Physical Interface: Difference Between MC33399 and MC33661
Literature Number
EB215
33661
20
Analog Integrated Circuit Device Data
Freescale Semiconductor
REVISION HISTORY
REVISION HISTORY
REVISION
DATE
DESCRIPTION OF CHANGES
5.0
10/2006
•
•
•
Implemented Revision History page
Updated the Freescale format and style
Added MCZ33661EF/R2 to the part number Ordering Information
6.0
11/2006
•
Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from
MAXIMUM RATINGS 4. Added note with instructions from www.freescale.com.
7.0
2/2012
•
•
Updated Freescale format and package drawing. No content was altered.
Updated ordering information. Removed MC33661D/R2 and MCZ33662EF/R2, and replaced with
MC33661PEF/R2.
4/2012
•
•
Corrected the definition of LIN
Updated Freescale form and style
4/2013
•
•
Change TSTG to -55 to 150
Revised back page. Updated document properties. Added SMARTMOS sentence to first
paragraph.
8.0
33661
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
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© 2013 Freescale Semiconductor, Inc.
Document Number: MC33661
Rev. 8.0
4/2013
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