Data Sheet

Freescale Semiconductor
Technical Data
Document Number: MC33790
Rev 13.0, 2/2014
Two Channel Distributed
System Interface (DSI) Physical
Interface Device
33790
The 33790 is a dual channel physical layer interface IC for the
Distributed System Interface (DSI) bus. It is designed to meet
automotive requirements. It can also be used in non automotive
applications. It supports bidirectional communication between slave
and master ICs. Some slave devices derive a regulated 5.0 V from
the bus, which can be used to power sensors, thereby eliminating the
need for additional circuitry and wiring. This device is powered by
SMARTMOS technology.
DISTRIBUTED SYSTEM INTERFACE (DSI)
Features
•
•
•
•
•
•
•
•
Two independent DSI compatible buses
Wave-shaped bus output voltage
Independent thermal shutdown and current limit
Return signalling current detection
Internal logic input pull-ups and pull-downs
On-board charge pump
2.0 kV ESD capability
Communications rate up to 150 kbps
EG SUFFIX (PB-FREE)
98ASB42567B
16-PIN SOICW
Applications
• Simple bus for remote control and sensing
• Automotive, aircraft, marine, industrial controls,
and safety systems
• Heating and air-conditioning
33790
DSI0F
MCU
+5.0 V
VDD
DSI0S
GND
DSI0R
DSI0O
DSI1F
VSUP
DSI1S
DSI1O
DSI1R
GND
+25 V
CPCAP
33793
DSI
SLAVE
DEVICE
BUS_IN
BUS_OUT
BUS_IN
BUS_OUT
33793
33793
Figure 1. 33790 Simplified Application Diagram
© Freescale Semiconductor, Inc., 2010 - 2014. All rights reserved.
ORDERABLE PARTS
ORDERABLE PARTS
Table 1. Orderable Part Variations
Part Number
Temperature (TA)
Package
MC33790HEG / R2
-40 to 85 C
16 SOICW
33790
2
Analog Integrated Circuit Device Data
Freescale Semiconductor
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
+
VSUP (IDLE Level)
CPCAP
VDD (+5.0 V)
Internal
Bias
Charge
Pump
Bus Current
Sense
WaveShaper
DSI0F
DSI0S
Bus Supply
Voltage
DSI0O
DSI Bus
Transmitter
Driver
DSI0R
GND
+
DSI1F
DSI1S
Bus Current
Sense
WaveShaper
DSI1O
DSI Bus
Transmitter
Driver
DSI1R
Figure 2. 33790 Simplified Internal Block Diagram
33790
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
PIN CONNECTIONS
PIN CONNECTIONS
DSI0F
1
16
VDD
DSI0S
2
15
GND
DSI0R
3
14
DSI0O
DSI1F
4
13
VSUP
DSI1S
5
12
DSI10
DSI1R
6
11
GND
NC
7
10
NC
CPCAP
8
9
NC
Figure 3. 33790 Pin Connections
Table 2. 33790 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 9.
Pin Number
Pin Name
Definition
1
DSI0F
This logic input controls the frame output for DSI channel 0 in accordance with Table 6, page 9.
2
DSI0S
This logic input controls the signalling output for DSI channel 0 in accordance with Table 6, page 9.
3
DSI0R
This logic output provides the return data for DSI channel 0 in accordance with Table 6, page 9.
4
DSI1F
This logic input controls the frame output for DSI channel 1 in accordance with Table 6, page 9.
5
DSI1S
This logic input controls the signalling output for DSI channel 1 in accordance with Table 6, page 9.
6
DSI1R
This logic output provides the return data for DSI channel 1 in accordance with Table 6, page 9.
7
NC
8
CPCAP
9
NC
Unused.
10
NC
Unused.
11
GND
12
DSI1O
DSI bus 1 input / output.
13
VSUP
Idle level supply input. The voltage supplied to this pin sets the idle level on the DSI bus.
14
DSI0O
DSI bus 0 input / output.
15
GND
Circuit and bus ground return.
16
VDD
5.0 V logic supply input.
Unused.
Used to store and filter charge pump output.
Circuit and bus ground return.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent
damage to the device.
Ratings
Symbol
Value
VSUP
- 0.5 to 25
VSUP (t)
40
Unit
ELECTRICAL RATINGS
Supply Voltage
V
Continuous
Load Dump - t < 300 ms
Maximum Voltage on Input / Output Pins
VDD
DSIxS, DSIxF
- 0.3 to 5.5
(1)
V
- 0.3 to VDD + 0.3
DSIxO (1)
- 0.3 to VSUP + 0.3
TSTG
- 55 to 150
C
TA
-40 to 85
C
TJ
- 40 to 150
C
TPPRT
Note 3
°C
VDD
0 to 10
mA
DSIxR
- 2.5 to 5.0
VSUP
500
Thermal Resistance Junction to Ambient
RJA
45
C / W
Thermal Shutdown
TSD
155 to 190
C
Human Body Model
VESD1
2000
Machine Model
VESD2
200
Storage Temperature
Operating Ambient Temperature
Operating Junction Temperature
Peak Package Reflow Temperature During Reflow
Continuous Current per Pin
(2), (3)
V
ESD Voltage (All Pins) (4)
Notes
1. R = 0 
2. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
3. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL),
Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.
MC33xxxD enter 33xxx), and review parametrics.
4. ESD1 performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ), ESD2 performed in accordance with the
Machine Model (CZAP = 200 pF, RZAP = 0 ).
33790
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics
Characteristics noted under conditions 4.75 V  VDD  5.25 V, 8.0 V  VSUP  25.0 V, -40 C  TJ  150 C, unless otherwise
noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SUPPLY
ISUP Supply Current / Channel (Not Including IOUT)
mA
DSIx0 = Idle Voltage, -100 mA  IOUT  0 mA
ISUPI
–
1.35
3.25
DSIx0 = Output High Voltage, IOUT = 12 mA
ISUPH
–
5.0
9.00
IDD
–
0.5
1.0
IDD Supply Current / Channel
mA
BUS TRANSMITTER
VSUP to DSIxO ON Resistance (During Idle)
–
IOUT = -100 mA
Output High Voltage
–
10
DSIVOH
DSIx0 (-15 mA  IOUT  1.0 mA)
Output Low Voltage

RDS(ON)
V
4.175
4.5
4.825
1.325
1.5
1.675
DSIVOL
DSIx0 (-15 mA  IOUT  1.0 mA)
V
Output High Side Current Limit (5)
ICLH
- 100
–
-200
mA
Output Low Side Current Limit (5)
ICLL
110
–
220
mA
- 200
–
50
IRH
- 5.0
- 6.0
- 7.0
mA
VIN(TH)
1.10
–
2.20
V
0.8 VDD
–
VDD
Input Leakage
A
DSIIB
DSIxO When DSIxF Is High and DSIxS Is Low (0 V  DSIxO  Min
(VSUP = 16.5 V))
BUS RECEIVER
Return Current Threshold
MICROCONTROLLER INTERFACE
Logic Input Thresholds DSIxS, DSIxF
Output High Voltage
VOH
DSIxR Pin = -0.5 mA
Output Low Voltage
V
VOL
DSIxR Pin = 1.0 mA
V
0.0
–
0.2 VDD
Internal Pull-up for DSIxF
IIL
-100
–
-10
A
Internal Pull-down for DSIxS
IIH
10
–
100
A
Notes
5. After 10 s settling time (assured by design).
33790
6
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions 4.75 V  VDD  5.25 V, 8.0 V  VSUP  25.0 V, -40 C  TJ  150 C, unless otherwise
noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Microcontroller Signal Cycle Time
t CYC
6.6
–
1000
s
Microcontroller Signal Low Time
t CYCL
2.0
–
667
s
Microcontroller Signal High Time
t CYCH
2.0
–
667
s
Microcontroller Signal Duty Cycle for Logic Zero
DCLO
30
33
36
%
Microcontroller Signal Duty Cycle for Logic One
DCHI
60.0
66.7
72.0
%
t SLEW
–
–
500
ns
Frame Start to Signal Delay Time
t DLY1
t cyc - 0.1
t cyc
t cyc + 0.1
s
Signal End to Frame End Delay Time
t DLY2
1.0
–
–
s
Rise Time (6)
t RISE
0
–
100
ns
Fall Time (6)
t FALL
0
–
100
ns
MICROCONTROLLER INTERFACE
Microcontroller Signal Slew Time
(6)
BUS TRANSMITTER
Idle to Frame and Frame to Idle Slew Rate
t SLEW (FRAME)
C  5.0 nF
V/s
3.0
6.0
10.0
3.0
4.5
8.0
DSIxF, VIN(TH) to DSIxO = 5.3 V
t DVLD1
2.44
–
6.56
DSIxS, VIN(TH) to DSIxO = 2.6 V
t DVLD2
0.25
–
1.3
DSIxS, VIN(TH) to DSIxO = 3.4 V
tDVLD3
0.25
–
1.3
DSIxF, VIN(TH) to DSIxO = 7.0 V
tDVLD4
0.25
–
1.3
tDRH: I = IRH to DSIxR = 2.5 V
t DRH
–
400
750
tDRL: I = IRH to DSIxR = 2.5 V
t DRL
–
400
750
Signal High to Low and Signal Low to High Slew Rate
t SLEW (SIGNAL)
C  5.0 nF
V/s
Data Valid (VSUPx = 25 V, CL  5.0 nF)
s
BUS RECEIVER
Receiver Delay Time
ns
Notes
6. Slew times and rise and fall times between 10% and 90% of output high and low levels.
33790
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
ELECTRICAL CHARACTERISTICS
TIMING CHARACTERISTICS
TIMING CHARACTERISTICS
tCYC
tCYC
tDLY2
tCYCH
5.0 V
DSIxS
VIN(TH)
0V
tRISE
tCYCL
tRISE
tDLY1
tFALL
5.0 V
DSIxF
VIN(TH)
0V
tDVLD4
tDVLD1
25 V
7.0 V
tDVLD3
DSIxO 5.0 V
tSLEW(SIGNAL)
tDVLD2
DSIVOH 4.5 V
3.0 V
tSLEW(FRAME)
Note (7)
1.5 V
tTAT
IOUT
IRH
(Note (8))
0 mA
tDRH
tDRL
5.0 V
DSIxR
(Note (9))
0V
Figure 4. Timing Characteristics
Notes
7. Typical BUSIN / BUSOUT logic thresholds (VTHL) from MC33793 datasheet.
8.
9.
tTAT (Turnaround Time) is dependent upon wire length, bus loads, and slave response characteristics.
DSIxR stable on falling edge of DSIxS or rising edge of DSIxF.
33790
8
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33790 is designed to provide the interface between logic
and the DSI bus. It accepts signals with a typical 0 V to 5.0 V
logic level to control the state of the bus output (Idle Level,
Logic High Level, Logic Low Level, and High Impedance). It
detects the current drawn from the bus output during
signaling and outputs a 0 V to 5.0 V logic level corresponding
to the bus current being above (Logic [1] out) the bus return
logic [1] current or below (Logic [0] out). The 33790 contains
current limiting of the bus outputs as required by the DSI Bus
specification and thermal shutdown to protect itself from
damage. Two independent DSI bus outputs are provided by
the IC.
FUNCTIONAL TERMINAL DESCRIPTION
Bus Driver and Receiver
The Wave-Shaper converts the 0 to 5.0 V logic inputs from
DSIxF (frame) and DSIxS (signal) to a wave-shaped signal
on the DSIxO output, as shown in the timing diagrams in
Figure 2, page 3, and the truth table in Table 6. The Bus
Current Sense detects the current being drawn by the
device(s) on the bus during signalling (DSIxF = 0). If the
current is above a set level, DSIxR will be high; otherwise, it
is low. Due to the variations in the turnaround time (tTAT) from
slave devices and bus delays, DSIxR should be sampled on
the falling edge of DSIxS and on the rising edge of DSIxF (for
the last return bit).
Table 6. DSI Bus Truth Table
DSIxF
DSIxS
TxLIM
DSIxR
DSIxO
0
0
0
Not Defined
Low (1.5 V)
0
1
0
Not Defined
High (4.5 V)
0

0
Return Data
Unchanged

X
0
Return Data
Unchanged
1
0
0
0
High Impedance
1
1
0
0
Idle  VSUP - 0.5 V
X
X
1
1
High Impedance
The current for the idle state is from the supply connected to
VSUP and this supply should not be current limited below
250 mA per channel. During idle state, the voltage on the DSI
bus will be very close to the VSUP voltage.
Internal thermal shutdown circuitry and current limit
individually protect the DSIxO outputs from shorts to battery
and ground.
Typically, the thermal shutdown occurs between 160 °C and
170 °C. If the junction temperature rises above this
temperature, the internal TxLIM bit is asserted, and the output
drivers for DSIxO are disabled by the thermal shutdown
circuitry. The output drivers remain off until the junction
temperature decreases below approximately 155 °C, at
which time the thermal shutdown circuitry turns off and the
outputs are re-enabled. Each DSIxO output has a unique
thermal sense and shutdown circuit, so a short on one
channel does not affect the other channel.
Charge Pump
The charge pump uses on-board capacitors to step the input
voltage up to the voltage needed to drive the on-board
transmitter FETs. A filter / storage capacitor is connected to
CPCAP to hold the stepped-up voltage.
Input Pull-ups and Pull-downs
Internal current pull-ups are used on the DSIxF pins and
pulldowns on the DSIxS pins. If these pins are left
unconnected, their associated DSI bus will go to the unused
(high-impedance) state.
33790
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
The 33790 is intended for use in a DSI system. This device
supplies the interface between standard logic levels and the
voltage and current required for the DSI bus. Two
independent DSI busses are supported by this part. The
33790 does not form the timing for the DSI bus. This is done
by logic embedded in a microcontroller which interfaces to
the 33790 through the MCU’s 5 V I/O pins.
A capacitor attached to CPCAP serves as a charge reservoir
for the gate drive charge pump. This circuit creates a voltage
that is higher than the source of the N-channel output
transistor. This allows turning on of the transistor enough to
prevent any significant voltage drop across it. The rest of
charge pump electronics are completely self-contained on
the IC.
33790
10
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below.
EG SUFFIX (PB-FREE)
98ASB42567B
16-PIN SOICW
33790
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
REVISION HISTORY
REVISION HISTORY
Revision
Date
7.0
5/2006
8.0
11/2006
9.0
11/2006
10.0
12/2006
11.0
3/2008
12.0
12/2011
13.0
2/2014
Description of Changes
•
•
Implemented Revision History page
Converted to Freescale format
•
•
Updated data sheet format
Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from
Maximum Ratings on page 5. Added note with instructions to obtain this information from
www.freescale.com.
•
Minor correction changes to Figure 1 and ordering information
•
Restated note Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC
standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels
(MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter
the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. on
page 5
•
Removed watermark from page 1.
•
Removed part numbers MCZ33790EG/R2, MC33790DW/R2 and added part number
MC33790HEG/R2.
Deleted references to MC68HC55.
Updated Freescale form and style.
•
•
•
No technical changes. Revised back page. Updated document properties. Added SMARTMOS
sentence to last paragraph on page 1.
33790
12
Analog Integrated Circuit Device Data
Freescale Semiconductor
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© 2014 Freescale Semiconductor, Inc.
Document Number: MC33790
Rev 13.0
2/2014
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