Data Sheet

PCK953
20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL
clock driver
Rev. 05 — 9 October 2008
Product data sheet
1. General description
The PCK953 is a 3.3 V compatible, PLL-based clock driver device targeted for high
performance clock tree designs. With output frequencies of up to 125 MHz, and output
skews of 100 ps, the PCK953 is ideal for the most demanding clock tree designs. The
devices employ a fully differential PLL design to minimize cycle-to-cycle and phase jitter.
The PCK953 has a differential LVPECL reference input, along with an external feedback
input. These features make the PCK953 ideal for use as a zero delay, low skew fan-out
buffer. The device performance has been tuned and optimized for zero delay performance.
The MR/OE input pin will reset the internal counters and 3-state the output buffers when
driven HIGH.
The PCK953 is fully 3.3 V compatible and requires no external loop filter components. All
control inputs accept LVCMOS or LVTTL compatible levels, while the outputs provide
LVCMOS levels with the ability to drive terminated 50 Ω transmission lines. For series
terminated 50 Ω lines, each of the PCK953 outputs can drive two traces, giving the device
an effective fan-out of 1 : 18. The device is packaged in a 7 mm × 7 mm 32-lead LQFP
package to provide the optimum combination of board density and performance.
2. Features
n
n
n
n
n
n
n
Fully integrated PLL
Output frequency up to 125 MHz in PLL mode
Outputs disable in high-impedance
LQFP32 packaging
55 ps cycle-to-cycle jitter typical
9 mA quiescent current typical
60 ps static phase offset typical
PCK953
NXP Semiconductors
20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL clock driver
3. Ordering information
Table 1.
Ordering information
Type number
PCK953BD
Package
Name
Description
Version
LQFP32
plastic low profile quad flat package; 32 leads; body 7 × 7 × 1.4 mm
SOT358-1
PCK953BD/G
Also refer to Table 8 “Packing information”.
4. Functional diagram
QFB
PECL_CLK
PECL_CLK
PHASE
DETECTOR
FB_CLK
LPF
7
VCO
200 MHz
to 500 MHz
÷4
÷2
Q0 to Q6
Q7
VCO_SEL
BYPASS
MR/OE
PLL_EN
Fig 1.
002aae138
Functional diagram
5. Pinning information
25 GNDO
26 Q0
27 VCCO
28 QFB
1
24 Q1
2
23 VCCO
n.c.
3
n.c.
4
n.c.
5
n.c.
6
19 VCCO
GNDI
7
18 Q4
PECL_CLK
8
17 GNDO
22 Q2
21 GNDO
Q5 16
20 Q3
VCCO 15
Q6 14
GNDO 13
Q7 12
VCCO 11
9
MR/OE 10
PCK953BD
PCK953BD/G
002aae137
Pin configuration for LQFP32
PCK953_5
Product data sheet
29 GNDO
30 PLL_EN
VCCA
FB_CLK
PECL_CLK
Fig 2.
31 BYPASS
32 VCO_SEL
5.1 Pinning
© NXP B.V. 2008. All rights reserved.
Rev. 05 — 9 October 2008
2 of 15
PCK953
NXP Semiconductors
20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL clock driver
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
VCCA
1
Analog supply voltage. See Section 11 “Application information” for
design and layout considerations.
FB_CLK
2
Feedback clock input (CMOS) to comparator/phase detector.
n.c.
3, 4, 5, 6
Not connected.
GNDI
7
Ground pin associated with input circuitry.
PECL_CLK
8
LVPECL reference clock input, true.
PECL_CLK
9
LVPECL reference clock input, complementary.
MR/OE
10
Master reset/output enable input. See Table 3 “Function selection”.
VCCO
11, 15, 19, Supply voltage pins associated with output driver circuitry.
23, 27
Q7
12
Q6
14
Q5
16
Q4
18
Q3
20
Q2
22
Q1
24
Q0
26
GNDO
13, 17, 21, Ground pins associated with output driver circuitry.
25, 29
QFB
28
Buffered clock output intended to be fed to feedback pin FB_CLK.
PLL_EN
30
PLL enable input pin. See Table 3 “Function selection”.
Buffered clock outputs (CMOS).
BYPASS
31
Bypass input pin. See Table 3 “Function selection”.
VCO_SEL
32
VCO select input pin. See Table 3 “Function selection”.
6. Functional description
Refer to Figure 1 “Functional diagram”.
6.1 Function selection
Table 3.
Function selection
Pin
Value
Function
BYPASS
1
PLL enabled
0
PLL bypass
MR/OE
VCO_SEL
PLL_EN
1
outputs disabled
0
outputs enabled
1
divide-by-2
0
divide-by-1
1
select VCO
0
select PECL_CLK
PCK953_5
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 05 — 9 October 2008
3 of 15
PCK953
NXP Semiconductors
20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL clock driver
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VCC
Conditions
Min
Max
Unit
supply voltage
−0.3
+4.6
V
VI
input voltage
−0.3
VDD + 0.3
V
II
input current
-
±20
mA
Tstg
storage temperature
−40
+125
°C
8. Static characteristics
Table 5.
Static characteristics
Tamb = 0 °C to 70 °C; VCC = 3.3 V ± 5 %, unless specified otherwise.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIH
HIGH-level input voltage
LVCMOS inputs
2.0
-
3.6
V
VIL
LOW-level input voltage
LVCMOS inputs
-
-
0.8
V
Vi(p-p)
peak-to-peak input voltage
PECL_CLK
300
-
1000
mV
Vcm
common-mode voltage
PECL_CLK
[1]
VCC − 1.5
-
VCC − 0.6
mV
VOH
HIGH-level output voltage
IOH = −20 mA
[2]
2.4
-
-
V
IOL = 20 mA
[2]
-
-
0.5
V
-
-
±75
µA
VOL
LOW-level output voltage
II
input current
Ci
input capacitance
-
-
4
pF
CPD
power dissipation capacitance
per output
-
25
-
pF
ICC
maximum quiescent supply current
all VCC pins
-
9
20
mA
ICCPLL
maximum PLL supply current
VCCA pin only
-
9
20
mA
[1]
Vcm is the difference from the most positive side of the differential input signal. Normal operation is obtained when the HIGH input is
within the Vcm range and the input swing lies within the Vi(p-p) specification.
[2]
The PCK953 outputs can drive series or parallel terminated 50 Ω (or 50 Ω to 0.5VCC) transmission lines on the incident edge (see
Section 11 “Application information”).
PCK953_5
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 05 — 9 October 2008
4 of 15
PCK953
NXP Semiconductors
20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL clock driver
9. Dynamic characteristics
Table 6.
Dynamic characteristics
Tamb = 0 °C to 70 °C; VCC = 3.3 V ± 5 %; unless specified otherwise.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tr(o)
output rise time
0.8 V to 2.0 V
0.30
0.55
0.8
ns
tf(o)
output fall time
0.8 V to 2.0 V
δo
output duty cycle
tsk(o)
output skew time
fVCO
PLL VCO lock range
fo(max)
maximum output frequency
0.30
0.55
0.8
ns
45
50
55
%
-
-
100
ps
120
-
500
MHz
PLL mode; VCO_SEL = 1
20
-
100
MHz
PLL mode; VCO_SEL = 0
35
-
125
MHz
Bypass mode
-
-
225
MHz
output-to-output; relative to QFB
tpd(lock)
input to EXT_FB delay (with
PLL locked)
fref = 50 MHz
−75
-
+125
ps
tpd(bypass)
input to Qn delay
PLL bypassed
3
5.2
7
ns
tPLZ-HZ
output disable time
-
-
7
ns
tPZL
output enable time
-
-
6
ns
tjit(cc)
cycle-to-cycle jitter time
tlock
maximum PLL lock time
peak-to-peak
-
55
100
ps
-
0.01
10
ms
Unit
10. PLL input reference characteristics
Table 7.
PLL input reference characteristics
Tamb = 0 °C to 70 °C.
Maximum and minimum input reference is limited by the VCO lock range and the feedback divider.
Symbol
Parameter
fref
frefDC
Conditions
Min
Typ
Max
reference input frequency
20
-
125
MHz
reference input duty cycle
25
-
75
%
PCK953_5
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 05 — 9 October 2008
5 of 15
PCK953
NXP Semiconductors
20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL clock driver
11. Application information
11.1 Power supply filtering
The PCK953 is a mixed analog/digital product and as such it exhibits some sensitivities
that would not necessarily be seen on a fully digital product. Analog circuitry is naturally
susceptible to random noise, especially if this noise is seen on the power supply pins. The
PCK953 provides separate power supplies for the output buffers (VCCO) and the
phase-locked loop (VCCA) of the device. The purpose of this design technique is to try to
isolate the high switching noise digital outputs from the relatively sensitive internal analog
phase-locked loop. In a controlled environment such as an evaluation board, this level of
isolation is sufficient. However, in a digital system environment where it is more difficult to
minimize noise on the power supplies, a second level of isolation may be required. The
simplest form of isolation is a power supply filter on the VCCA pin for the PCK953.
Figure 3 illustrates a typical power supply filter scheme. The PCK953 is most susceptible
to noise with spectral content in the 1 kHz to 1 MHz range. Therefore, the filter should be
designed to target this range. The key parameter that needs to be met in the final filter
design is the DC voltage drop that will be seen between the VCC supply and the VCCA pin
of the PCK953. The current sourced though the VCCA pin is typically 15 mA (20 mA
maximum), assuming that a minimum of 3.0 V must be maintained on the VCCA pin,
very little DC voltage drop can be tolerated when a 3.3 V VCC supply is used. The resistor
shown in Figure 3 must have a resistance of 10 Ω to 15 Ω to meet the voltage drop
criteria. The RC filter pictured will provide a broadband filter with approximately 100 : 1
attenuation for noise whose spectral content is above 20 kHz. As the noise frequency
crosses the series resonant point of an individual capacitor, its overall impedance begins
to look inductive, and thus increases with increasing frequency. The parallel capacitor
combination shown ensures that a low impedance path to ground exists for frequencies
well above the bandwidth of the PLL. It is recommended that the user start with an 8 Ω to
10 Ω resistor to avoid potential VCC drop problems, and only move to the higher value
resistors when a higher level of attenuation is shown to be needed.
Although the PCK953 has several design features to minimize the susceptibility to power
supply noise (isolated power and grounds and fully differential PLL) there still may be
applications in which overall performance is being degraded due to system power supply
noise. The power supply filter schemes discussed in this section should be adequate to
eliminate power supply noise related problems in most designs.
3.3 V
Rs = 5 Ω to 15 Ω
PCK953
VCCA
0.01 µF
22 µF
VCC
0.01 µF
002aae139
Fig 3.
Power supply filter
PCK953_5
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 05 — 9 October 2008
6 of 15
PCK953
NXP Semiconductors
20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL clock driver
11.2 Driving transmission lines
The PCK953 clock driver was designed to drive high speed signals in a terminated
transmission line environment. To provide the optimum flexibility to the user, the output
drivers were designed to exhibit the lowest impedance possible. With an output
impedance of less than 20 Ω, the drivers can drive either parallel or series terminated
transmission lines.
In most high performance clock networks, point-to-point distribution of signals is the
method of choice. In a point-to-point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel technique terminates the signal at
the end of the line with a 50 Ω resistance to 0.5VCC. This technique draws a fairly high
level of DC current, and thus only a single terminated line can be driven by each output of
the PCK953 clock driver. For the series terminated case, however, there is no DC current
draw, thus the outputs can drive multiple series terminated lines. Figure 4 illustrates an
output driving a single series terminated line versus two series terminated lines in parallel.
When taken to its extreme, the fan-out of the PCK953 clock driver is effectively doubled
due to its capability to drive multiple lines.
PCK953
OUTPUT BUFFER
Ro
Rs = 36 Ω
Zo = 50 Ω
OutA
IN
14 Ω
PCK953
OUTPUT BUFFER
Rs = 36 Ω
Zo = 50 Ω
OutB0
Ro
IN
14 Ω
Rs = 36 Ω
Zo = 50 Ω
OutB1
002aae140
Fig 4.
Single versus dual transmission lines
The waveform plots of Figure 5 show the simulation results of an output driving a single
line versus two lines. In both cases, the drive capability of the PCK953 output buffers is
more than sufficient to drive 50 Ω transmission lines on the incident edge. Note from the
delay measurements in the simulations, a delta of only 43 ps exists between the two
differently loaded outputs. This suggests that the dual line driving need not be used
exclusively to maintain the tight output-to-output skew of the PCK953. The output
waveform in Figure 5 shows a step in the waveform; this step is caused by the impedance
mismatch seen looking into the driver. The parallel combination of the 43 Ω series resistor
plus the output impedance does not match the parallel combination of the line
impedances. The voltage wave launched down the two lines will equal:
Zo
V L = V S  ------------------------------
 R s + R o + Z o
(1)
Zo = 50 Ω || 50 Ω
Rs = 36 Ω || 36 Ω
Ro = 14 Ω
PCK953_5
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 05 — 9 October 2008
7 of 15
PCK953
NXP Semiconductors
20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL clock driver
25
25
V L = 3.0  ------------------------------ = 3.0  ------ = 1.31 V
 18 + 14 + 25
 57
(2)
At the load end, the voltage will double due to the near unity reflection coefficient, to
2.62 V. It will then increment towards the quiescent 3.0 V in steps separated by one
round-trip delay (in this case, 4.0 ns).
002aae141
3.0
voltage
(V)
OutA
td = 3.8956 ns
2.0
IN
OutB
td = 3.9386 ns
1.0
0
−0.5
0
4
8
12
16
time (ns)
Fig 5.
Single versus dual waveforms
Since this step is well above the threshold region, it will not cause any false clock
triggering, however, designers may be uncomfortable with unwanted reflections on the
line. To better match the impedances when driving multiple lines, the situation in Figure 6
should be used. In this case, the series terminating resistors are reduced such that when
the parallel combination is added to the output buffer impedance, the line impedance is
perfectly matched.
PCK953
OUTPUT BUFFER
Rs = 22 Ω
Zo = 50 Ω
Rs = 22 Ω
Zo = 50 Ω
Ro
IN
14 Ω
002aae142
14 Ω + 22 Ω || 22 Ω = 50 Ω || 50 Ω
25 Ω = 25 Ω
Fig 6.
Optimized dual line termination
SPICE level output buffer models are available for engineers who want to simulate their
specific interconnect schemes. In addition, IV characteristics are in the process of being
generated to support the other board-level simulators in general use.
PCK953_5
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 05 — 9 October 2008
8 of 15
PCK953
NXP Semiconductors
20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL clock driver
12. Package outline
LQFP32: plastic low profile quad flat package; 32 leads; body 7 x 7 x 1.4 mm
SOT358-1
c
y
X
24
A
17
16
25
ZE
e
E HE
A A2 A
1
(A 3)
wM
θ
bp
Lp
pin 1 index
L
32
9
detail X
1
8
e
ZD
v M A
wM
bp
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
v
w
y
mm
1.6
0.20
0.05
1.45
1.35
0.25
0.4
0.3
0.18
0.12
7.1
6.9
7.1
6.9
0.8
9.15
8.85
9.15
8.85
1
0.75
0.45
0.2
0.25
0.1
Z D (1) Z E (1)
0.9
0.5
0.9
0.5
θ
o
7
o
0
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
Fig 7.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT358 -1
136E03
MS-026
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
03-02-25
05-11-09
Package outline SOT358-1 (LQFP32)
PCK953_5
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 05 — 9 October 2008
9 of 15
PCK953
NXP Semiconductors
20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL clock driver
13. Packing information
Table 8.
Packing information
Type number
Ordering code
(12NC)
Package
Packing
Description
PCK953BD
9352 679 41118
SOT358-1
(LQFP32)
reel pack, SMD, 13”
180° rotation package orientation
in reel
PCK953BD
9352 679 41128
SOT358-1
(LQFP32)
reel pack, SMD, 13”, turned
JEDEC standard package orientation
in reel
PCK953BD
9352 679 41151
SOT358-1
(LQFP32)
tray pack, bakeable, single
PCK953BD
9352 679 41157
SOT358-1
(LQFP32)
tray pack, bakeable, multiple
PCK953BD/G
9352 761 22128
SOT358-1
(LQFP32)
reel pack, SMD, 13”, turned
JEDEC standard package orientation
in reel
14. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
PCK953_5
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 05 — 9 October 2008
10 of 15
PCK953
NXP Semiconductors
20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL clock driver
•
•
•
•
•
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
14.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 8) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 9 and 10
Table 9.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
≥ 350
< 350
< 2.5
235
220
≥ 2.5
220
220
Table 10.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
PCK953_5
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 05 — 9 October 2008
11 of 15
PCK953
NXP Semiconductors
20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL clock driver
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 8.
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 8.
Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
15. Abbreviations
Table 11.
Abbreviations
Acronym
Description
CMOS
Complementary Metal-Oxide Semiconductor
LPF
Low-Pass Filter
LVCMOS
Low Voltage Complementary Metal-Oxide Semiconductor
LVPECL
Low Voltage Positive Emitter-Coupled Logic
LVTTL
Low Voltage Transistor-Transistor Logic
PECL
Positive Emitter-Coupled Logic
PLL
Phase-Locked Loop
RC
Resistor-Capacitor network
SPICE
Simulation Program with Integrated Circuit Emphasis
VCO
Voltage Controlled Oscillator
PCK953_5
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 05 — 9 October 2008
12 of 15
PCK953
NXP Semiconductors
20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL clock driver
16. Revision history
Table 12.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCK953_5
20081009
Product data sheet
-
PCK953_4
Modifications:
•
The format of this data sheet has been redesigned to comply with the new identity guidelines of
NXP Semiconductors.
•
•
•
Legal texts have been adapted to the new company name where appropriate.
Section 2 “Features”, deleted (old) 8th bullet item
Section 3 “Ordering information”:
– added Type number PCK953BD/G
– added paragraph following Table 1
•
•
Table 4 “Limiting values”: removed (old) table note 1(now covered under Section 17.3
“Disclaimers”)
Table 5 “Static characteristics”:
– changed title of this table from “DC characteristics” to “Static characteristics”
– changed symbol “Vp-p” to “Vi(p-p)”
– changed symbol/parameter “VCMR, Common mode range” to “Vcm, common-mode voltage”
– changed symbol “IIN” to “II”
– changed symbol “CIN” to “Ci”
•
Table 6 “Dynamic characteristics”:
– changed title of this table from “AC characteristics” to “Dynamic characteristics”
– split “tr, tf” specification into 2 separate items, “tr(o), output rise time” and “tf(o), output fall time”
– changed symbol “tpw, output duty cycle” to “δo, output duty cycle”
– changed symbol “fMAX” to “fo(max)”
– changed symbol “tjitter” to “tjit(cc)”
– deleted (old) table note 1
•
•
Added Section 13 “Packing information”
Added soldering information
PCK953_4
20030731
(9397 750 11762)
Product data
ECN 853-2222 30050
dated 18 June 2003
PCK953_3
PCK953_3
20030502
(9397 750 11465)
Product data
ECN 853-2222 29827
dated 02 May 2003
PCK953_2
PCK953_2
20010208
(9397 750 08062)
Product data
ECN 853-2222 25600
dated 08 Feb 2001
PCK953_1
PCK953_1
Product data
-
-
20001025
PCK953_5
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 05 — 9 October 2008
13 of 15
PCK953
NXP Semiconductors
20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL clock driver
17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
17.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PCK953_5
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 05 — 9 October 2008
14 of 15
PCK953
NXP Semiconductors
20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL clock driver
19. Contents
1
2
3
4
5
5.1
5.2
6
6.1
7
8
9
10
11
11.1
11.2
12
13
14
14.1
14.2
14.3
14.4
15
16
17
17.1
17.2
17.3
17.4
18
19
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Function selection. . . . . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
PLL input reference characteristics. . . . . . . . . 5
Application information. . . . . . . . . . . . . . . . . . . 6
Power supply filtering . . . . . . . . . . . . . . . . . . . . 6
Driving transmission lines . . . . . . . . . . . . . . . . . 7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Packing information. . . . . . . . . . . . . . . . . . . . . 10
Soldering of SMD packages . . . . . . . . . . . . . . 10
Introduction to soldering . . . . . . . . . . . . . . . . . 10
Wave and reflow soldering . . . . . . . . . . . . . . . 10
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 11
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 11
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13
Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Contact information. . . . . . . . . . . . . . . . . . . . . 14
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 9 October 2008
Document identifier: PCK953_5
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