Data Sheet

INTEGRATED CIRCUITS
PCK2001R
533 MHz I2C 1:6 clock buffer
Product data
Supersedes data of 2000 Jul 25
Philips
Semiconductors
2002 Dec 13
Philips Semiconductors
Product data
533 MHz I2C 1:6 clock buffer
PCK2001R
• Individual SDRAM clock output enable/disable via I2C
• Multiple VDD, VSS pins for noise reduction
• 3.3 V operation
• ESD protection exceeds 2000 V per Standard 801.2
FEATURES
• Typically used to support four registered SDRAM DIMMs
• 16-pin SSOP package
• See PCK2001 for 48-pin 1:18 buffer part
• See PCK2001M for 28-pin 1:10 buffer part
• Operating frequency: 0 - 533 MHz
• Optimized for 33 MHz, 66 MHz, 100 MHz and 133 MHz operation
• Part-to-part skew < 500 ps
• 175 ps skew outputs typical
DESCRIPTION
The PCK2001R is a 1- 6 fanout buffer used for 133/100 MHz CPU,
66/33 MHz PCI, 14.318 MHz REF, or 133/100/66 MHz SDRAM clock
distribution. 6 outputs are typically used to support up to 4 registered
SDRAM DIMMs commonly found in server applications.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
2.5
2.5
ns
VCC = 3.3 V, CL = 30 pF
1.0
ns
VCC = 3.3 V, CL = 20 pF
700
ps
VCC = 3.465 V
50
µA
tPLH
tPHL
Propagation delay
BUF_IN to BUF_OUTn
VCC = 3.3 V, CL = 30 pF
tr
Rise time
tf
Fall time
Total supply current
ICC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
DRAWING NUMBER
16-Pin Plastic SSOP
0 to +70 °C
PCK2001RDB
SOT369-1
PIN CONFIGURATION
PIN DESCRIPTION
PIN
NUMBER
I/O
TYPE
SYMBOL
FUNCTION
1, 3
Output
BUF_OUT
(0, 2)
Buffered clock outputs
13, 15
Output
BUF_OUT
(11, 14)
Buffered clock outputs
6, 11
Output
BUF_OUT
(7, 17)
Buffered clock outputs
VSSI2C
4
Input
BUF_IN
SCL
8
I/O
SDA
I2C serial data
9
Input
SCL
I2C serial clock
12, 16
Input
VDD
(5, 9)
3.3 V power supply
2, 14
Input
VSS
(0, 9)
Ground
7
Input
VDDI2C
1
16
VDD9
VSS0
2
15
BUF_OUT14
BUF_OUT2
3
14
VSS9
BUF_IN
4
13
BUF_OUT11
12
VDD5
11
BUF_OUT17
PCK2001R
BUF_OUT0
VSS
5
BUF_OUT7
6
VDDI2C
7
10
SDA
8
9
TOP VIEW
SA00542
Intel and Pentium are registered trademarks of Intel Corporation.
I2C is a trademark of Philips Semiconductors Corporation.
10
2002 Dec 13
2
Input
2
VSSI C
Buffered clock input
3.3 V I2C power supply
I2C ground
Philips Semiconductors
Product data
533 MHz I2C 1:6 clock buffer
PCK2001R
FUNCTION TABLE
I2CEN
BUF_IN
BUF_OUTn
L
X
L
H
H
H
H
L
L
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to VSS (VSS = 0V).
SYMBOL
PARAMETER
VDD
DC 3.3 V supply voltage
IIK
DC input diode current
VI
DC input voltage
Note 2
DC output diode current
VO > VDD or VO < 0
VO
DC output voltage
Note 2
VO ≥ 0 to VDD
IO
DC output source or sink current
Storage temperature range
PTOT
Power dissipation per package
plastic medium-shrink SO (SSOP)
UNIT
MIN
MAX
-0.5
+4.6
V
-50
mA
VI < 0
IOK
Tstg
LIMITS
CONDITION
-0.5
5.5
V
±50
mA
-0.5
VCC + 0.5
V
±50
mA
-65
+150
°C
850
mW
For temperature range: 0 to +70 °C
above +55 °C derate linearly with 11.3mW/K
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
VDD
CL
VI
CONDITIONS
LIMITS
UNIT
MIN
MAX
DC 3.3 V supply voltage
3.135
3.465
V
Capacitive load
20
30
pF
DC input voltage range
0
VDD
V
VO
DC output voltage range
0
VDD
V
Tamb
Operating ambient temperature range in free air
0
+70
°C
2002 Dec 13
3
Philips Semiconductors
Product data
533 MHz I2C 1:6 clock buffer
PCK2001R
DC CHARACTERISTICS
SYMBOL
LIMITS
TEST CONDITIONS
PARAMETER
VDD
(V)
VIH
HIGH level input voltage
3.135 to 3.465
Tamb = 0°C to +70°C
OTHER
UNIT
MIN
MAX
2.0
VDD + 0.3
V
V
VIL
LOW level input voltage
3.135 to 3.465
VSS - 0.3
0.8
VOH
3.3V output HIGH voltage
3.135 to 3.465
IOH = -1mA
3.1
-
V
VOL
3.3V output LOW voltage
3.135 to 3.465
IOL= 1mA
-
50
mV
IOH
Output HIGH current
3.135 to 3.465
VOUT = 1.5V
-70
-185
mA
IOL
Output LOW current
3.135 to 3.465
VOUT = 1.5V
65
160
mA
±II
Input leakage current
3.465
-5
5
µA
ICC
Quiescent supply current
3.465
-
100
µA
2002 Dec 13
VI = VDD or GND
4
IO = 0
Philips Semiconductors
Product data
533 MHz I2C 1:6 clock buffer
PCK2001R
AC CHARACTERISTICS
LIMITS
Tamb = 0°C to +70°C
TEST CONDITIONS
SYMBOL
PARAMETER
tP
CLK period
tH
CLK HIGH time
33 MHz
UNIT
NOTES
MIN
TYP9
MAX
1, 6
29.9
30.0
30.2
2, 6, 8
12.3
14.3
16.3
tL
CLK LOW time
3, 6, 8
12.1
14.1
16.1
tP
CLK period
1, 6
14.9
15.0
15.2
tH
CLK HIGH time
2, 6, 8
5.6
6.8
8.0
66 MHz
ns
ns
tL
CLK LOW time
3, 6, 8
5.3
6.5
7.7
tP
CLK period
1,6
9.9
10.01
10.2
tH
CLK HIGH time
2, 6, 8
3.3
4.2
5.1
tL
CLK LOW time
3, 6, 8
3.2
4.1
5.0
tP
CLK period
1, 6
7.4
7.5
7.7
tH
CLK HIGH time
2, 6, 8
2.6
3.1
3.6
tL
CLK LOW time
3, 6, 8
2.2
2.7
3.2
tSDRISE
Rise time
4, 6, 10
1.5
2.0
4.0
V/ns
tSDFALL
Fall time
4, 6, 11
1.5
2.5
4.0
V/ns
tPLH
Buffer LH propagation delay
6, 7
1.0
2.4
3.5
ns
tPHL
Buffer HL propagation delay
6, 7
1.0
2.6
3.5
ns
DUTY CYCLE
Output Duty Cycle
5, 6, 7
45
tSKW
Bus CLK skew
tDDSKW
Device to device skew
100 MHz
133 MHz
Measured at 1.5 V
1, 6
ns
ns
50
55
%
150
250
ps
500
ps
NOTES:
1. Clock period and skew are measured on the rising edge at 1.5V.
2. tH is measured at 2.4V as shown in Figure 2.
3. tL is measured at 0.4V as shown in Figure 2.
4. tSDRISE and tSDFALL are measured as a transition through the threshold region VOL = 0.4V and VOH = 2.4V (1 mA) JEDEC specification.
5. Duty cycle should be tested with a 50/50% input.
6. Over MIN (20pF) to MAX (30pF) discrete load, process, voltage, and temperature.
7. Input edge rate for these tests must be faster than 1 V/ns.
8. Calculated at minimum edge rate (1.5ns) to guarantee 45/55% duty cycle at 1.5V. Pulsewidth is required to be wider at the faster edge to
ensure duty cycle specification is met.
9. All typical values are at VCC = 3.3V and Tamb = 25°C.
10. Typical is measured with MAX (30pF) discrete load.
11. Typical is measured with MIN (20pF) discrete load.
2002 Dec 13
5
Philips Semiconductors
Product data
533 MHz I2C 1:6 clock buffer
PCK2001R
I2C CONSIDERATIONS
I2C has been chosen as the serial bus interface to control the PCK2001R. I2C was chosen to support the JEDEC proposal JC-42.5 168 Pin
Unbuffered SDRAM DIMM. All vendors are required to determine the legal issues associated with the manufacture of I2C devices.
1) Address assignment: The clock driver in this specification uses the single, 7-bit address shown below. All devices can use the address if only
one master clock driver is used in a design. The address can be re-used for the CKBF device if no other conflicting I2C clock driver is used in
the system.
The following address was confirmed by Philips on 09/04/96.
A6
A5
A4
A3
A2
A1
A0
R/W
1
1
0
1
0
0
1
0
NOTE: The R/W bit is used by the I2C controller as a data direction bit. A ‘zero’ indicates a transmission (WRITE) to the clock device. A ‘one’
indicates a request for data (READ) from the clock driver. Since the definition of the clock buffer only allows the controller to WRITE data; the
R/W bit of the address will always be seen as ‘zero’. Optimal address decoding of this bit is left to the vendor.
2) Options: It is our understanding that metal mask options and other pinouts of this type of clock driver will be allowed to use the same address
as the original CKBF device. I2C addresses are defined in terms of function (master clock driver) rather than form (pinout, and option).
3) Slave/Receiver: The clock driver is assumed to require only slave/receiver functionality. Slave/transmitter functionality is optional.
4) Data Transfer Rate: 100 kbits/s (standard mode) is the base functionality required. Fast mode (400 kbits/s) functionality is optional.
5) Logic Levels: I2C logic levels are based on a percentage of VDD for the controller and other devices on the bus. Assume all devices are
based on a 3.3 Volt supply.
6) Data Byte Format: Byte format is 8 Bits as described in the following appendices.
7) Data Protocol: To simplify the clock I2C interface, the clock driver serial protocol was specified to use only block writes from the controller.
The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been
transferred. Indexed bytes are not allowed. However, the SMBus controller has a more specific format than the generic I2C protocol.
The clock driver must meet this protocol which is more rigorous than previously stated I2C protocol. Treat the description from the viewpoint of
controller. The controller ‘‘writes” to the clock driver and if possible would ‘‘read” from the clock driver (the clock driver is a slave/receiver only
and is incapable of this transaction.)
‘‘The block write begins with a slave address and a write condition. After the command code the host (controller) issues a byte count which
describes how many more bytes will follow in the message. If the host had 20 bytes to send, the first byte would be the number 20 (14h),
followed by the 20 bytes of data. The byte count may not be 0. A block write command is allowed to transfer a maximum of 32 data bytes.”
1 bit
7 bits
1
1
8 bits
1
Start bit
Slave Address
R/W
Ack
Command Code
Ack
Ack
Data Byte 1
Ack
Data Byte 2
Ack
1 bit
8 bits
1
8 bits
1
...
Byte Count = N
Data Byte 2
Ack
Stop
8 bits
1
1
SW00279
NOTE: The acknowledgement bit is returned by the slave/receiver (the clock driver).
Consider the command code and the byte count bytes required as the first two bytes of any transfer. The command code is software
programmable via the controller, but will be specified as 0000 0000 in the clock specification. The byte count byte is the number of additional
bytes required to transfer, not counting the command code and byte count bytes. Additionally, the byte count byte is required to be a minimum of
1 byte and a maximum of 32 bytes to satisfy the above requirement.
2002 Dec 13
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Philips Semiconductors
Product data
533 MHz I2C 1:6 clock buffer
PCK2001R
For example:
Notes:
Byte count byte
MSB
LSB
0000
0000
Not allowed. Must have at least one byte.
0000
0001
Data for functional and frequency select register (currently byte 0 in spec)
0000
0010
Reads first two bytes of data. (byte 0 then byte 1)
0000
0011
Reads first three bytes (byte 0, 1, 2 in order)
0000
0100
Reads first four bytes (byte 0, 1, 2, 3 in order)
0000
0101
Reads first five bytes (byte 0, 1, 2, 3, 4 in order)
0000
0110
Reads first six bytes (byte 0, 1, 2, 3, 4, 5 in order)
0000
0111
Reads first seven bytes (byte 0, 1, 2, 3, 4, 5, 6 in order)
0010
0000
Max byte count supported = 32
A transfer is considered valid after the acknowledge bit corresponding to the byte count is read by the controller. The serial controller interface
can be simplified by discarding the information in both the command code and the byte count bytes and simply reading all the bytes that are
sent to the clock driver after being addressed by the controller. It is expected that the controller will not provide more bytes than the clock driver
can handle. A clock vendor may choose to discard any number of bytes that exceed the defined byte count.
8) Clock stretching: The clock device must not hold/stretch the SCLOCK or SDATA lines low for more than 10 ms. Clock stretching is
discouraged and should only be used as a last resort. Stretching the clock/data lines for longer than this time puts the device in an error/time-out
mode and may not be supported in all platforms. It is assumed that all data transfers can be completed as specified without the use of
clock/data stretching.
9) General Call: It is assumed that the clock driver will not have to respond to the ‘‘general call.”
10) Electrical Characteristics: All electrical characteristics must meet the standard mode specifications found in section 15 of the I2C
specification.
a) Pull-Up Resistors: Any internal resistors pull-ups on the SDATA and SCLOCK inputs must be stated in the individual datasheet. The use of
internal pull-ups on these pins of below 100 kΩ is discouraged. Assume that the board designer will use a single external pull-up resistor for
each line and that these values are in the 5-6 kΩ range. Assume one I2C device per DIMM (serial presence detect), one I2C controller, one
clock driver plus one/two more I2C devices on the platform for capacitive loading purposes.
(b) Input Glitch Filters: Only fast mode I2C devices require input glitch filters to suppress bus noise. The clock driver is specified as a standard
mode device and is not required to support this feature.
11) PWR DWN: If a clock driver is placed in PWR DWN mode, the SDATA and SCLK inputs must be 3-Stated and the device must retain all
programming information. IDD current due to the I2C circuitry must be characterized and in the data sheet.
For specific I2C information consult the Philips I2C Peripherals Data Handbook IC12 (1997).
2002 Dec 13
7
Philips Semiconductors
Product data
533 MHz I2C 1:6 clock buffer
PCK2001R
SERIAL CONFIGURATION MAP
The serial bits will be read by the clock buffer in the following order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 2 - Bits 7, 6, 5, 4, 3, 2, 1, 0
All unused register bits (Reserved and N/A) should be desined as “Don’t Care”. It is expected that the controller will force all of these bits to a
“0” level.
All register bits labeled “Initialize to 0” must be written to zero during intialization. Failure to do so may result in a higher than normal operating
current. The controller will read back the last written value.
Byte 0: Active/inactive register
1 = enable; 0 = disable
BIT
PIN#
NAME
DESCRIPTION
7
6
BUF_OUT7
Active/Inactive
6
—
—
—
5
—
—
—
4
—
—
—
3
—
—
—
2
3
BUF_OUT2
Active/Inactive
1
—
—
—
0
1
BUF_OUT0
Active/Inactive
NOTE:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are
not expected to be configured during the normal modes of operation.
Byte 1: Active/inactive register
1 = enable; 0 = disable
BIT
PIN#
NAME
7
—
—
—
6
15
BUF_OUT14
Active/Inactive
5
—
—
—
DESCRIPTION
4
—
—
—
3
13
BUF_OUT11
Active/Inactive
2
—
—
—
1
—
—
—
0
—
—
—
NOTE:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are
not expected to be configured during the normal modes of operation.
Byte 2: Active/inactive register
BIT
PIN#
NAME
DESCRIPTION
7
11
BUF_OUT17
Active/Inactive
6
—
—
—
5
—
—
—
4
—
—
—
3
—
—
—
2
—
—
—
1
—
—
—
0
—
—
—
NOTE:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are
not expected to be configured during the normal modes of operation.
2002 Dec 13
8
Philips Semiconductors
Product data
533 MHz I2C 1:6 clock buffer
PCK2001R
AC WAVEFORMS
TEST CIRCUIT
VM = 1.5 V
VX = VOL + 0.3 V
VY = VOH -0.3 V
VOL and VOH are the typical output voltage drop that occur with the
output load.
VDD
VI
VDD
BUF_IN
INPUT
VM
VO
PULSE
GENERATOR
VM
D.U.T.
RT
tPLH
CL
500Ω
tPHL
VM
VM
SW00719
BUF_OUT
Figure 3. Load circuitry for switching times
SW00246
Figure 1. Load circuitry for switching times.
tp
th
DUTY CYCLE
2.4
1.5
0.4
tl
tr
tf
SW00613
Figure 2. Buffer Output clock
2002 Dec 13
9
Philips Semiconductors
Product data
533 MHz I2C 1:6 clock buffer
PCK2001R
SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm
2002 Dec 13
10
SOT369-1
Philips Semiconductors
Product data
533 MHz I2C 1:6 clock buffer
REVISION HISTORY
Rev
Date
PCK2001R
Description
_2
20021213
Product data (9397 750 10864); ECN 853-2210 29225 of 22 November 2002.
Modifications:
• Increase Fmax to 533 MHz.
_1
20000725
Product data (9397 750 07352); ECN 853-2210 24202 of 25 July 2000.
2002 Dec 13
11
Philips Semiconductors
Product data
533 MHz I2C 1:6 clock buffer
PCK2001R
Data sheet status
Level
Data sheet status[1]
Product
status[2] [3]
Definitions
I
Objective data
Development
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described
or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated
via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys
no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent,
copyright, or mask work right infringement, unless otherwise specified.
 Koninklijke Philips Electronics N.V. 2002
All rights reserved. Printed in U.S.A.
Contact information
For additional information please visit
http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
Date of release: 12-02
For sales offices addresses send e-mail to:
[email protected]
Document order number:
Philips
Semiconductors
2002 Dec 13
12
9397 750 10864
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