PCK351 1 : 10 clock distribution device with 3-state outputs Rev. 02 — 16 December 2005 Product data sheet 1. General description The PCK351 is a high-performance 3.3 V LVTTL clock distribution device. The PCK351 enables a single clock input to be distributed to ten outputs with minimum output skew and pulse skew. The use of distributed VCC and GND pins in the PCK351 ensures reduced switching noise. The PCK351 is characterized for operation over the supply range 3.0 V to 3.6 V, and over the industrial temperature range −40 °C to +85 °C. 2. Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 1 : 10 LVTTL clock distribution Low output-to-output skew Low output pulse skew Overvoltage tolerant inputs and outputs LVTTL-compatible inputs and outputs Distributed VCC and ground pins reduce switching noise Balanced high-drive outputs (−32 mA IOH, 32 mA IOL) Reduced power dissipation due to the state-of-the-art QUBiC-LP process Supply range of +3.0 V to +3.6 V Package options include plastic small-outline (D) and shrink small-outline (DB) packages ■ Industrial temperature range −40 °C to +85 °C PCK351 Philips Semiconductors 1 : 10 clock distribution device with 3-state outputs 3. Quick reference data Table 1: Quick reference data GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns. Symbol Parameter Conditions Min Typ Max Unit tPLH LOW-to-HIGH propagation delay A input to Yn outputs; CL = 50 pF; VCC = 3.3 V 3.1 3.6 4.1 ns tPHL HIGH-to-LOW propagation delay A input to Yn outputs; CL = 50 pF; VCC = 3.3 V 3.1 3.6 4.1 ns Ci input capacitance VCC = 3.3 V; VI = VCC or GND; f = 10 MHz - 4 - pF Co output capacitance VCC = 3.3 V; VO = VCC or GND; f = 10 MHz - 6 - pF CPD power dissipation capacitance [1] CL = 50 pF; f = 1 MHz - 48 - pF [1] CPD is used to determine the dynamic power dissipation (P in µW). P = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; ∑ (CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in volts. 4. Ordering information Table 2: Ordering information Tamb = −40 °C to +85 °C Type number Package Name Description Version PCK351D SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 PCK351DB SSOP24 plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1 PCK351_2 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 16 December 2005 2 of 18 PCK351 Philips Semiconductors 1 : 10 clock distribution device with 3-state outputs 5. Functional diagram OE 5 23 21 19 18 A Y1 Y2 Y3 Y4 6 16 14 11 9 4 2 Y5 Y6 Y7 Y8 Y9 Y10 002aaa282 Fig 1. Logic diagram of PCK351 PCK351_2 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 16 December 2005 3 of 18 PCK351 Philips Semiconductors 1 : 10 clock distribution device with 3-state outputs 6. Pinning information 6.1 Pinning GND 1 24 GND GND 1 24 GND Y10 2 23 Y1 Y10 2 23 Y1 VCC 3 VCC 3 Y9 4 22 VCC 21 Y2 Y9 4 22 VCC 21 Y2 OE 5 20 GND OE 5 20 GND A 6 19 Y3 A 6 GND 7 18 Y4 GND 7 GND 8 17 GND GND 8 17 GND Y8 9 16 Y5 Y8 9 16 Y5 PCK351D VCC 10 Y7 11 GND 12 15 VCC 14 Y6 VCC 10 13 GND GND 12 PCK351DB 18 Y4 15 VCC 14 Y6 Y7 11 13 GND 002aaa280 Fig 2. Pin configuration for SO24 19 Y3 002aaa281 Fig 3. Pin configuration for SSOP24 6.2 Pin description Table 3: Pin description Symbol Pin Description GND 1, 7, 8, 12, 13, 17, 20, 24 ground (0 V) Y10 2 outputs Y9 4 Y8 9 Y7 11 Y6 14 Y5 16 Y4 18 Y3 19 Y2 21 Y1 23 VCC 3, 10, 15, 22 supply voltage OE 5 output enable input (active LOW) A 6 data input PCK351_2 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 16 December 2005 4 of 18 PCK351 Philips Semiconductors 1 : 10 clock distribution device with 3-state outputs 7. Functional description Refer to Figure 1 “Logic diagram of PCK351”. 7.1 Function table Table 4: Function table H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state Inputs Outputs A OE Yn L H Z H H Z L L L H L H 7.2 Logic symbol OE A 5 EN 6 23 21 19 18 16 14 11 9 4 2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 002aaa283 Fig 4. Logic symbol PCK351_2 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 16 December 2005 5 of 18 PCK351 Philips Semiconductors 1 : 10 clock distribution device with 3-state outputs 8. Limiting values Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). [1] Symbol Parameter VCC Conditions Min Max Unit supply voltage −0.5 +4.6 V VI input voltage −0.5 [2] +7.0 V VO output voltage −0.5 [2] +3.6 V IIK input clamping current VI < 0 V - −18 mA IOK output clamping current VI < 0 V - −50 mA IO(sink) output sink current - 64 mA ICC quiescent supply current - ±75 mA IGND ground current - ±75 mA Tstg storage temperature −65 +150 °C P power dissipation SO package - 0.65 W SSOP package - 1.7 W Tamb = +55 °C [1] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C. [2] The input and output negative voltage ratings may be exceeded if the input and output clamping currents are observed. 9. Recommended operating conditions Table 6: Recommended operating conditions Unused pins (input or I/O) must be held HIGH or LOW. Symbol Parameter Conditions Max Unit VCC supply voltage 3.0 3.6 V VIH HIGH-state input voltage 2.0 5.5 V VI input voltage 0 0.8 V Tamb ambient temperature see Table 7 and Table 8 per device −40 +85 °C tr rise time input; VCC = 3.3 ± 0.3 V - 100 ns/V tf fall time input; VCC = 3.3 ± 0.3 V - 100 ns/V PCK351_2 Product data sheet Min © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 16 December 2005 6 of 18 PCK351 Philips Semiconductors 1 : 10 clock distribution device with 3-state outputs 10. Characteristics Table 7: Static characteristics Over recommended operating conditions; voltages are referenced to GND (ground = 0 V). Tamb = 25 °C. Symbol Parameter Conditions Min Typ Max Unit VIK input clamping voltage VCC = 3.0 V; II = −18 mA - - −1.2 V VOH HIGH-state output voltage VCC = 3.0 V; IOH = −32 mA 2.0 - - V VOL LOW-state output voltage VCC = 3.0 V; IOL = 32 mA - - 0.5 V ILI input leakage current VCC = 3.6 V; VI = GND or 5.5 V - - ±1.0 µA ILO output leakage current VCC = 3.6 V; VO = 2.5 V −15 - −150 mA - - ±10 µA outputs HIGH - - 0.3 mA outputs LOW - - 25 mA outputs disabled IOZ OFF-state output current 3-state; VCC = 3.6 V; VO = 3 V ICC quiescent supply current VCC = 3.6 V; VI = VCC or GND; IO = 0 A [1] - - 0.3 mA Ci input capacitance VCC = 3.3 V; VI = VCC or GND; f = 10 MHz - 4 - pF Co output capacitance VCC = 3.3 V; VO = VCC or GND; f = 10 MHz - 6 - pF [1] Not more than one output should be tested at a time, and the duration of the test should not exceed one second. PCK351_2 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 16 December 2005 7 of 18 PCK351 Philips Semiconductors 1 : 10 clock distribution device with 3-state outputs Table 8: Dynamic characteristics GND = 0 V; tr = tf ≤ 2.5 ns. Symbol Parameter Conditions Min Typ Max Unit VCC = 3.3 V; Tamb = 25 °C; CL = 50 pF tPLH LOW-to-HIGH propagation delay A to Yn; see Figure 5 and Figure 8 3.1 3.8 4.1 ns tPHL HIGH-to-LOW propagation delay A to Yn; see Figure 5 and Figure 8 3.1 3.8 4.1 ns tPZH OFF-state to HIGH propagation delay OE to Yn; see Figure 6 and Figure 8 1.8 3.8 5.5 ns tPZL OFF-state to LOW propagation delay OE to Yn; see Figure 6 and Figure 8 1.8 3.8 5.5 ns tPHZ HIGH to OFF-state propagation delay OE to Yn; see Figure 6 and Figure 8 1.8 3.8 5.9 ns tPLZ LOW to OFF-state propagation delay OE to Yn; see Figure 6 and Figure 8 1.8 3.8 5.9 ns tsk(o) output skew time A to Yn; output-to-output; see Figure 7 and Figure 8 - 0.3 0.5 ns tsk(p) pulse skew time A to Yn; see Figure 7 and Figure 8 - 0.2 0.8 ns tsk(pr) process skew time A to Yn; part-to-part; see Figure 7 and Figure 8 - - 1 ns tr rise time A to Yn; see Figure 5 and Figure 8 0.3 - 2.0 ns tf fall time A to Yn; see Figure 5 and Figure 8 0.3 - 2.0 ns 2.5 3.3 5.9 ns VCC = 3.0 V to 3.6 V; Tamb = −40 °C to +85 °C; CL = 50 pF tPLH LOW-to-HIGH propagation delay A to Yn; see Figure 5 and Figure 8 tPHL HIGH-to-LOW propagation delay A to Yn; see Figure 5 and Figure 8 2.5 3.3 5.9 ns tPZH OFF-state to HIGH propagation delay OE to Yn; see Figure 6 and Figure 8 1.3 - 5.9 ns tPZL OFF-state to LOW propagation delay OE to Yn; see Figure 6 and Figure 8 1.3 - 5.9 ns tPHZ HIGH to OFF-state propagation delay OE to Yn; see Figure 6 and Figure 8 1.7 - 6.3 ns tPLZ LOW to OFF-state propagation delay OE to Yn; see Figure 6 and Figure 8 1.7 - 6.3 ns tsk(o) output skew time A to Yn; output-to-output; see Figure 7 and Figure 8 - - 0.5 ns tsk(p) pulse skew time A to Yn; see Figure 7 and Figure 8 - - 0.8 ns tsk(pr) process skew time A to Yn; part-to-part; see Figure 7 and Figure 8 - - 1 ns tr rise time A to Yn; see Figure 5 and Figure 8 0.3 - 2.0 ns tf fall time A to Yn; see Figure 5 and Figure 8 0.3 - 2.0 ns PCK351_2 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 16 December 2005 8 of 18 PCK351 Philips Semiconductors 1 : 10 clock distribution device with 3-state outputs Table 9: Switching characteristics Temperature and VCC coefficients over recommended operating free-air temperature and VCC range. [1] Symbol Parameter Conditions Min Max Unit - 65 ps/10 °C ∆tPLH(T) temperature coefficient of LOW-to-HIGH propagation delay A to Yn (average value) [2] ∆tPHL(T) temperature coefficient of HIGH-to-LOW propagation delay A to Yn (average value) [2] - 45 ps/10 °C ∆tPLH(V) VCC coefficient of LOW-to-HIGH propagation delay A to Yn (average value) [3] - −140 ps/100 mV ∆tPHL(V) VCC coefficient of HIGH-to-LOW propagation delay A to Yn (average value) [3] - −120 ps/100 mV [1] These data were extracted from characterization material and are not tested at the factory. [2] ∆tPLH(T) and ∆tPHL(T) are virtually independent of VCC. [3] ∆tPLH(V) and ∆tPHL(V) are virtually independent of temperature. 10.1 AC waveforms 3.0 V A input 1.5 V 0V tPHL tPLH VOH 2V Yn output 1.5 V 0.8 V VOL tr tf 002aaa289 Fig 5. The input (A) to outputs (Yn) propagation delays and rise and fall times 3V OE input 1.5 V 0V tPZL tPLZ VCC output LOW-to-OFF OFF-to-LOW 1.5 V VOL + 0.3 V VOL tPHZ tPZH VOH VOH − 0.3 V output HIGH-to-OFF OFF-to-HIGH 1.5 V GND outputs disabled outputs disabled outputs disabled 002aaa290 Fig 6. 3-state enable and disable times PCK351_2 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 16 December 2005 9 of 18 PCK351 Philips Semiconductors 1 : 10 clock distribution device with 3-state outputs A input Y1 output tPHL(A-Y1) tPLH(A-Y1) tPHL(A-Y2) tPLH(A-Y2) tPHL(A-Y3) tPLH(A-Y3) tPHL(A-Y4) tPLH(A-Y4) tPHL(A-Y5) tPLH(A-Y5) tPHL(A-Y6) tPLH(A-Y6) tPHL(A-Y7) tPLH(A-Y7) tPHL(A-Y8) tPLH(A-Y8) tPHL(A-Y9) tPLH(A-Y9) tPHL(A-Y10) tPLH(A-Y10) Y2 output Y3 output Y4 output Y5 output Y6 output Y7 output Y8 output Y9 output Y10 output 002aaa286 Output-to-output skew is the highest values of positive and negative edge skew: tsk(o) = tPLH(A-Yn)(max) − tPLH(A-Yn)(min) and tsk(o) = tPHL(A-Yn)(max) − tPHL(A-Yn)(min). Output pulse skew is the highest value of: tsk(p) = |tPLH(A-Yn) − tPHL(A-Yn)|. Part-to-part skew tsk(pr) represents the positive and negative edge skew between outputs of several devices operating under identical conditions. Fig 7. Calculation of tsk(o), tsk(p), and tsk(pr) PCK351_2 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 16 December 2005 10 of 18 PCK351 Philips Semiconductors 1 : 10 clock distribution device with 3-state outputs 11. Test information S1 VCC PULSE GENERATOR VI RL 500 Ω VO 6V open GND DUT CL 50 pF RT RL 500 Ω 002aaa285 Test data are given in Table 10. CL = load capacitance includes jig and probe capacitance. RL = load resistance. RT = termination resistance. Fig 8. Load circuitry for switching times Table 10: Test Test data Load Switch CL RL tPLH, tPHL 50 pF 500 Ω open tPLZ, tPZL 50 pF 500 Ω 6V tPHZ, tPZH 50 pF 500 Ω GND PCK351_2 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 16 December 2005 11 of 18 PCK351 Philips Semiconductors 1 : 10 clock distribution device with 3-state outputs 12. Package outline SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 D E A X c HE y v M A Z 24 13 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 12 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 15.6 15.2 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.61 0.60 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT137-1 075E05 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 9. Package outline SOT137-1 (SO24) PCK351_2 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 16 December 2005 12 of 18 PCK351 Philips Semiconductors 1 : 10 clock distribution device with 3-state outputs SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm D SOT340-1 E A X c HE y v M A Z 24 13 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 12 bp e detail X w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 8.4 8.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 0.8 0.4 8 o 0 o Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT340-1 REFERENCES IEC JEDEC JEITA MO-150 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SOT340-1 (SSOP24) PCK351_2 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 16 December 2005 13 of 18 PCK351 Philips Semiconductors 1 : 10 clock distribution device with 3-state outputs 13. Soldering 13.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 13.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 °C to 270 °C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: • below 225 °C (SnPb process) or below 245 °C (Pb-free process) – for all BGA, HTSSON..T and SSOP..T packages – for packages with a thickness ≥ 2.5 mm – for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called thick/large packages. • below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. 13.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; PCK351_2 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 16 December 2005 14 of 18 PCK351 Philips Semiconductors 1 : 10 clock distribution device with 3-state outputs – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 13.4 Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 °C and 320 °C. 13.5 Package related soldering information Table 11: Suitability of surface mount IC packages for wave and reflow soldering methods Package [1] Soldering method Wave Reflow [2] BGA, HTSSON..T [3], LBGA, LFBGA, SQFP, SSOP..T [3], TFBGA, VFBGA, XSON not suitable suitable DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS not suitable [4] suitable PLCC [5], SO, SOJ suitable suitable not recommended [5] [6] suitable SSOP, TSSOP, VSO, VSSOP not recommended [7] suitable CWQCCN..L [8], PMFP [9], WQCCN..L [8] not suitable LQFP, QFP, TQFP [1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. [2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. [3] These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. PCK351_2 Product data sheet not suitable © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 16 December 2005 15 of 18 PCK351 Philips Semiconductors 1 : 10 clock distribution device with 3-state outputs [4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. [6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [7] Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [8] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. [9] Hot bar soldering or manual soldering is suitable for PMFP packages. 14. Revision history Table 12: Revision history Document ID Release date Data sheet status Change notice Doc. number Supersedes PCK351_2 20051216 Product data sheet - - PCK351-01 Modifications: • The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors. • • Section 2 “Features”: deleted (old) 12th bullet • Table 2 “Ordering information”: changed “Temperature range = −65 °C to +150 °C” to “Tamb = −40 °C to +85 °C” Table 5 “Limiting values”: – removed (old) Table note [1]; this is now presented in the Definitions section – symbol “IO” changed to “IO(sink)” – row “ICC, IGND” split to 2 rows, and parameter for each revised • Table 6 “Recommended operating conditions”: – moved (old) Table note [1] to description below table title – split row “tr, tf” • Table 7 “Static characteristics”: changed parameter description of VIK from “input diode voltage” to “input clamping voltage” • Table 8 “Dynamic characteristics”: – in descriptive line below table title: changed “tr = tf = ≤ 3.0 ns” to “tr = tf = ≤ 2.5 ns” – (VCC = 3.3 V) typical value for tPLH and tPHL (A to Yn) changed from 3.6 ns to 3.8 ns – (VCC = 3.3 V) typical value for tPHZ and tPZH (OE to Yn) changed from 4.0 ns to 3.8 ns – (VCC = 3.3 V) tr and tf minimum values changed from “-” to “0.3 ns”; maximum values changed from “-” to “2.0 ns” – subheading “VCC = 3.3 to 3.6 V; Tamb = 0 °C to +70 °C” changed to “VCC = 3.0 V to 3.6 V; Tamb = −40 °C to +85 °C” – (VCC = 3.0 V to 3.6 V) values for tPLH and tPHL (A to Yn) changed from “-” to “2.5 ns” (min), “3.3 ns” (typ), “5.9 ns” (max) – (VCC = 3.0 V to 3.6 V) tr and tf minimum values changed from “-” to “0.3 ns”; maximum values changed from “-” to “2.0 ns” PCK351-01 20020514 Product data 853-2344 28198 PCK351_2 Product data sheet 9397 750 09791 - © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 16 December 2005 16 of 18 PCK351 Philips Semiconductors 1 : 10 clock distribution device with 3-state outputs 15. Data sheet status Level Data sheet status [1] Product status [2] [3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 16. Definitions customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 18. Trademarks 17. Disclaimers Notice — All referenced brands, product names, service names and trademarks are the property of their respective owners. Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors 19. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: [email protected] PCK351_2 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 16 December 2005 17 of 18 PCK351 Philips Semiconductors 1 : 10 clock distribution device with 3-state outputs 20. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 8 9 10 10.1 11 12 13 13.1 13.2 13.3 13.4 13.5 14 15 16 17 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Logic symbol. . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 6 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 7 AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . 9 Test information . . . . . . . . . . . . . . . . . . . . . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 14 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 14 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 15 Package related soldering information . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information . . . . . . . . . . . . . . . . . . . . 17 © Koninklijke Philips Electronics N.V. 2005 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 16 December 2005 Document number: PCK351_2 Published in The Netherlands