Data Sheet

GTL2007
12-bit GTL to LVTTL translator with power good control
Rev. 02 — 16 February 2007
Product data sheet
1. General description
The GTL2007 is a customized translator between dual Xeon processors, Platform Health
Management, South Bridge and Power Supply LVTTL and GTL signals.
The GTL2007 is derived from the GTL2006 with an enable function added that disables
the error output to the monitoring agent for platforms that monitor the individual error
conditions from each processor. This enable function can be used so that false error
conditions are not passed to the monitoring agent when the system is unexpectedly
powered down. This unexpected power-down could be from a power supply overload, a
CPU thermal trip, or some other event of which the monitoring agent is unaware.
A typical implementation would be to connect each enable line to the system power good
signal or the individual enables to the VRD power good for each processor.
Typically Xeon processors specify a VTT of 1.1 V to 1.2 V, as well as a nominal Vref of
0.73 V to 0.76 V. To allow for future voltage level changes that may extend Vref to 0.63 of
VTT (minimum of 0.693 V with VTT of 1.1 V) the GTL2007 allows a minimum Vref of 0.66 V.
Characterization results show that there is little DC or AC performance variation between
these Vref levels.
2. Features
n
n
n
n
n
n
n
Operates as a GTL to LVTTL sampling receiver or LVTTL to GTL driver
Operates at GTL−/GTL/GTL+ signal levels
EN1 and EN2 disable error output
3.0 V to 3.6 V operation
LVTTL I/O not 5 V tolerant
Series termination on the LVTTL outputs of 30 Ω
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
n Latch-up testing is done to JEDEC Standard JESD78 which exceeds 500 mA
n Package offered: TSSOP28
GTL2007
NXP Semiconductors
12-bit GTL to LVTTL translator with power good control
3. Quick reference data
Table 1.
Quick reference data
Tamb = 25 °C.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Cio
input/output capacitance
A port; VO = 3.0 V or 0 V
-
2.5
3.5
pF
B port; VO = VTT or 0 V
-
1.5
2.5
pF
Vref = 0.73 V; VTT = 1.1 V
tPLH
tPHL
LOW-to-HIGH
propagation delay
nA to nB; see Figure 4
1
4
8
ns
nBI to nAO; see Figure 5
2
5.5
10
ns
HIGH-to-LOW
propagation delay
nA to nB; see Figure 4
2
5.5
10
ns
nBI to nAO; see Figure 5
2
5.5
10
ns
nA to nB; see Figure 4
1
4
8
ns
Vref = 0.76 V; VTT = 1.2 V
tPLH
LOW-to-HIGH
propagation delay
tPHL
HIGH-to-LOW
propagation delay
nBI to nAO; see Figure 5
2
5.5
10
ns
nA to nB; see Figure 4
2
5.5
10
ns
nBI to nAO; see Figure 5
2
5.5
10
ns
4. Ordering information
Table 2.
Ordering information
Tamb = −40 °C to +85 °C.
Type number
GTL2007PW
Topside
mark
Package
Name
Description
Version
GTL2007
TSSOP28
plastic thin shrink small outline package;
28 leads; body width 4.4 mm
SOT361-1
GTL2007_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 16 February 2007
2 of 20
GTL2007
NXP Semiconductors
12-bit GTL to LVTTL translator with power good control
5. Functional diagram
GTL2007
GTL VREF
1AO
1
27
2
1BI
GTL inputs
LVTTL outputs
2AO
5A
LVTTL inputs/outputs
(open-drain)
6A
LVTTL input
EN1
GTL input
11BI
LVTTL input/output
(open-drain)
11A
GTL input
9BI
26
3
4
&
5
25
24
6
8
23
1
22
7BO2
EN2
LVTTL input
11BO
GTL output
DELAY(1)
21
9
7BO1
GTL outputs
&
7
2BI
5BI
DELAY(1)
20
6BI
GTL inputs
3AO
19
10
3BI
LVTTL outputs
4AO
18
11
1
10AI1
12
1
LVTTL inputs
10AI2
13
17
4BI
10BO1
GTL outputs
16
15
10BO2
9AO
LVTTL output
002aab210
(1) The enable on 7BO1/7BO2 include a delay that prevents the transient condition where 5BI/6BI go from LOW to HIGH, and
the LOW to HIGH on 5A/6A lags up to 100 ns from causing a LOW glitch on the 7BO1/7BO2 outputs.
Fig 1. Logic diagram of GTL2007
GTL2007_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 16 February 2007
3 of 20
GTL2007
NXP Semiconductors
12-bit GTL to LVTTL translator with power good control
6. Pinning information
6.1 Pinning
VREF
1
28 VCC
1AO
2
27 1BI
2AO
3
26 2BI
5A
4
25 7BO1
6A
5
24 7BO2
EN1
6
23 EN2
11BI
7
11A
8
9BI
9
20 6BI
3AO 10
19 3BI
4AO 11
18 4BI
GTL2007PW
22 11BO
21 5BI
10AI1 12
17 10BO1
10AI2 13
16 10BO2
GND 14
15 9AO
002aab209
Fig 2. Pin configuration for TSSOP28
6.2 Pin description
Table 3.
Pin description
Symbol
Pin
Description
VREF
1
GTL reference voltage
1AO
2
data output (LVTTL)
2AO
3
data output (LVTTL)
5A
4
data input/output (LVTTL), open-drain
6A
5
data input/output (LVTTL), open-drain
EN1
6
enable input (LVTTL)
11BI
7
data input (GTL)
11A
8
data input/output (LVTTL), open-drain
9BI
9
data input (GTL)
3AO
10
data output (LVTTL)
4AO
11
data output (LVTTL)
10AI1
12
data input (LVTTL)
10AI2
13
data input (LVTTL)
GND
14
ground (0 V)
9AO
15
data output (LVTTL)
10BO2
16
data output (GTL)
10BO1
17
data output (GTL)
4BI
18
data input (GTL)
3BI
19
data input (GTL)
GTL2007_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 16 February 2007
4 of 20
GTL2007
NXP Semiconductors
12-bit GTL to LVTTL translator with power good control
Table 3.
Pin description …continued
Symbol
Pin
Description
6BI
20
data input (GTL)
5BI
21
data input (GTL)
11BO
22
data output (GTL)
EN2
23
enable input (LVTTL)
7BO2
24
data output (GTL)
7BO1
25
data output (GTL)
2BI
26
data input (GTL)
1BI
27
data input (GTL)
VCC
28
positive supply voltage
7. Functional description
Refer to Figure 1 “Logic diagram of GTL2007”.
7.1 Function tables
Table 4.
GTL input signals
H = HIGH voltage level; L = LOW voltage level.
Input
Output[1]
1BI/2BI/3BI/4BI/9BI
1AO/2AO/3AO/4AO/9AO
L
L
H
H
[1]
1AO, 2AO, 3AO, 4AO and 5A/6A condition changed by ENn power good signal as described in Table 5 and
Table 6.
Table 5.
EN1 power good signal
H = HIGH voltage level; L = LOW voltage level.
EN1
1AO and 2AO
5A
L
H
5BI disconnected
H
follows BI
5BI connected
Table 6.
EN2 power good signal
H = HIGH voltage level; L = LOW voltage level.
EN2
3AO and 4AO
6A
L
H
6BI disconnected
H
follows BI
6BI connected
GTL2007_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 16 February 2007
5 of 20
GTL2007
NXP Semiconductors
12-bit GTL to LVTTL translator with power good control
Table 7.
SMI signals
H = HIGH voltage level; L = LOW voltage level.
Input
Input
Output
10AI1/10AI2
9BI
10BO1/10BO2
L
L
L
L
H
L
H
L
L
H
H
H
Table 8.
PROCHOT signals
H = HIGH voltage level; L = LOW voltage level.
Input
Input/output
Output
5BI/6BI
5A/6A (open-drain)
7BO1/7BO2
L
L
H[1]
H
L[2]
L
H
H
H
[1]
The enable on 7BO1/7BO2 includes a delay that prevents the transient condition where 5BI/6BI go from
LOW to HIGH, and the LOW to HIGH on 5A/6A lags up to 100 ns from causing a LOW glitch on the
7BO1/7BO2 outputs.
[2]
Open-drain input/output terminal is driven to logic LOW state by other driver.
Table 9.
NMI signals
H = HIGH voltage level; L = LOW voltage level.
Input
Input/output
Output
11BI
11A (open-drain)
11BO
L
H
L
L
L[1]
H
H
L
H
[1]
Open-drain input/output terminal is driven to logic LOW state by other driver.
GTL2007_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 16 February 2007
6 of 20
GTL2007
NXP Semiconductors
12-bit GTL to LVTTL translator with power good control
8. Application design-in information
VTT
VTT
56 Ω
56 Ω
R
VCC
1.5 kΩ to 1.2 kΩ
2R
1.5 kΩ
PLATFORM
HEALTH
MANAGEMENT
VCC
VREF
VCC
CPU1
CPU1 1ERR_L
1AO
1BI
IERR_L
CPU1 THRMTRIP L
2AO
2BI
THRMTRIP L
CPU1 PROCHOT L
5A
7BO1
FORCEPR_L
CPU2 PROCHOT L
6A
7BO2
EN1
EN2
11B1
11B0
PROCHOT L
NMI
CPU1 DISABLE_L
GTL2007
11A
5BI
9BI
6BI
PROCHOT L
CPU2 1ERR_L
3AO
3BI
IERR_L
CPU2 THRMTRIP L
4AO
4BI
THRMTRIP L
NMI_L
FORCEPR_L
CPU1 SMI L
10AI1
10BO1
NMI
CPU2 SMI L
10AI2
10BO2
CPU2 DISABLE_L
SMI_BUFF_L
GND
9AO
CPU2
SOUTHBRIDGE NMI
SOUTHBRIDGE SMI_L
power supply
POWER GOOD
002aab211
Fig 3. Typical application
GTL2007_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 16 February 2007
7 of 20
GTL2007
NXP Semiconductors
12-bit GTL to LVTTL translator with power good control
9. Limiting values
Table 10. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Max
Unit
−0.5
+4.6
V
-
−50
mA
VCC
supply voltage
IIK
input clamping current
VI < 0 V
VI
input voltage
A port (LVTTL)
[2]
−0.5
+4.6
V
B port (GTL)
[2]
−0.5
+4.6
V
IOK
output clamping current
VO < 0 V
-
−50
mA
VO
output voltage
output in OFF or HIGH state; A port
[2]
−0.5
+4.6
V
output in OFF or HIGH state; B port
[2]
−0.5
+4.6
V
A port
-
32
mA
B port
-
30
mA
A port
-
−32
mA
−60
+150
°C
-
+125
°C
current[3]
IOL
LOW-level output
IOH
HIGH-level output current[4]
Tstg
storage temperature
Tj(max)
[5]
maximum junction temperature
[1]
Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under Section 10 “Recommended operating conditions” is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
[2]
The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
[3]
Current into any output in the LOW state.
[4]
Current into any output in the HIGH state.
[5]
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.
10. Recommended operating conditions
Table 11.
Operating conditions
Symbol
Parameter
VCC
supply voltage
VTT
termination voltage
Vref
VI
Min
Typ
Max
Unit
3.0
3.3
3.6
V
GTL
-
1.2
-
V
reference voltage
GTL
0.64
0.8
1.1
V
input voltage
A port
0
3.3
3.6
V
B port
0
VTT
3.6
V
A port and ENn
2
-
-
V
B port
Vref + 0.050
-
-
V
A port and ENn
-
-
0.8
V
B port
-
-
Vref − 0.050
V
A port
-
-
−16
mA
VIH
HIGH-level input voltage
VIL
LOW-level input voltage
IOH
HIGH-level output current
IOL
LOW-level output current
Tamb
ambient temperature
Conditions
A port
-
-
16
mA
B port
-
-
15
mA
operating in free-air
−40
-
+85
°C
GTL2007_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 16 February 2007
8 of 20
GTL2007
NXP Semiconductors
12-bit GTL to LVTTL translator with power good control
11. Static characteristics
Table 12. Static characteristics
Recommended operating conditions; voltages are referenced to GND (ground = 0 V). Tamb = −40 °C to +85 °C.
Symbol
VOH
Parameter
HIGH-level output
voltage
LOW-level output
voltage
VOL
input current
II
Min
Typ[1]
Max
Unit
A port; VCC = 3.0 V to 3.6 V;
IOH = −100 µA
[2]
VCC − 0.2
3.0
-
V
A port; VCC = 3.0 V; IOH = −16 mA
[2]
2.1
2.3
-
V
A port; VCC = 3.0 V; IOL = 4 mA
[2]
-
0.15
0.4
V
A port; VCC = 3.0 V; IOL = 8 mA
[2]
-
0.3
0.55
V
A port; VCC = 3.0 V; IOL = 16 mA
[2]
-
0.6
0.8
V
B port; VCC = 3.0 V; IOL = 15 mA
[2]
-
0.13
0.4
V
A port; VCC = 3.6 V; VI = VCC
-
-
±1
µA
A port; VCC = 3.6 V; VI = 0 V
-
-
±1
µA
Conditions
B port; VCC = 3.6 V; VI = VTT or GND
-
-
±1
µA
ICC
supply current
A or B port; VCC = 3.6 V;
VI = VCC or GND; IO = 0 mA
-
8
12
mA
∆ICC[3]
additional supply
current
per input; A port or control inputs;
VCC = 3.6 V; VI = VCC − 0.6 V
-
-
500
µA
Cio
input/output
capacitance
A port; VO = 3.0 V or 0 V
-
2.5
3.5
pF
B port; VO = VTT or 0 V
-
1.5
2.5
pF
[1]
All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
[2]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[3]
This is the increase in supply current for each input that is at the specified LVTTL voltage level rather than VCC or GND.
GTL2007_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 16 February 2007
9 of 20
GTL2007
NXP Semiconductors
12-bit GTL to LVTTL translator with power good control
12. Dynamic characteristics
Table 13. Dynamic characteristics
VCC = 3.3 V ± 0.3 V.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
Vref = 0.73 V; VTT = 1.1 V
tPLH
tPHL
LOW-to-HIGH propagation delay
HIGH-to-LOW propagation delay
nA to nB; see Figure 4
1
4
8
ns
nBI to nAO; see Figure 5
2
5.5
10
ns
9BI to 10BOn
2
6
11
ns
11BI to 11BO
2
8
13
ns
5BI to 7BO1 or 6BI to 7BO2;
see Figure 7
4
7
12
ns
EN1 to nAO or EN2 to nAO;
see Figure 8
2
6.5
10
ns
nA to nB; see Figure 4
2
5.5
10
ns
nBI to nAO; see Figure 5
2
5.5
10
ns
2
6
11
ns
2
14
21
ns
5BI to 7BO1 or 6BI to 7BO2;
see Figure 7
100
205
350
ns
EN1 to nAO or EN2 to nAO;
see Figure 8
2
6.5
10
ns
9BI to 10BOn
11BI to 11BO
tPLZ
LOW to OFF-state propagation delay nBI to nA (I/O); see Figure 6
EN1 to 5A (I/O) or EN2 to 6A
(I/O); see Figure 9
tPZL
OFF-state to LOW propagation delay nBI to nA (I/O); see Figure 6
EN1 to 5A (I/O) or EN2 to 6A
(I/O); see Figure 9
GTL2007_2
Product data sheet
[2]
2
13
18
ns
1
3
7
ns
2
12
16
ns
2
7
10
ns
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 16 February 2007
10 of 20
GTL2007
NXP Semiconductors
12-bit GTL to LVTTL translator with power good control
Table 13. Dynamic characteristics …continued
VCC = 3.3 V ± 0.3 V.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
nA to nB; see Figure 4
1
4
8
ns
Vref = 0.76 V; VTT = 1.2 V
LOW-to-HIGH propagation delay
tPLH
HIGH-to-LOW propagation delay
tPHL
nBI to nAO; see Figure 5
2
5.5
10
ns
9BI to 10BOn
2
6
11
ns
11BI to 11BO
2
8
13
ns
5BI to 7BO1 or 6BI to 7BO2;
see Figure 7
4
7
12
ns
EN1 to nAO or EN2 to nAO;
see Figure 8
2
6.5
10
ns
nA to nB; see Figure 4
2
5.5
10
ns
nBI to nAO; see Figure 5
2
5.5
10
ns
9BI to 10BOn
2
6
11
ns
2
14
21
ns
5BI to 7BO1 or 6BI to 7BO2;
see Figure 7
100
205
350
ns
EN1 to nAO or EN2 to nAO;
see Figure 8
2
6.5
10
ns
LOW to OFF-state propagation delay nBI to nA (I/O); see Figure 6
2
13
18
ns
EN1 to 5A (I/O) or EN2 to 6A
(I/O); see Figure 9
1
3
7
ns
OFF-state to LOW propagation delay nBI to nA (I/O); see Figure 6
2
12
16
ns
EN1 to 5A (I/O) or EN2 to 6A
(I/O); see Figure 9
2
7
10
ns
[2]
11BI to 11BO
tPLZ
tPZL
[1]
All typical values are at VCC = 3.3 V and Tamb = 25 °C.
[2]
Includes ~7.6 ns RC rise time of test load pull-up on 11A, 1.5 kΩ pull-up and 21 pF load on 11A has about 23 ns RC rise time.
12.1 Waveforms
VM = 1.5 V at VCC ≥ 3.0 V for A ports; VM = Vref for B ports.
3.0 V
input
1.5 V
1.5 V
0V
tPLH
tp
tPHL
VTT
VOH
VM
output
VM
Vref
Vref
VOL
0V
002aab000
002aaa999
VM = 3.0 V for A port and VTT for B port
a. Pulse duration
A port to B port
b. Propagation delay times
Fig 4. Voltage waveforms
GTL2007_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 16 February 2007
11 of 20
GTL2007
NXP Semiconductors
12-bit GTL to LVTTL translator with power good control
VTT
input
Vref
VTT
Vref
input
1/ V
3 TT
tPLH
tPHL
Vref
Vref
tPZL
tPLZ
1/ V
3 TT
VOH
1.5 V
output
VCC
1.5 V
output
1.5 V
VOL + 0.3 V
VOL
002aab001
002aab002
PRR ≤ 10 MHz; ZO = 50 Ω; tr ≤ 2.5 ns; tf ≤ 2.5 ns
Fig 5. Propagation delay, nBI to nAO
Fig 6. nBI to nA (I/O)
VTT
input
Vref
Vref
tPLH
tPHL
3.0 V
input
1/ V
3 TT
1.5 V
1.5 V
tPLH
tPHL
0V
VTT
output
Vref
VOH
1.5 V
output
Vref
1.5 V
VOL
VOL
002aab003
002aab004
Fig 7. 5BI to 7BO1 or 6BI to 7BO2
Fig 8. EN1 to nAO or EN2 to nAO
3.0 V
input
1.5 V
1.5 V
tPLZ
tPZL
0V
VOH
output
VOL + 0.3 V
1.5 V
VOL
002aab005
Fig 9. EN1 to 5A (I/O) or EN2 to 6A (I/O)
GTL2007_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 16 February 2007
12 of 20
GTL2007
NXP Semiconductors
12-bit GTL to LVTTL translator with power good control
13. Test information
VCC
PULSE
GENERATOR
VI
VO
DUT
RL
500 Ω
CL
50 pF
RT
002aab006
Fig 10. Load circuit for A outputs
VTT
VCC
VI
PULSE
GENERATOR
50 Ω
VO
DUT
CL
30 pF
RT
002aab264
Fig 11. Load circuit for B outputs
VCC
VCC
PULSE
GENERATOR
VI
RL
1.5 kΩ
VO
DUT
RT
CL
21 pF
002aab265
RL = load resistor.
CL = load capacitance; includes jig and probe capacitance.
RT = termination resistance; should be equal to Zo of pulse generators.
Fig 12. Load circuit for open-drain LVTTL I/O
GTL2007_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 16 February 2007
13 of 20
GTL2007
NXP Semiconductors
12-bit GTL to LVTTL translator with power good control
14. Package outline
TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm
D
SOT361-1
E
A
X
c
HE
y
v M A
Z
15
28
Q
A2
(A 3)
A1
pin 1 index
A
θ
Lp
1
L
14
detail X
w M
bp
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
9.8
9.6
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.8
0.5
8
o
0
o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT361-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-153
Fig 13. Package outline SOT361-1 (TSSOP28)
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15. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
15.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
15.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus PbSn soldering
15.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
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Rev. 02 — 16 February 2007
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15.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 14) than a PbSn process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 14 and 15
Table 14.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 15.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 14.
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maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 14. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
16. Abbreviations
Table 16.
Abbreviations
Acronym
Description
CDM
Charged Device Model
CMOS
Complementary Metal Oxide Silicon
CPU
Central Processing Unit
DUT
Device Under Test
ESD
Electrostatic Discharge
GTL
Gunning Transceiver Logic
HBM
Human Body Model
LVTTL
Low Voltage Transistor-Transistor Logic
MM
Machine Model
PRR
Pulse Rate Repetition
TTL
Transistor-Transistor Logic
VRD
Voltage Regulator Down
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17. Revision history
Table 17.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
GTL2007_2
20070216
Product data sheet
-
GTL2007_1
Modifications:
•
The format of this data sheet has been redesigned to comply with the new identity guidelines of
NXP Semiconductors.
•
•
Legal texts have been adapted to the new company name where appropriate.
•
Data sheet descriptive title changed from “13-bit GTL to LVTTL translator with power good control”
to “12-bit GTL to LVTTL translator with power good control”
Section 1 “General description”:
– 4th paragraph re-written
– deleted (old) 5th paragraph
•
•
•
Section 2 “Features”: added (new) 2nd bullet item
Figure 1 “Logic diagram of GTL2007”: updated symbols to IEC convention
Figure 3 “Typical application” modified:
– in blocks CPU1 and CPU2, changed “SMI L” to “DISABLE_L”
– in block PLATFORM HEALTH MANAGEMENT: changed “CPU2 IERR_L” to “CPU2 1ERR_L”
•
•
•
Table 10 “Limiting values”: parameter definitions updated; added Table note 3 and Table note 4
Table 13 “Dynamic characteristics”: data reorganized (no specification changed)
Table 16 “Abbreviations”: added “DUT”
GTL2007_1
20050602
(9397 750 13264)
Product data sheet
-
GTL2007_2
Product data sheet
-
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Rev. 02 — 16 February 2007
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18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
18.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
19. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: [email protected]
GTL2007_2
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20. Contents
1
2
3
4
5
6
6.1
6.2
7
7.1
8
9
10
11
12
12.1
13
14
15
15.1
15.2
15.3
15.4
16
17
18
18.1
18.2
18.3
18.4
19
20
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Function tables . . . . . . . . . . . . . . . . . . . . . . . . . 5
Application design-in information . . . . . . . . . . 7
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8
Recommended operating conditions. . . . . . . . 8
Static characteristics. . . . . . . . . . . . . . . . . . . . . 9
Dynamic characteristics . . . . . . . . . . . . . . . . . 10
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Test information . . . . . . . . . . . . . . . . . . . . . . . . 13
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Introduction to soldering . . . . . . . . . . . . . . . . . 15
Wave and reflow soldering . . . . . . . . . . . . . . . 15
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 15
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 16
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18
Legal information. . . . . . . . . . . . . . . . . . . . . . . 19
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Contact information. . . . . . . . . . . . . . . . . . . . . 19
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 16 February 2007
Document identifier: GTL2007_2
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