Data Sheet

GTL1655
16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion
Rev. 01 — 11 May 2004
Product data
1. Description
The GTL1655 is a 16-bit bus transceiver that incorporates HIGH-drive
LOW-output-impedance (100 mA/12 Ω) with LVTTL-to-GTL/GTL+ and
GTL/GTL+-to-LVTTL logic level translation.
The device is configured as two 8-bit transceivers that share a common clock and a
master output enable pin, but also have individual latch timing and output enable
signals. D-type flip-flops and D-type latches enable three modes of data transfer;
Clocked, Latched, or Transparent. The GTL1655 provides the ideal interface between
cards operating at LVTTL levels and backplanes using GTL/GTL+ signal levels. The
combination of reduced output swing, reduced input threshold levels and configurable
edge control provides the higher speed operation of GTL/GTL+ backplanes.
The GTL1655 can be used at GTL (VTT = 1.2 V, VREF = 0.8 V) or GTL+ (VTT = 1.5 V,
VREF = 1.0 V) signalling levels. Port A and the control inputs are compliant with
LVTTL signal levels and are 5 V tolerant. Port B is designed to operate at GTL or
GTL+ signal levels, with VREF providing the reference voltage input.
The latch enable pins (nLEAB and nLEBA), the output enable pins (nOEAB, nOEBA)
and the clock pin (CP) are used to control the data flow through the two 8-bit
transceivers (n = 1 or 2). When nLEAB is set HIGH, the device will operate in the
transparent mode Port A to Port B. HIGH-to-LOW transitions of nLEAB will latch A
data independently of CP HIGH or LOW (latched mode). LOW-to-HIGH transitions of
CP will clock A data to the B port if nLEAB is LOW (clocked mode). Using the control
pins nLEBA, nOEBA and CP in the same way, data flow from Port B to Port A can be
controlled. The OE pin can be used to disable all of the I/O pins.
To optimize signal integrity, the GTL1655 features an adjustable edge rate control
(VERC). By adjusting VERC between GND and VCC, a designer can adjust the Port B
edge rate to suit an application’s load conditions.
The GTL1655 permits true live insertion capability by incorporating:
• BIAS VCC, to pre-charge outputs and avoid disturbing active data during card
insertion.
• Ioff to disable current flow through powered-off I/Os.
• Power-up 3-state, which ensures outputs are high-impedance during power-up,
thus preventing bus contention issues. Once VCC is above 1.5 V, the power-up
3-state circuit relinquishes control of the outputs to the OE pin. To ensure the
outputs remain 3-state, the OE pin should be tied to VCC via a pull-up resistor.
GTL1655
Philips Semiconductors
16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion
2. Features
■ Combination of D-type latches and D-type flip-flops for transceiver operation in
clocked, latched or transparent mode
■ Logic level translation between LVTTL and GTL/GTL+ signals
■ HIGH-drive LOW-output-impedance (100 mA/12 Ω) on Port B
■ Configurable rise and fall times on Port B
■ Supports live insertion (Ioff, Power-up 3-state, and BIAS VCC)
■ Bus Hold on Port A inputs
■ Over voltage tolerance on Port A
■ Minimized switching noise through use of distributed VCC and GND pins
■ Available in TSSOP64 package
■ Industrial temperature range (−40 °C to +85 °C)
■ ESD protection
◆ HBM EIA/JESD22-A114-A exceeds 2000 V
◆ CDM EIA/JESD22-C101 exceeds 1000 V
■ Latch-up EIA/JEDS78 exceeds 200 mA
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tPLH
propagation delay, nAn to nBn
VCC = 3.3 V; VERC = GND;
VTT = 1.5 V; VREF = 1 V
-
3.9
-
ns
VCC = 3.3 V; VERC = GND;
VTT = 1.5 V; VREF = 1 V
-
4.4
-
ns
propagation delay, nBn to nAn
VCC = 3.3 V
-
2.6
-
ns
propagation delay, nAn to nBn
VCC = 3.3 V; VERC = GND;
VTT = 1.5 V; VREF = 1 V
-
3.1
-
ns
VCC = 3.3 V; VERC = GND;
VTT = 1.5 V; VREF = 1 V
-
2.7
-
ns
propagation delay, nBn to nAn
VCC = 3.3 V
-
4.2
-
ns
Ci
input capacitance (control pins)
Vi = VCC or GND
-
3
-
pF
CI/O
I/O capacitance, Port A
Vi = VCC or GND
-
7
-
pF
I/O capacitance, Port B
Vi = VCC or GND
-
8
-
pF
tPHL
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12936
Product data
Rev. 01 — 11 May 2004
2 of 23
GTL1655
Philips Semiconductors
16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion
4. Ordering information
Table 2:
Ordering information
Type number
Package
Name
Description
Version
GTL1655DGG TSSOP64 plastic thin shrink small outline package; 64 leads;
body width 6.1 mm
SOT646-1
Standard packing quantities and other packaging data are available at
www.philipslogic.com/packaging.
4.1 Ordering options
Table 3:
Part marking
Type number
Topside mark
Temperature range
GTL1655DGG
GTL1655DGG
Tamb = −40 °C to +85 °C
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12936
Product data
Rev. 01 — 11 May 2004
3 of 23
GTL1655
Philips Semiconductors
16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion
5. Pinning information
5.1 Pinning
1OEAB
1
64 CP
1OEBA
2
63 1LEAB
VCC
3
62 1LEBA
1A1
4
GND
5
61 VERC
60 GND
1A2
6
59 1B1
1A3
7
58 1B2
GND
8
57 GND
1A4
9
56 1B3
GND 10
55 1B4
1A5 11
54 1B5
GND 12
53 GND
1A6 13
52 1B6
1A7 14
51 1B7
VCC 15
50 VCC
49 1B8
1A8 16
2A1 17
GTL1655DGG
48 2B1
GND 18
47 GND
2A2 19
46 2B2
2A3 20
45 2B3
GND 21
44 GND
2A4 22
43 2B4
2A5 23
42 2B5
GND 24
2A6 25
41 VREF
40 2B6
GND 26
39 GND
2A7 27
38 2B7
VCC 28
37 2B8
2A8 29
36 BIAS_VCC
35 2LEAB
GND 30
2OEAB 31
34 2LEBA
2OEBA 32
33 OE
002aaa763
Fig 1. TSSOP64 pin configuration.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12936
Product data
Rev. 01 — 11 May 2004
4 of 23
GTL1655
Philips Semiconductors
16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion
5.2 Pin description
Table 4:
Pin description
Symbol
Pin
Description
1OEAB
1
output enable 1A-to-1B (active-LOW)
1OEBA
2
output enable 1B-to-1A (active-LOW)
VCC
3, 15, 28, 50
DC supply voltage
1A1 to 1A8
4, 6, 7, 9, 11, 13, data inputs/outputs port 1A
14, 16
GND
5, 8, 10, 12, 18,
21, 24, 26, 30,
39, 44, 47, 53,
57, 60
ground (0 V)
2A1 to 2A8
17, 19, 20, 22,
23, 25, 27, 29
data inputs/outputs port 2A
2OEAB
31
output enable 2A-to-2B (active-LOW)
2OEBA
32
output enable 2B-to-2A (active-LOW)
OE
33
output enable, all I/O pins (active-LOW)
2LEBA
34
latch enable 2B-to-2A
2LEAB
35
latch enable 2A-to-2B
BIAS_VCC
36
bias supply voltage
2B8 to 2B1
37, 38, 40, 42,
43, 45, 46, 48
data inputs/outputs port 2B
VREF
41
reference voltage
1B8 to 1B1
49, 51, 52, 54,
55, 56, 58, 59
data inputs/outputs port 1B
VERC
61
edge-rate control voltage Port B
1LEBA
62
latch enable 2B-to-2A
1LEAB
63
latch enable 1A-to-1B
CP
64
clock input
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12936
Product data
Rev. 01 — 11 May 2004
5 of 23
GTL1655
Philips Semiconductors
16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion
6. Functional description
VREF
VERC
CP
1LEAB
1LEBA
1OEBA
1OEAB
OE
41
61
64
63
62
2
1
33
1D
59
C1
1A1
4
1B1
CP
1D
C1
CP
TO 7 OTHER CHANNELS
002aaa764
Fig 2. Logic diagram.
VREF
VERC
CP
2LEAB
2LEBA
2OEBA
2OEAB
OE
41
61
64
35
34
32
31
33
1D
C1
2A1
17
48
2B1
CP
1D
C1
CP
TO 7 OTHER CHANNELS
002aaa765
Fig 3. Logic diagram.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12936
Product data
Rev. 01 — 11 May 2004
6 of 23
GTL1655
Philips Semiconductors
16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion
6.1 Function table
Table 5:
Function table
See Table note [1].
Inputs
Output
Port A
Mode
OEAB
LEAB
CP
Port B
H
X
X
X
Z
isolation
L
H
X
L
L
transparent
L
H
X
H
H
transparent
L
L
↑
L
L
registered
L
L
↑
H
H
registered
L
L
H
X
B0[2]
previous state
L
L
L
X
B0[3]
previous state
Table 6:
Output Enable function table
See Table note [1].
Inputs
Outputs
OE
OEAB
OEBA
Port A
Port B
L
L
L
active
active
L
L
H
Z
active
L
H
L
active
Z
L
H
H
Z
Z
H
X
X
Z
Z
Table 7:
Port B edge-rate control (VERC) function table
See Table note [1].
Input VERC
Output port B edge-rate
Logic level
Nominal voltage
H
VCC
slow
L
GND
fast
[1]
[2]
[3]
A-to-B data flow is shown. B-to-A is similar, but uses OEBA, LEBA, and CP. It is not recommended to
set OEAB and OEBA LOW at the same time.
X — don’t care
H — HIGH voltage level
L — LOW voltage level
Z — high-impedance OFF-state
↑ — LOW-to-HIGH transition
Output level before the indicated steady-state input conditions were established, provided that CP
was HIGH before LEAB went LOW.
Output level before the indicated steady-state input conditions were established.
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9397 750 12936
Product data
Rev. 01 — 11 May 2004
7 of 23
GTL1655
Philips Semiconductors
16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion
7. Limiting values
Table 8:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). See Table note [1] and Table note [2]
Symbol
Parameter
VCC
DC supply voltage
BIAS VCC
BIAS supply voltage
IIK
input clamping diode current
Vi < 0 V
Vi
DC input voltage
port A
port B; VERC, VREF
DC output voltage
Vo
IOL(d)
DC LOW-level diode output current
IOH(d)
DC HIGH-level diode output current
Tstg
storage temperature
[1]
[2]
[3]
Conditions
Min
Max
Unit
−0.5
+4.6
V
−0.5
+4.6
V
-
−50
mA
[3]
−0.5
+7.0
V
[3]
−0.5
+4.6
V
output in HIGH or power-OFF state;
port A
−0.5
+7.0
V
output in HIGH or power-OFF state;
port B
−0.5
+4.6
V
port A
-
48
mA
port B
-
200
mA
port A
-
48
mA
−65
+150
°C
Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any conditions beyond those indicated under Section 8 “Recommended operating conditions” is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.
The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12936
Product data
Rev. 01 — 11 May 2004
8 of 23
GTL1655
Philips Semiconductors
16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion
8. Recommended operating conditions
Table 9:
Recommended operating conditions
Symbol
Parameter
BIAS VCC
DC supply voltage
VTT
termination voltage
VREF
Vi
VIH
VIL
GTL reference voltage
input voltage
HIGH-level input voltage
LOW-level input voltage
Conditions
Min
Max
Unit
3.0
3.6
V
GTL
1.14
1.26
V
GTL+
1.35
1.65
V
GTL
0.74
0.87
V
GTL+
0.87
1.10
V
port B
0
VTT
V
except port B
0
5.5
V
port B
VREF + 50 mV
-
V
except port B
2.0
-
V
VERC
VCC − 0.6
-
V
port B
-
VREF − 50 mV
V
except port B
-
0.8
V
VERC
-
0.6
V
|IIK|
input clamp current
-
18
mA
IOH
HIGH-level output current
port A
-
−24
mA
IOL
LOW-level output current
port A
-
24
mA
port B
-
100
mA
∆t/∆VCC
power-up ramp rate
200
-
µs/V
Tamb
operating ambient temperature
−40
85
°C
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9397 750 12936
Product data
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GTL1655
Philips Semiconductors
16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion
9. Static characteristics
Table 10: DC characteristics
Tamb = −40 °C to +85 °C; values otherwise stated VREF = 1 V; VTT = 1.5 V.
Min
Typ[1]
Max
Unit
VCC = 3.0 V; IIK = 19 mA
-
-
−1.2
V
port A
VCC = 3.0 V to 3.6 V;
IOH = −100 µA
VCC − 0.2 -
-
V
VCC = 3.0 V;
IOH = −12 mA
2.4
-
-
V
VCC = 3.0 V;
IOH = −24 mA
2.2
-
-
V
VCC = 3.0 to 3.6 V;
IOL = 100 µA
-
-
0.2
V
VCC = 3.0 V;
IOL = 12 mA
-
-
0.4
V
VCC = 3.0 V;
IOL = 24 mA
-
-
0.55
V
VCC = 3.0 V;
IOL = 40 mA
-
-
0.2
V
VCC = 3.0 V;
IOL = 80 mA
-
-
0.4
V
VCC = 3.0 V;
IOL = 100 mA
-
-
0.5
V
control pins
VCC = 3.6 V;
Vi = VCC or GND
-
-
± 10
µA
port B
VCC = 3.6 V;
Vi = VTT or GND
-
-
± 10
µA
port A +
control pin
VCC = 0 V;
Vo = 0 V to 3.6 V
-
-
± 100
µA
port B
VCC = 0 V;
Vo = 0 V to 1.5 V
-
-
± 300
µA
port A
VCC = 3.0 V;
Vi = 0.8 V
75
-
-
µA
VCC = 3.0 V;
Vi = 2.0 V
−75
-
-
µA
-
-
± 500
µA
Symbol
Parameter
Conditions
VIK
input clamp voltage
VOH
VOL
HIGH-level output
voltage
LOW-level output
voltage
port A
port B
Ii
Ioff
IHOLD
input leakage current
output OFF current
bus hold current,
A outputs
[2]
overdrive current
port A
VCC = 3.6 V;
Vi = 0 V to VCC
IOZH
HIGH OFF-state output
current
port B
VCC = 3.6 V;
Vo = 1.5 V
-
-
10
µA
IOZL
LOW OFF-state
output current
port B
VCC = 3.6 V;
Vo = 0.4 V
-
-
−10
µA
IOZ
OFF-state output
current
port A
VCC = 3.6 V;
Vo = VCC or GND
-
-
10
µA
IOZPU
power-up 3-state output
current
VCC = 0 to 3.6 V; Vo = 0.5 V to 3 V;
OE = LOW
-
-
± 50
µA
IOZPD
power-down 3-state
output current
VCC = 3.6 to 0 V; Vo = 0.5 V to 3 V;
OE = LOW
-
-
± 50
µA
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12936
Product data
[3]
Rev. 01 — 11 May 2004
10 of 23
GTL1655
Philips Semiconductors
16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion
Table 10: DC characteristics…continued
Tamb = −40 °C to +85 °C; values otherwise stated VREF = 1 V; VTT = 1.5 V.
Min
Typ[1]
Max
Unit
VCC = 3.6 V;
Vi = VCC or GND;
Io = 0 mA
-
-
45
mA
outputs
LOW
VCC = 3.6 V;
Vi = VCC or GND;
Io = 0 mA
-
-
45
mA
disabled
VCC = 3.6 V;
Vi = VCC or GND;
Io = 0 mA
-
-
45
mA
-
0.1
-
mA
Symbol
Parameter
Conditions
ICC
quiescent supply
current
outputs
HIGH
∆ICC
additional quiescent
supply current per input
pin; except port B
VCC = 3.6 V; one input at
VCC − 0.6 V; port A or control inputs
at VCC or GN D
Ci
input capacitance
control pins
VCC = 3.6 V;
Vi = VCC or 0
-
3
5
pF
CIO
I/O capacitance
port A
VCC = 3.6 V;
Vi = VCC or 0
-
7
8
pF
port B
VCC = 3.6 V;
Vi = VCC or 0
-
8
10
pF
[1]
[2]
[3]
[4]
[4]
All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
For I/O ports, this parameter IOZ includes the input leakage current.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
Table 11: Live insertion characteristics
Tamb = −40 °C to +85 °C
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ICC
(BIAS VCC)
supply current
VCC = 0 V to 3.0 V; V (port B) = 0 to 1.2 V;
Vi (BIAS VCC) = 3.0 V to 3.6 V
-
-
5
mA
VCC = 3.0 V to 3.6 V;
V (port B) = 0 to 1.2 V;
Vi (BIAS VCC) = 3.0 V to 3.6 V
-
-
10
µA
Vo
output voltage
port B
VCC = 0 V;
Vi (BIAS VCC) = 3.3 V
1
-
1.2
V
Io
output current
port B
VCC = 0 V; V (port B) = 0.4 V;
Vi (BIAS VCC) = 3 V to 3.6 V
−1
-
-
µA
VCC = 0 V to 3.6 V; OE = 3.3 V;
V (port B) = 0 V to 1.5 V
-
-
300
µA
VCC = 0 V to 1.5 V;
OE = 0 V to 3.3 V;
V (port B) = 0 V to 1.5 V
-
-
300
µA
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12936
Product data
Rev. 01 — 11 May 2004
11 of 23
GTL1655
Philips Semiconductors
16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion
10. Dynamic characteristics
Table 12: Timing requirements over recommended supply voltage
VTT = 1.2 V; VREF = 0.8 V and VERC = VCC or GND for GTL (unless otherwise noted; see Figures 15 and 16).
Tamb = −40 °C to +85 °C.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tW
pulse duration
CP HIGH or LOW; see Figures 4 and 5
3.0
-
-
ns
LE HIGH; see Figures 6 and 7
3.0
-
-
ns
data before CP↑; see Figures 4 and 5
2.7
-
-
ns
data before LE↓; see Figures 6 and 7
2.8
-
-
ns
data after CP↑; see Figures 4 and 5
0.4
-
-
ns
data after LE↓; see Figures 6 and 7
1.2
-
-
ns
Min
Typ
Max
Unit
tsu
th
set-up time
hold time
Table 13: Port A to Port B switching
VTT = 1.2 V; VREF = 0.8 V and VERC = VCC or GND for GTL (see Figure 16).
Tamb = −40 °C to +85 °C.
Symbol
Parameter
Conditions
tPLH
A to B
OEAB = OE = 0 V;
LEAB = 3 V
VERC = VCC;
see Figure 10
3.1
5.3
6.2
ns
2.2
3.8
6.2
ns
OEAB = OE = 0 V;
LEAB = 0 V
VERC = VCC;
see Figure 4
3.4
5.9
7.2
ns
2.4
4.1
6.0
ns
OEAB = OE = 0 V;
CP = 0 or 3 V
VERC = VCC;
see Figure 8
3.3
5.7
7.0
ns
2.6
4.6
6.8
ns
LEAB = 3.0 V;
Port A = 0 V
VERC = VCC;
see Figure 12
2.7
5.3
6.5
ns
2.5
3.9
6.4
ns
OEAB = OE = 0 V;
LEAB = 3 V
VERC = GND;
see Figure 10
2.3
4.4
5.3
ns
1.7
2.7
4.4
ns
OEAB = OE = 0 V;
LEAB = 0 V
VERC = GND;
see Figure 4
2.7
5.2
6.1
ns
1.8
3.7
5.3
ns
OEAB = OE = 0 V;
CP = 0 or 3 V
VERC = GND;
see Figure 8
2.5
4.8
6.5
ns
2.0
3.6
5.3
ns
LEAB = 3.0 V;
Port A = 0 V
VERC = GND;
see Figure 12
2.0
4.8
6.2
ns
2.0
3.1
4.9
ns
0.6 V to 1.0 V
VERC = VCC
-
-
1
V/ns
VERC = GND
-
-
1
V/ns
-
-
1
ns
tPHL
tPLH
CP to B
tPHL
tPLH
LEAB to B
tPHL
tPLH
OEAB or OE to B
tPHL
tPLH
A to B
tPHL
tPLH
CP to B
tPHL
tPLH
LEAB to B
tPHL
tPLH
OEAB or OE to B
tPHL
∆V/∆t
tsk(o)
output slew rate
output edge skew
measured at VREF
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Product data
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16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion
Table 14: Port B to Port A switching
VTT = 1.2 V; VREF = 0.8 V for GTL (see Figure 15).
Tamb = −40 °C to +85 °C.
Symbol
Parameter
fmax
maximum
frequency
tPLH
B to A
tPHL
tPLH
CP to A
tPHL
tPLH
LEBA to A
Conditions
OEBA = OE = 0 V;
LEBA = 3 V
see Figure 11
OEBA = OE = 0 V;
LEBA = 0 V
see Figure 5
OEBA = OE = 0 V
see Figure 9
tPHL
tPZL
OEBA or OE to A
tPLZ
tPZH
tPHZ
tsk(o)
output edge skew
LEBA = 3.0 V;
Port B = 0 V
see Figure 13
LEBA = 3 V;
Port B = VTT
see Figure 14
measured at 1.5 V
Typ
Max
Unit
-
-
MHz
1.8
2.6
4.9
ns
2.3
4.2
5.3
ns
1.5
3.1
4.4
ns
1.5
3.7
4.6
ns
1.3
2.7
4.0
ns
1.4
3.1
3.9
ns
1.3
3.1
5.1
ns
1.7
2.8
6.1
ns
1.3
3.3
5.1
ns
1.7
3.3
6.1
ns
-
-
1
ns
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12936
Product data
Min
160
Rev. 01 — 11 May 2004
13 of 23
GTL1655
Philips Semiconductors
16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion
Table 15: Timing requirements over recommended supply voltage
VTT = 1.5 V; VREF = 1 V and VERC = VCC or GND for GTL+ (unless otherwise noted).
Tamb = −40 °C to +85 °C.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tW
pulse duration
CP HIGH or LOW; see Figures 4 and 5
3.0
-
-
ns
LE HIGH; see Figures 6 and 7
3.0
-
-
ns
tsu
set-up time
data before CP↑; see Figures 4 and 5
2.7
-
-
ns
data before LE↓; see Figures 6 and 7
2.8
-
-
ns
th
hold time
data after CP↑; see Figures 4 and 5
0.4
-
-
ns
data after LE↓; see Figures 6 and 7
1.2
-
-
ns
Min
Typ
Max
Unit
4.7
6.1
ns
Table 16: Port A to Port B switching
VTT = 1.5 V; VREF = 1 V and VERC = VCC or GND for GTL+ (see Figures 15 and 16).
Tamb = −40 °C to +85 °C.
Symbol
Parameter
Conditions
tPLH
A to B
OEAB = OE = 0 V;
LEAB = 3 V
VERC = VCC;
see Figure 10
3.0
2.3
4.4
6.5
ns
CP to B
OEAB = OE = 0 V;
LEAB = 0 V
VERC = VCC;
see Figure 4
3.3
5.3
7.0
ns
2.7
4.7
6.2
ns
LEAB to B
OEAB = OE = 0 V;
CP = 0 or 3 V
VERC = VCC;
see Figure 8
3.2
5.2
6.8
ns
2.8
5.2
7.1
ns
OEAB or OE to B
LEAB = 3.0 V;
Port A = 0 V
VERC = VCC;
see Figure 12
3.2
4.8
6.5
ns
2.6
4.6
6.6
ns
A to B
OEAB = OE = 0 V;
LEAB = 3 V
VERC = GND;
see Figure 10
2.3
3.9
5.2
ns
1.7
3.1
4.5
ns
CP to B
OEAB = OE = 0 V;
LEAB = 0 V
VERC = GND;
see Figure 4
2.5
4.8
6.0
ns
1.9
4.1
5.4
ns
LEAB to B
OEAB = OE = 0 V;
CP = 0 or 3 V
VERC = GND;
see Figure 8
2.5
4.3
6.5
ns
2.1
4.0
5.4
ns
OEAB or OE to B
LEAB = 3.0 V;
Port A = 0 V
VERC = GND;
see Figure 12
2.1
4.4
6.1
ns
2.0
3.4
5.0
ns
VERC = VCC
-
-
1
V/ns
VERC = GND
-
-
1
V/ns
-
-
1
ns
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
∆V/∆t
output slew rate
0.6 V to 1.3 V
tsk(o)
output edge skew
measured at VREF
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12936
Product data
Rev. 01 — 11 May 2004
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GTL1655
Philips Semiconductors
16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion
Table 17: Port B to Port A switching
VTT = 1.5 V; VREF = 1 V for GTL+ (see Figures 15 and 16).
Tamb = −40 °C to +85 °C.
Symbol
Parameter
fmax
maximum
frequency
tPLH
B to A
Conditions
tPHL
CP to A
tPLH
tPHL
LEBA to A
tPLH
OEBA = OE = 0 V;
LEBA = 3 V
see Figure 11
OEBA = OE = 0 V;
LEBA = 0 V
see Figure 5
OEBA = OE = 0 V
see Figure 9
tPHL
OEBA or OE to A
tPZL
tPLZ
tPZH
tPHZ
output edge skew
tsk(o)
LEBA = 3.0 V;
Port B = 0 V
see Figure 13
LEBA = 3 V;
Port B = VTT
see Figure 14
measured at 1.5 V
Min
Typ
Max
Unit
160
-
-
MHz
1.8
2.6
4.9
ns
2.3
4.2
5.3
ns
1.5
3.1
4.4
ns
1.5
3.7
4.6
ns
1.3
2.7
4.0
ns
1.4
3.1
3.9
ns
1.3
3.1
5.1
ns
1.7
2.8
6.1
ns
1.3
3.3
5.1
ns
1.7
3.3
6.1
ns
-
-
1
ns
10.1 AC waveforms
Port A
input
3.0 V
1.5 V
tsu
1.5 V
1.5 V
Port B
input
0V
tsu
th
1.5 V
VTT
VREF
tsu
th
VREF
VREF
0V
tsu
th
VREF
th
3.0 V
CP
input
1.5 V
1.5 V
1.5 V
0V
tW
tW
tPLH
Port B
output
3.0 V
CP
input
1.5 V
VREF
VREF
tW
tPLH
Port A
output
1.5 V
0V
tW
tPHL
VTT
1.5 V
tPHL
VOH
1.5 V
1.5 V
VOL
VOL
002aaa766
002aaa767
Test condition: OEAB = OE = 0 V
Test condition: OEAB = OE = 0 V; LEBA = 0 V
Fig 4. CP to B timing.
Port A
input
Fig 5. CP to A timing.
3.0 V
1.5 V
tsu
1.5 V
1.5 V
tsu
th
1.5 V
0V
1.5 V
1.5 V
1.5 V
VTT
VREF
tsu
th
3.0 V
LEAB
input
Port B
input
VREF
VREF
tsu
th
VREF
0V
th
3.0 V
LEBA
input
1.5 V
1.5 V
1.5 V
0V
0V
tW
tW
002aaa768
Test condition: OEAB = OE = 0 V
Test condition: OEAB = OE = 0 V
Fig 6. LEAB set-up and hold times.
Fig 7. LEBA set-up and hold times.
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9397 750 12936
Product data
002aaa769
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GTL1655
Philips Semiconductors
16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion
3.0 V
LEAB
input
1.5 V
1.5 V
3.0 V
LEBA
input
1.5 V
1.5 V
1.5 V
1.5 V
0V
tPLH
Port B
output
tW
0V
tPHL
VTT
VREF
VREF
tW
tPLH
tPHL
VOH
Port A
output
1.5 V
1.5 V
VOL
VOL
002aaa770
002aaa771
Test condition: OEAB = OE = 0 V; CP = 0 V or 3 V
Test condition: OEAB = OE = 0 V; CP = 0 V or 3 V
Fig 8. LEAB to B propagation delay.
Fig 9. LEBA to A propagation delay.
3.0 V
Port A
input
1.5 V
VTT
Port B
input
1.5 V
VREF
VREF
0V
0V
tPLH
Port B
input
tPHL
tPLH
VTT
VOH
Port A
input
VREF
VREF
tPHL
1.5 V
1.5 V
VOL
VOL
002aaa772
002aaa773
Test conditions: OEAB = OE = 0 V; LEAB = 3 V
Test conditions: OEBA = OE = 0 V; LEBA = 3 V
Fig 10. A to B propagation delay.
OE or
OEAB
input
Fig 11. B to A propagation delay.
3.0 V
1.5 V
0V
tPHL
Port B
output
3.0 V
OE or
OEBA
input
1.5 V
1.5 V
0V
tPLH
tPZL
VTT
tPLZ
3.0 V
Port A
output
VREF
VREF
1.5 V
1.5 V
VOL
002aaa774
VOL + 0.3 V
Test conditions: LEAB = 3 V; Port A = 0 V
Test conditions: LEBA = 3 V; Port B = 0 V
Fig 12. OE or OEAB to B propagation delay.
Fig 13. OE or OEBA to A propagation delay.
OE or
OEBA
input
3.0 V
1.5 V
1.5 V
0V
tPZH
Port A
output
VOL
002aaa775
1.5 V
tPHZ
VOH
VOH − 0.3 V
0V
002aaa776
Test conditions: LEBA = 3 V; Port B = VTT
Fig 14. OE or OEBA to A propagation delay.
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9397 750 12936
Product data
Rev. 01 — 11 May 2004
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GTL1655
Philips Semiconductors
16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion
11. Test information
6V
open
GND
S1
RL
500 Ω
VCC
PULSE
GENERATOR
VI
VO
D.U.T.
CL
50 pF
RT
RL
500 Ω
002aaa777
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance ZO of the pulse
generator.
Fig 15. Load circuitry for Port A output switching times.
VTT
VCC
PULSE
GENERATOR
VI
RL
12.5 Ω
VO
D.U.T.
CL
30 pF
RT
002aaa778
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance ZO of the pulse
generator.
Fig 16. Load circuitry for Port B output switching times.
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9397 750 12936
Product data
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GTL1655
Philips Semiconductors
16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion
12. Package outline
TSSOP64: plastic thin shrink small outline package; 64 leads; body width 6.1 mm
SOT646-1
E
D
A
X
c
HE
y
v M A
Z
64
33
A2
(A 3)
A1
pin 1 index
A
θ
Lp
L
1
32
bp
e
detail X
w M
2.5
0
5 mm
scale
DIMENSIONS (mm are the original dimensions).
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
v
w
y
Z
θ
mm
1.2
0.15
0.05
1.05
0.85
0.25
0.27
0.17
0.2
0.1
17.1
16.9
6.2
6.0
0.5
8.3
7.9
1
0.75
0.45
0.2
0.08
0.1
0.89
0.61
8
0o
o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT646-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
00-08-21
03-02-18
MO-153
Fig 17. TSSOP64 package outline (SOT646-1).
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Product data
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16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion
13. Soldering
13.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account
of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit
Packages (document order number 9398 652 90011).
There is no soldering method that is ideal for all surface mount IC packages. Wave
soldering can still be used for certain surface mount ICs, but it is not suitable for fine
pitch SMDs. In these situations reflow soldering is recommended. In these situations
reflow soldering is recommended.
13.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling
or pressure-syringe dispensing before package placement. Driven by legislation and
environmental forces the worldwide use of lead-free solder pastes is increasing.
Several methods exist for reflowing; for example, convection or convection/infrared
heating in a conveyor type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending on heating method.
Typical reflow peak temperatures range from 215 to 270 °C depending on solder
paste material. The top-surface temperature of the packages should preferably be
kept:
• below 225 °C (SnPb process) or below 245 °C (Pb-free process)
– for all BGA, HTSSON..T and SSOP..T packages
– for packages with a thickness ≥ 2.5 mm
– for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called
thick/large packages.
• below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with
a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages.
Moisture sensitivity precautions, as indicated on packing, must be respected at all
times.
13.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging
and non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically
developed.
If wave soldering is used the following conditions must be observed for optimal
results:
• Use a double-wave soldering method comprising a turbulent wave with high
upward pressure followed by a smooth laminar wave.
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Product data
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16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be
parallel to the transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the
transport direction of the printed-circuit board.
The footprint must incorporate solder thieves at the downstream end.
• For packages with leads on four sides, the footprint must be placed at a 45° angle
to the transport direction of the printed-circuit board. The footprint must
incorporate solder thieves downstream and at the side corners.
During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or
265 °C, depending on solder material applied, SnPb or Pb-free respectively.
A mildly-activated flux will eliminate the need for removal of corrosive residues in
most applications.
13.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low
voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time
must be limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within
2 to 5 seconds between 270 and 320 °C.
13.5 Package related soldering information
Table 18:
Suitability of surface mount IC packages for wave and reflow soldering
methods
Package[1]
Soldering method
BGA, HTSSON..T[3], LBGA, LFBGA, SQFP,
SSOP..T[3], TFBGA, USON, VFBGA
Reflow[2]
not suitable
suitable
DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, not suitable[4]
HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,
HVSON, SMS
suitable
PLCC[5], SO, SOJ
suitable
suitable
LQFP, QFP, TQFP
not recommended[5][6]
suitable
recommended[7]
SSOP, TSSOP, VSO, VSSOP
not
CWQCCN..L[8],
not suitable
[1]
[2]
PMFP[9],
WQCCN..L[8]
suitable
not suitable
For more detailed information on the BGA packages refer to the (LF)BGA Application Note
(AN01026); order a copy from your Philips Semiconductors sales office.
All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal
or external package cracks may occur due to vaporization of the moisture in them (the so called
popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated
Circuit Packages; Section: Packing Methods.
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9397 750 12936
Product data
Wave
Rev. 01 — 11 May 2004
20 of 23
GTL1655
Philips Semiconductors
16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion
[3]
[4]
[5]
[6]
[7]
[8]
[9]
These transparent plastic packages are extremely sensitive to reflow soldering conditions and must
on no account be processed through more than one soldering cycle or subjected to infrared reflow
soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow
oven. The package body peak temperature must be kept as low as possible.
These packages are not suitable for wave soldering. On versions with the heatsink on the bottom
side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with
the heatsink on the top side, the solder might be deposited on the heatsink surface.
If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave
direction. The package footprint must incorporate solder thieves downstream and at the side corners.
Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it
is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
Wave soldering is suitable for SSOP, TSSOP, VSO and VSOP packages with a pitch (e) equal to or
larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than
0.5 mm.
Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered
pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex
foil by using a hot bar soldering process. The appropriate soldering profile can be provided on
request.
Hot bar soldering or manual soldering is suitable for PMFP packages.
14. Revision history
Table 19:
Revision history
Rev Date
01
20040511
CPCN
Description
-
Product data (9397 750 12936).
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9397 750 12936
Product data
Rev. 01 — 11 May 2004
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16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion
15. Data sheet status
Level
Data sheet status[1]
Product status[2][3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
Please consult the most recently issued data sheet before initiating or completing a design.
[2]
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
16. Definitions
17. Disclaimers
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Contact information
For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: [email protected]
Product data
Fax: +31 40 27 24825
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Rev. 01 — 11 May 2004
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16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion
Contents
1
2
3
4
4.1
5
5.1
5.2
6
6.1
7
8
9
10
10.1
11
12
13
13.1
13.2
13.3
13.4
13.5
14
15
16
17
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional description . . . . . . . . . . . . . . . . . . . 6
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8
Recommended operating conditions. . . . . . . . 9
Static characteristics. . . . . . . . . . . . . . . . . . . . 10
Dynamic characteristics . . . . . . . . . . . . . . . . . 12
AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 15
Test information . . . . . . . . . . . . . . . . . . . . . . . . 17
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Introduction to soldering surface mount
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 19
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 19
Manual soldering . . . . . . . . . . . . . . . . . . . . . . 20
Package related soldering information . . . . . . 20
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 21
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 22
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
© Koninklijke Philips Electronics N.V. 2004.
Printed in the U.S.A.
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 11 May 2004
Document order number: 9397 750 12936
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