Data Sheet

GTL2005
Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched
translator
Rev. 07 — 3 February 2009
Product data sheet
1. General description
The GTL2005 is a quad translating transceiver designed for 3.3 V system interface with a
GTL/GTL+ bus.
The direction pin (DIR) allows the part to function as either a GTL-to-TTL sampling
receiver or as a TTL-to-GTL interface.
The GTL2005 LVTTL interface is tolerant up to 5.5 V allowing direct access to TTL or 5 V
CMOS outputs.
The GTL2005 Vref linearity degrades below 0.8 V (see Section 10.1). If the application
allows, use the GTL2014, otherwise more closely review noise margins.
fast tPD
GTL2005
GTL2014
slow tPD
GTL−
GTL
GTL+
002aab378
Fig 1.
GTL2005/GTL2014 positioning
2. Features
n Operates as a quad GTL/GTL+ sampling receiver or as a LVTTL/TTL to GTL/GTL+
driver
n Quad bidirectional bus interface
n 3.0 V to 3.6 V operation with 5 V tolerant LVTTL I/O
n Live insertion/extraction permitted
n Latch-up protection exceeds 500 mA per JESD78
n ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per
JESD22-A115, and 1000 V CDM per JESD22-CC101
n Package offered: TSSOP14
GTL2005
NXP Semiconductors
Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator
3. Quick reference data
Table 1.
Quick reference data
VCC = 3.3 V ± 0.3 V
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
Ci
input capacitance
control inputs;
VI = 3.0 V or 0 V
-
2.3
3.5
pF
Cio
input/output capacitance
A port;
VO = VTT or 0 V
-
3.4
5.0
pF
B port;
VO = 3.0 V or 0 V
-
6.0
7.0
pF
-
2.1
2.3
ns
-
1.9
2.6
ns
-
4.1
5.9
ns
-
4.4
5.9
ns
GTL; Vref = 0.8 V
tPLH
propagation delay, Bn to An see Figure 7
tPHL
tPLH
propagation delay, An to Bn see Figure 8
tPHL
[1]
All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
4. Ordering information
Table 2.
Ordering information
Tamb = −40 °C to +85 °C
Type number
GTL2005PW
Topside
mark
Package
Name
Description
Version
GTL2005
TSSOP14
plastic thin shrink small outline package;
14 leads; body width 4.4 mm
SOT402-1
GTL2005_7
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 07 — 3 February 2009
2 of 19
GTL2005
NXP Semiconductors
Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator
5. Functional diagram
GTL2005
A0
B0
A1
B1
A2
B2
A3
B3
002aab151
VREF
Fig 2.
DIR
Logic diagram of GTL2005
6. Pinning information
6.1 Pinning
DIR
1
14 VCC
A0
2
13 B0
A1
3
VREF
4
A2
5
10 B2
A3
6
9
B3
GND
7
8
GND
12 B1
GTL2005PW
11 GND
002aab150
Fig 3.
Pin configuration for TSSOP14
GTL2005_7
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 07 — 3 February 2009
3 of 19
GTL2005
NXP Semiconductors
Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator
6.2 Pin description
Table 3.
Pin description
Symbol
Pin
Description
DIR
1
direction control input
A0
2
data inputs/outputs (A side, GTL)
A1
3
A2
5
A3
6
B0
13
B1
12
B2
10
B3
9
VREF
4
GTL reference voltage
GND
7, 8, 11
ground (0 V)
VCC
14
positive supply voltage
data inputs/outputs (B side, TTL)
7. Functional description
Refer to Figure 2 “Logic diagram of GTL2005”.
7.1 Function table
Table 4.
Function table
H = HIGH voltage level; L = LOW voltage level.
Input
Input/output
DIR
B (TTL)
H
inputs
Bn = An
L
An = Bn
inputs
GTL2005_7
Product data sheet
A (GTL)
© NXP B.V. 2009. All rights reserved.
Rev. 07 — 3 February 2009
4 of 19
GTL2005
NXP Semiconductors
Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
VCC
DC supply voltage
IIK
VI
Unit
−0.5
+4.6
V
DC input diode current
VI < 0 V
-
−50
mA
DC input voltage
A port
−0.5[2]
+7.0
V
B port
−0.5[2]
+4.6
V
IOK
DC output diode current
VO < 0 V
-
−50
mA
VO
DC output voltage
output in OFF or
HIGH state; A port
−0.5[2]
+7.0
V
output in OFF or
HIGH state; B port
−0.5[2]
+4.6
V
current into any output in
the LOW state
B port
-
128
mA
A port
-
80
mA
IOH
current into any output in
the HIGH state
B port
-
−64
mA
Tstg
storage temperature range
−60
+150
°C
IOL
[3]
[1]
Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions beyond those indicated under
Section 9 “Recommended operating conditions” is not implied. Exposure to absolute-maximum-rated
conditions for extended periods may affect device reliability.
[2]
The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings
are observed.
[3]
The performance capability of a high-performance integrated circuit in conjunction with its thermal
environment can create junction temperatures which are detrimental to reliability. The maximum junction
temperature of this integrated circuit should not exceed 150 °C.
GTL2005_7
Product data sheet
Max
© NXP B.V. 2009. All rights reserved.
Rev. 07 — 3 February 2009
5 of 19
GTL2005
NXP Semiconductors
Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator
9. Recommended operating conditions
Table 6.
Operating conditions [1]
Symbol Parameter
Conditions
VCC
supply voltage
VTT
termination voltage
reference voltage
Vref
input voltage
VI
HIGH-level input voltage
VIH
LOW-level input voltage
VIL
Min
Typ
Max
Unit
3.0
3.3
3.6
V
GTL−
0.85
0.9
0.95
V
GTL
1.14
1.2
1.26
V
GTL+
1.35
1.5
1.65
V
0.5
2⁄ V
3 TT
1.8
V
GTL−
0.5
0.6
0.63
V
GTL
0.76
0.8
0.84
V
GTL+
0.87
1.0
1.10
V
A port
0
VTT
3.6
V
except A port
0
3.3
5.5
V
A port
[3]
-
-
V
except A port
2
-
-
V
V
V
overall
A port
-
-
[3]
except A port
-
-
0.8
IOH
HIGH-level output current B port
-
-
−12
mA
IOL
LOW-level output current
A port
-
-
40
mA
B port
-
-
12
mA
operating in
free-air
−40
-
+85
°C
Tamb
ambient temperature
[1]
Unused inputs must be held HIGH or LOW to prevent them from floating.
[2]
Vref is normally 2⁄3VTT, but based upon application and noise margin requirements can be set anywhere
within this range and does not need to follow GTL-/GTL/GTL+ specification.
[3]
Nominally ±50 mV around Vref. See Figure 4, Figure 5, and Figure 6 for actual performance versus Vref,
VCC, and temperature.
GTL2005_7
Product data sheet
[2]
© NXP B.V. 2009. All rights reserved.
Rev. 07 — 3 February 2009
6 of 19
GTL2005
NXP Semiconductors
Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator
10. Static characteristics
Table 7.
Static characteristics
Recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = −40 °C to +85 °C.
Symbol
VOH
Parameter
HIGH-level output
voltage
LOW-level output
voltage
VOL
input current
II
Min
Typ[1]
Max
Unit
B port; VCC = 3.0 V to 3.6 V;
IOH = −100 µA
[2]
VCC − 0.2
-
-
V
B port; VCC = 3.0 V;
IOH = −12 mA
[2]
2.0
-
-
V
A port; VCC = 3.0 V; IOL = 40 mA
[2]
-
-
0.4
V
B port; VCC = 3.0 V; IOL = 4 mA
[2]
-
-
0.4
V
B port; VCC = 3.0 V; IOL = 8 mA
[2]
-
-
0.55
V
B port; VCC = 3.0 V; IOL = 12 mA
[2]
-
-
0.8
V
control inputs; VCC = 3.6 V;
VI = VCC or GND
-
-
±1
µA
A port; VCC = 3.6 V;
VI = VTT or GND
-
-
±1
µA
B port; VCC = 0 V or 3.6 V;
VI = 5.5 V
-
-
10
µA
B port; VCC = 3.6 V; VI = VCC
-
-
±1
µA
B port; VCC = 3.6 V; VI = 0 V
-
-
−5
µA
Conditions
IOFF
output OFF current
A port; VCC = 0 V;
VI or VO = 0 V to 4.5 V
-
-
±100
µA
IEX
high contention over
voltage leakage
current
B port; VCC = 3.0 V; VO = 5.5 V
-
50
125
µA
ICC
supply current
A or B port; VCC = 3.6 V;
VI = VCC or GND; IO = 0 mA
-
-
3
mA
∆ICC[3]
additional supply
current per input
B port or control inputs;
VCC = 3.6 V; VI = VCC − 0.6 V
-
-
500
µA
Ci
input capacitance
control inputs; VI = 3.0 V or 0 V
-
2.3
3.5
pF
Cio
input/output
capacitance
A port; VO = VTT or 0 V
-
3.4
5.0
pF
B port; VO = 3.0 V or 0 V
-
6.0
7.0
pF
[1]
All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
[2]
The input and output voltage ratings my be exceeded if the input and output current ratings are observed.
[3]
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
GTL2005_7
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 07 — 3 February 2009
7 of 19
GTL2005
NXP Semiconductors
Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator
10.1 Performance curves
002aab152
1200
VTH+
and
VTH−
(mV)
1000
002aab153
1200
VTH+
and
VTH−
(mV)
1000
VTH+
VTH+
VTH−
800
Vref
800
VTH−
600
Vref
600
400
0.5
0.6
0.7
0.9
0.8
400
0.5
1.0
Vref (V)
a. VCC = 3.0 V
0.6
0.7
0.8
0.9
1.0
Vref (V)
b. VCC = 3.3 V
002aab154
1200
VTH+
and
VTH−
(mV)
1000
VTH+
800
Vref
VTH−
600
400
0.5
0.6
0.7
0.8
0.9
1.0
Vref (V)
c. VCC = 3.6 V
Fig 4.
GTL VTH+ and VTH− versus Vref; Tamb = −40 °C
GTL2005_7
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 07 — 3 February 2009
8 of 19
GTL2005
NXP Semiconductors
Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator
002aab155
1200
VTH+
and
VTH−
(mV)
1000
002aab156
1200
VTH+
and
VTH−
(mV)
1000
VTH+
VTH+
Vref
Vref
VTH−
800
800
600
600
400
0.5
0.6
0.7
0.9
0.8
400
0.5
1.0
Vref (V)
a. VCC = 3.0 V
0.6
0.7
VTH−
0.8
0.9
1.0
Vref (V)
b. VCC = 3.3 V
002aab157
1200
VTH+
and
VTH−
(mV)
1000
VTH+
Vref
VTH−
800
600
400
0.5
0.6
0.7
0.8
0.9
1.0
Vref (V)
c. VCC = 3.6 V
Fig 5.
GTL VTH+ and VTH− versus Vref; Tamb = +25 °C
GTL2005_7
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 07 — 3 February 2009
9 of 19
GTL2005
NXP Semiconductors
Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator
002aab158
1200
VTH+
and
VTH−
(mV)
1000
002aab159
1200
VTH+
and
VTH−
(mV)
1000
VTH+
VTH−
VTH+
800
800
VTH−
Vref
600
600
Vref
400
0.5
0.6
0.7
0.9
0.8
400
0.5
1.0
Vref (V)
a. VCC = 3.0 V
0.6
0.7
0.8
0.9
1.0
Vref (V)
b. VCC = 3.3 V
002aab160
1200
VTH+
and
VTH−
(mV)
1000
VTH+
800
VTH−
Vref
600
400
0.5
0.6
0.7
0.8
0.9
1.0
Vref (V)
c. VCC = 3.6 V
Fig 6.
GTL VTH+ and VTH− versus Vref; Tamb = +85 °C
GTL2005_7
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 07 — 3 February 2009
10 of 19
GTL2005
NXP Semiconductors
Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator
11. Dynamic characteristics
Table 8.
Dynamic characteristics
VCC = 3.3 V ± 0.3 V
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
see Figure 7
-
2.1
2.3
ns
-
1.9
2.6
ns
-
4.1
5.9
ns
-
4.4
5.9
ns
-
2.1
2.3
ns
-
1.9
2.6
ns
-
4.1
5.9
ns
-
4.4
5.9
ns
-
2.1
2.3
ns
-
1.9
2.6
ns
-
4.2
5.7
ns
-
3.8
5.4
ns
GTL−; Vref = 0.6 V
propagation delay, Bn to An
tPLH
tPHL
propagation delay, An to Bn
tPLH
see Figure 8
tPHL
GTL; Vref = 0.8 V
propagation delay, Bn to An
tPLH
see Figure 7
tPHL
propagation delay, An to Bn
tPLH
see Figure 8
tPHL
GTL+; Vref = 1.0 V
propagation delay, Bn to An
tPLH
see Figure 7
tPHL
propagation delay, An to Bn
tPLH
see Figure 8
tPHL
[1]
All typical values are at VCC = 3.3 V and Tamb = 25 °C.
11.1 Waveforms
VM = 1.5 V at VCC ≥ 3.0 V; VM = VCC/2 at VCC ≤ 2.7 V for B ports and control pins;
VM = Vref for A ports.
3.0 V
input
1.5 V
1.5 V
0V
tPLH
tp
tPHL
VOH
3.0 V
VM
output
VM
Vref
Vref
VOL
0V
002aab141
002aab140
VM = 1.5 V for B port and Vref for A port
a. Pulse duration
Fig 7.
b. Propagation delay times
Voltage waveforms
GTL2005_7
Product data sheet
B port to A port
© NXP B.V. 2009. All rights reserved.
Rev. 07 — 3 February 2009
11 of 19
GTL2005
NXP Semiconductors
Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator
3.0 V
input
Vref
Vref
0V
tPLH
tPHL
VOH
1.5 V
output
1.5 V
VOL
002aab163
PRR ≤ 10 MHz; Zo = 50 Ω; tr ≤ 2.5 ns; tf ≤ 2.5 ns
Fig 8.
Propagation delay, An to Bn
12. Test information
VCC
PULSE
GENERATOR
VI
VO
DUT
RL
500 Ω
CL
50 pF
RT
002aab006
Fig 9.
Load circuitry for switching times
VTT
VCC
PULSE
GENERATOR
VI
25 Ω
VO
DUT
CL
30 pF
RT
002aab143
Fig 10. Load circuit for A (GTL) outputs
RL — Load resistor
CL — Load capacitance; includes jig and probe capacitance
RT — Termination resistance; should be equal to Zo of pulse generators.
GTL2005_7
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 07 — 3 February 2009
12 of 19
GTL2005
NXP Semiconductors
Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator
13. Package outline
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
E
D
A
X
c
y
HE
v M A
Z
8
14
Q
(A 3)
A2
A
A1
pin 1 index
θ
Lp
L
1
7
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.72
0.38
8
o
0
o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT402-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
MO-153
Fig 11. Package outline SOT402-1 (TSSOP14)
GTL2005_7
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 07 — 3 February 2009
13 of 19
GTL2005
NXP Semiconductors
Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator
14. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
GTL2005_7
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 07 — 3 February 2009
14 of 19
GTL2005
NXP Semiconductors
Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator
14.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 12) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 9 and 10
Table 9.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 10.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 12.
GTL2005_7
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 07 — 3 February 2009
15 of 19
GTL2005
NXP Semiconductors
Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 12. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
15. Abbreviations
Table 11.
Abbreviations
Acronym
Description
CDM
Charged-Device Model
CMOS
Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
GTL
Gunning Transceiver Logic
HBM
Human Body Model
I/O
Input/Output
LVTTL
Low Voltage Transistor-Transistor Logic
MM
Machine Model
TTL
Transistor-Transistor Logic
GTL2005_7
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 07 — 3 February 2009
16 of 19
GTL2005
NXP Semiconductors
Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator
16. Revision history
Table 12.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
GTL2005_7
20090203
Product data sheet
-
GTL2005_6
Modifications:
•
Figure 2 “Logic diagram of GTL2005” modified: symbol for AND gate replaced and its direction
reversed
•
updated soldering information
GTL2005_6
20070906
Product data sheet
-
GTL2005_5
GTL2005_5
(9397 750 14285)
20050406
Product data sheet
-
GTL2005_4
GTL2005_4
(9397 750 13104)
20040510
Product data
-
GTL2005_3
GTL2005_3
(9397 750 07222)
20000619
Product data
853-2171 23901
GTL2005_2
GTL2005_2
(9397 750 06695)
19990917
Product data
853-2171 22353
GTL2005_1
GTL2005_1
(9397 750 06497)
19990917
Product data
GTL2005_7
Product data sheet
-
© NXP B.V. 2009. All rights reserved.
Rev. 07 — 3 February 2009
17 of 19
GTL2005
NXP Semiconductors
Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator
17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
17.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
GTL2005_7
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 07 — 3 February 2009
18 of 19
GTL2005
NXP Semiconductors
Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator
19. Contents
1
2
3
4
5
6
6.1
6.2
7
7.1
8
9
10
10.1
11
11.1
12
13
14
14.1
14.2
14.3
14.4
15
16
17
17.1
17.2
17.3
17.4
18
19
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 4
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Performance curves . . . . . . . . . . . . . . . . . . . . . 8
Dynamic characteristics . . . . . . . . . . . . . . . . . 11
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Test information . . . . . . . . . . . . . . . . . . . . . . . . 12
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13
Soldering of SMD packages . . . . . . . . . . . . . . 14
Introduction to soldering . . . . . . . . . . . . . . . . . 14
Wave and reflow soldering . . . . . . . . . . . . . . . 14
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 14
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 15
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17
Legal information. . . . . . . . . . . . . . . . . . . . . . . 18
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Contact information. . . . . . . . . . . . . . . . . . . . . 18
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 3 February 2009
Document identifier: GTL2005_7
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