PTN3356R1 ROM-based low-power DisplayPort to VGA adapter Rev. 2.1 — 16 July 2015 Product data sheet 1. General description PTN3356R1 is a ROM-based DisplayPort to VGA adapter optimized primarily for motherboard applications, to convert a DisplayPort signal from the chip set to an analog video signal that directly connects to the VGA connector. PTN3356R1 integrates a DisplayPort receiver, a high-speed triple video digital-to-analog converter that supports a wide range of display resolutions, for example, VGA to WUXGA (see Table 8). PTN3356R1 supports two DisplayPort lanes operating at either 2.7 Gbit/s or 1.62 Gbit/s per lane. PTN3356R1 supports I2C-bus over AUX per DisplayPort standard (Ref. 1), and bridges the VESA DDC channel to the DisplayPort Interface. PTN3356R1 is powered from a 3.3 V power supply and consumes approximately 200 mW of power for video streaming in WUXGA resolution and 410 W of power in Low-power mode. The VGA output is powered down when there is no valid DisplayPort source data being transmitted. PTN3356R1 also aids in monitor detection by performing load sensing on RGB lines and reporting sink connection status to the source. 2. Features and benefits 2.1 VESA-compliant DisplayPort converter Main Link: 1-lane and 2-lane modes supported HBR (High Bit Rate) at 2.7 Gbit/s per lane RBR (Reduced Bit Rate) at 1.62 Gbit/s per lane BER (Bit Error Rate) better than 109 DisplayPort Link down-spreading supported 1 MHz AUX channel Supports native AUX CH syntax Supports I2C-bus over AUX CH syntax Active HIGH Hot Plug Detect (HPD) signal to the source 2.2 VESA-compliant eDP extensions Supports Alternate Scrambler Seed Reset (ASSR) Supports Alternate Enhanced Framing mode - Enhanced Framing 2.3 DDC channel output I2C-Over-AUX feature facilitates support of MCCS, DDC/CI, and DDC protocols (see Ref. 2) PTN3356R1 NXP Semiconductors ROM-based low-power DP to VGA adapter 2.4 Analog video output VSIS 1.2 compliance (Ref. 3) for supported video output modes Analog RGB current-source outputs 3.3 V VSYNC and HSYNC outputs Pixel clock up to 240 MHz Triple 8-bit Digital-to-Analog Converter (DAC) Direct drive of double terminated 75 load with standard 700 mV (peak-to-peak) signals 2.5 General features Monitor presence detection through load detection scheme. Connection/disconnection reported via HPD IRQ and DPCD update. Wide set of display resolutions are supported1: 1920 1440, 60 Hz, 18 bpp, 234 MHz pixel clock rate 2048 1152, 60 Hz (reduced blanking), 24 bpp, 162 MHz pixel clock rate 2048 1536, 50 Hz (reduced blanking), 24 bpp, 167.2 MHz pixel clock rate WUXGA: 1920 1200, 60 Hz, 18 bpp, 193 MHz pixel clock rate WUXGA: 1920 1200, 60 Hz (reduced blanking), 24 bpp, 154 MHz pixel clock rate UXGA: 1600 1200, 60 Hz, 162 MHz pixel clock rate SXGA: 1280 1024, 60 Hz, 108 MHz pixel clock rate XGA: 1024 768, 60 Hz, 65 MHz pixel clock rate SVGA: 800 600, 60 Hz, 40 MHz pixel clock rate VGA: 640 480, 60 Hz, 25 MHz pixel clock rate Any resolution and refresh rates are supported from 25 MHz up to 180 MHz pixel clock rate at 24 bpp, or up to 240 MHz pixel clock rate at 18 bpp Bits per color (bpc) supported1 6, 8 bits supported 10, 12, 16 bits supported by truncation to 8 MSBs All VGA colorimetry formats (RGB) supported Power modes (when the application design is as per Figure 4) Active-mode power consumption: ~200 mW at WUXGA, 1920 1200, 60 Hz (18 bpc) 410 W at Low-power mode Supports flexible choice of timing reference On-board oscillator with external crystal, ceramic resonator Different frequencies supported: 24 MHz, 25 MHz, 27 MHz ESD protection: 7 kV HBM Single power supply (3.3 V) for easy integration in the platforms Commercial temperature range: 0 C to 85 C 32-pin HVQFN, 5 mm 5 mm 0.85 mm (nominal); 0.5 mm pitch; lead-free package 1. Except for color depth beyond 8 bits, display resolutions and refresh rates are only limited to those which a standard 2-lane DisplayPort configuration is able to support over 2.7 Gbit/s per lane of DP Main Link. PTN3356R1 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 16 July 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 2 of 38 PTN3356R1 NXP Semiconductors ROM-based low-power DP to VGA adapter 3. Applications Notebook computers, tablets and desktop PCs Dongles, adapters, docking stations 4. Ordering information Table 1. Ordering information Type number PTN3356R1BS [1] Topside mark 356R1 Package Name Description Version HVQFN32 plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; 5 5 0.85 mm[1] SOT617-3 Maximum height is 1 mm. 4.1 Ordering options Table 2. Ordering options Type number Orderable part number Package Packing method PTN3356R1BS PTN3356R1BSMP HVQFN32 Reel 13” Q2/T3 *standard mark 6000 SMD dry pack Tamb = 0 C to +85 C PTN3356R1BS PTN3356R1BSZ HVQFN32 Reel 7” Q2/T3 *standard mark SMD dry pack Tamb = 0 C to +85 C PTN3356R1 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 16 July 2015 Minimum order quantity 500 Temperature © NXP Semiconductors N.V. 2015. All rights reserved. 3 of 38 xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x ML1_P, ML1_N 10b/8b DIFF CDR, RCV S2P DE-SCRAM Vbias TIME CONV. DAC G[7:0] MAIN STREAM B[7:0] TIMING RECOVERY DAC DAC RED GRN BLU MONITOR PRESENCE DETECT INTERFACE DE-SKEWING 10b/8b ML0_P, ML0_N VIDEO DAC SUBSYSTEM ISOCHRONOUS LINK R[7:0] DE-SCRAM DIFF CDR, RCV S2P RX PHY DIGITAL HSYNC VSYNC H, V sync VGA OUTPUT DPCD REGISTERS CONTROL ROM MCU Rev. 2.1 — 16 July 2015 RCV MANCHESTER CODEC AUX_P, AUX_N HPD DRV Functional diagram RX DIGITAL SUBSYSTEM Vbias OSC_IN Fig 1. AUX COMMAND LEVEL MODULE DDC_SCL DDC_SDA I2C-BUS MASTER OSC_OUT RSET RST_N CFG1, CFG2 aaa-013783 PTN3356R1 4 of 38 © NXP Semiconductors N.V. 2015. All rights reserved. ROM-based low-power DP to VGA adapter All information provided in this document is subject to legal disclaimers. Vbias NXP Semiconductors RX PHY ANALOG SUBSYSTEM 5. Functional diagram PTN3356R1 Product data sheet PTN3356R1 CFG3, CFG5, TESTMODE PTN3356R1 NXP Semiconductors ROM-based low-power DP to VGA adapter 6. Pinning information 25 OSC_IN 26 OSC_OUT 27 VDDA15_DAC 28 VDDD15 29 TESTMODE 30 PVDD33 31 SWOUT terminal 1 index area 32 PGND 6.1 Pinning VDDA33_DNW 1 24 RED AUX_P 2 23 RSET AUX_N 3 22 GRN ML0_P 4 21 BLU PTN3356R1 ML0_N 5 20 HSYNC VDDA15_DP 6 19 VSYNC DDC_SCL 16 CFG2 15 CFG3 14 CFG5 13 17 VDDE33_IO CFG1 12 HPD 11 VDDE33_IO 9 ML1_N 8 18 DDC_SDA GND(1) RST_N 10 ML1_P 7 Transparent top view aaa-013784 (1) Exposed die pad. Fig 2. Pin configuration for HVQFN32 6.2 Pin description Table 3. Pin description Symbol Pin Type Description VDDA33_DNW 1 power 3.3 V power supply AUX_P 2 self-biasing differential input DisplayPort AUX channel positive input AUX_N 3 self-biasing differential input DisplayPort AUX channel negative input ML0_P 4 self-biasing differential input DisplayPort Main Link lane 0 positive input ML0_N 5 self-biasing differential input DisplayPort Main Link lane 0 negative input VDDA15_DP 6 power 1.5 V power supply for DisplayPort PHY; power provided to this pin from SWOUT pin ML1_P 7 self-biasing differential input DisplayPort Main Link lane 1 positive input ML1_N 8 self-biasing differential input DisplayPort Main Link lane 1 negative input PTN3356R1 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 16 July 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 5 of 38 PTN3356R1 NXP Semiconductors ROM-based low-power DP to VGA adapter Table 3. Pin description …continued Symbol Pin Type Description VDDE33_IO 9 power 3.3 V power supply for I/O RST_N 10 3.3 V digital input Reset input active LOW; pulled up to VDD(3V3) internally HPD 11 3.3 V digital I/O DisplayPort Hot Plug Detection output CFG1 12 5 V open-drain I/O General purpose configuration pin CFG1 CFG5 13 3.3 V digital I/O Configuration pin supporting trinary input CFG3 14 3.3 V digital I/O Reserved CFG2 15 5 V open-drain I/O General purpose configuration pin CFG2 DDC_SCL 16 5 V open-drain I/O DDC I2C-bus clock VDDE33_IO 17 power 3.3 V power supply for I/O DDC_SDA 18 5 V open-drain I/O DDC I2C-bus data VSYNC 19 3.3 V 50 digital I/O Vertical sync HSYNC 20 3.3 V 50 digital I/O Horizontal sync BLU 21 analog output Blue DAC analog output GRN 22 analog output Green DAC analog output RSET 23 input Resistor for DAC output reference control RED 24 analog output Red DAC analog output OSC_IN 25 input Crystal oscillator input OSC_OUT 26 output Crystal oscillator output VDDA15_DAC 27 power 1.5 V power supply for DAC; power provided to this pin from SWOUT pin VDDD15 28 power 1.5 V power supply for digital core; power provided to this pin from SWOUT pin TESTMODE 29 input Test mode selection for CFG/JTAG PVDD33 30 power 3.3 V power supply for switching regulator SWOUT 31 power Switching regulator output PGND 32 ground Ground for switching regulator GND[1] - power central supply ground connection (exposed die pad) [1] HVQFN32 package die supply ground is connected to exposed center pad. Exposed center pad must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad must be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias must be incorporated in the PCB in the thermal pad region. PTN3356R1 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 16 July 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 6 of 38 PTN3356R1 NXP Semiconductors ROM-based low-power DP to VGA adapter 7. Functional description Referring to Figure 1 “Functional diagram”, the PTN3356R1 performs protocol conversion from VESA DisplayPort specification to VESA VGA output. At the physical layer, PTN3356R1 implements the advanced DisplayPort Front-end technology (Auto receive equalization, Clock Data Recovery) to support the objectives of delivering excellent Signal Integrity (SI) performance, and consuming very low power consumption. The PTN3356R1 integrates a DisplayPort receiver (according to VESA DisplayPort standard, Ref. 1) and a high-speed triple 8-bit video digital-to-analog converter that supports a wide range of video resolutions (see Table 8 “Display resolution and pixel clock rate[1]”), up to a pixel clock rate of 240 MHz. The PTN3356R1 supports one or two DisplayPort Main Link lanes operating at either in 2.7 Gbit/s or 1.62 Gbit/s per lane. PTN3356R1 comprises the following functional blocks: • • • • • DP Main Link DP AUX CH (Auxiliary Channel) DPCD (DisplayPort Configuration Data) VGA monitor detection Video DAC The RGB video data with corresponding synchronization references are extracted from the main stream video data. Main stream video attribute information is also extracted. This information is inserted once per video frame during the vertical blanking period by the DP source. The attributes describe the main video stream format in terms of geometry, timing, and color format. The original video clock and video stream are derived from these main link data. The PTN3356R1 internal DPCD registers can be accessed by the DP source via the DP AUX channel. The monitor’s DDC control bus may also be controlled via the DP AUX channel. PTN3356R1 implements the standard DisplayPort I2C-over-AUX protocol conversion to provide DP source access to the VGA plug DDC-I2C interface. The PTN3356R1 passes through sink-side status change (for example, hot-plug events) to the source side, through HPD interrupts and DPCD registers. 7.1 DisplayPort Main Link The DisplayPort main link consists of two AC-coupled differential pairs. The 50 termination resistors are integrated inside PTN3356R1. The PTN3356R1 supports HBR at 2.7 Gbit/s and RBR at 1.62 Gbit/s per lane. 7.2 DisplayPort auxiliary channel (AUX CH) The AUX CH is a half-duplex, bidirectional channel between DisplayPort source and sink. It consists of one differential pair transporting self-clocked data at 1 Mbit/s. The PTN3356R1 integrates the AUX CH replier (or slave), and responds to transactions initiated by the DisplayPort source AUX CH requester (or master). The AUX CH uses the Manchester-II code for the self-clocked transmission of signals; every ‘zero’ is represented by LOW-to-HIGH transition, and ‘one’ represented by HIGH-to-LOW transition, in the middle of the bit time. PTN3356R1 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 16 July 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 7 of 38 PTN3356R1 NXP Semiconductors ROM-based low-power DP to VGA adapter 7.3 DPCD registers DPCD registers that are part of the VESA DisplayPort standard are described in detail in Ref. 1. The following describes the specific implementation by PTN3356R1 only. PTN3356R1 DisplayPort receiver capability and status information about the link are reported by DisplayPort Configuration Data (DPCD) registers, when a DP source issues a read command on the AUX CH. The DP source device can also write to the link configuration field of DPCD to configure and initialize the link. The DPCD is DisplayPort v1.2a compliant. PTN3356R1 specific capabilities are made available to DP source in the relevant DPCD read/write registers. In line with the DisplayPort standard (Ref. 1), the specific Link controls are also made available to initialize and maintain the DisplayPort Link. It is the responsibility of the DP source to issue commands only within the capability of the PTN3356R1 as defined in the ‘Receiver Capability Field’ in order to prevent undefined behavior. PTN3356R1 specific DPCD registers are listed in Table 4. 7.3.1 PTN3356R1 specific DPCD register settings Table 4. PTN3356R1 specific DPCD registers DPCD Description register [1] Power-on Reset value Read/write over AUX CH Receiver Capability Field 0000Ch I2C-bus speed control capabilities bit map. Speed control is 00h not supported through DPCD register. Default speed of 50 kbit/s is supported. read only 0000Dh eDP_CONFIGURATION_CAP. 03h read only I2C-bus speed control capabilities bit map. Speed control is 00h not supported and the default speed of 50 kbit/s is supported. Writes are ignored and reads would get zeros. read/write Bit 0 = ALTERNATE_SCRAMBLER_RESET_CAPABLE. A setting of 1 indicates that this is an eDP device that can use the eDP alternate scrambler reset value of FFFFh. Bit 1 = FRAMING_CHANGE_CAPABLE. A setting of 1 indicates that this is an eDP device that uses only Enhanced Framing independently of the setting by the source of ENHANCED_FRAME_EN. Bit 2 = reserved for eDP. Read 0. Bit 3 = DPCD_DISPLAY_CONTROL_CAPABLE. A setting of 1 indicates that display control registers starting at address 00700h are enabled. Bits 7:4 = reserved for eDP. Read all zeros. Link Configuration Field 00109h PTN3356R1 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 16 July 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 8 of 38 PTN3356R1 NXP Semiconductors ROM-based low-power DP to VGA adapter Table 4. PTN3356R1 specific DPCD registers …continued DPCD Description register [1] Power-on Reset value Read/write over AUX CH 0010Ah 00h read/write 00h read only 60h read only 37h read only 33h read only 00504h 33h read only 00505h 35h read only 00506h 36h read only 00507h 4Eh read only 00508h 32h read only Bit 0 = ALTERNATE_SCRAMBLER_RESET_ENABLE. Source sets to 1 to select the alternate scrambler reset. Writes ignored if ALTERNATE_SCRAMBLER_RESET_CAPABLE = 0. Power-on default value = 0. Bit 1 = FRAMING_CHANGE_ENABLE. Source sets to 1 to select the framing change. Writes ignored if FRAMING_CHANGE_CAPABLE = 0. Power-on default value = 0. Bits 6:2 = reserved. Read all zeros. Bit 7 = PANEL_SELF_TEST_ENABLE (not supported in PTN3356R1). Branch device specific field 00500h BRANCH_IEEE_OUI 7:0 Branch vendor 24-bit IEEE OUI. NXP OUI = 00 00501h BRANCH_IEEE_OUI 15:8 NXP OUI = 60 00502h BRANCH_IEEE_OUI 23:16 NXP OUI = 37 00503h ID string = 3356N2 00509h Hardware revision level v1.1 10h read only 0050Ah Firmware/software major revision level 01h read only 0050Bh Firmware/software minor revision level 02h read only 0050Ch to RESERVED 005FFh [1] PTN3356R1 Product data sheet read only Byte fields that are not explicitly listed are by definition reserved (‘RES’) and their default value is 0h. All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 16 July 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 9 of 38 PTN3356R1 NXP Semiconductors ROM-based low-power DP to VGA adapter 7.4 VGA monitor detection The PTN3356R1 implements a robust scheme for VGA monitor detection. It senses presence or absence of VGA monitor load termination (75 ) by pulsing the RGB lines. The load sensing operation is performed periodically to determine the latest VGA connectivity status. If the VGA monitor is disconnected, then the detection logic informs the host platform via IRQ_HPD signal. 7.5 EDID handling Figure 3 shows a DisplayPort-to-analog video converter between the DisplayPort source and a VGA monitor. The PTN3356R1 implements a DP I2C-Over-AUX protocol, providing for DP source access to the monitor’s DDC bus. With this, the monitor’s EDID data is made available to DP source for access at any time. It is the responsibility of the source to choose only video modes which are declared in the EDID and to adjust the DisplayPort link capabilities (link rate and lane count) to provide the necessary video bandwidth. The PTN3356R1 does not cache or modify the EDID to match the capabilities of the DisplayPort link data. If the DisplayPort source drives display modes that are not specified in the EDID mode list, the PTN3356R1 does not detect such conditions, and it depends entirely on the VGA display on what is being displayed. sink device DisplayPort to VGA adapter IC source device DP Tx embedded DisplayPort DP Rx with DPCD VIDEO DAC box-to-box legacy VGA DISPLAY WITH EDID aaa-014243 Fig 3. DisplayPort to VGA adapter IC sits between the DisplayPort source and a VGA monitor with EDID 7.6 Triple 8-bit video DACs and VGA outputs The triple 8-bit video DACs output a 700 mV (peak-to-peak) analog video output signal into 37.5 load, as is the case of a doubly terminated 75 cable. The DAC is capable of supporting the maximum pixel rate supported by a two-lane DP link (240 MHz). 7.6.1 DAC reference resistor An external reference resistor must be connected between pin RSET and ground. This resistor sets the reference current which determines the analog output level, and is specified as 1.2 k with a 1 % tolerance. This value allows a 0.7 V (peak-to-peak) output into a 37.5 load (for example, double-terminated 75 coaxial cable). PTN3356R1 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 16 July 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 10 of 38 PTN3356R1 NXP Semiconductors ROM-based low-power DP to VGA adapter 8. Power-up and reset PTN3356R1 has built-in power-on reset circuitry which automatically sequences the part through reset and initialization. In addition, there is a dedicated pin (RST_N) to control/effect reset operation externally. This provides flexibility at the platform level for debug or application purpose. Before link is established, the PTN3356R1 holds VSYNC and HSYNC signals LOW and blanks the RGB signals. While the PTN3356R1 performs power-on initialization, • The HPD signal is driven LOW, to indicate to the DisplayPort source that the PTN3356R1 is not ready for AUX channel communication. Once the device is initialized, the HPD level is produced based on CFG1/CFG2 setting • The RGB outputs are disabled • The VSYNC and HSYNC outputs are maintained LOW as long as there is no active video streaming from the DisplayPort source. 9. Configurability The PTN3356R1 delivers flexibility for application usage by providing configurability via two options: • Configuration pins CFG1, CFG2, CFG5, and TESTMODE • DP-AUX vendor-specific configuration registers The pins provide limited application board level configurability, whereas vendor-specific configuration registers deliver ultimate flexibility. The configuration pin changes (static, dynamic) are reflected in the IC behavior. The configuration pin definitions are as follows: • CFG1, CFG2 are used as dedicated configuration pins with binary leveled I/O. The use of these configuration pins is defined in Table 7. • Configuration pin CFG5 selects OSC_IN clock frequency setting. Table 5 captures the pin definition. Table 5. CFG5 pin definition Configuration input OSC_IN clock frequency setting HIGH 24 MHz LOW 25 MHz OPEN 27 MHz The TESTMODE pin is used to indicate selection of JTAG or configuration for CFG1, CFG2 and CFG5. Table 6 defines the possible combinations of TESTMODE pin. PTN3356R1 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 16 July 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 11 of 38 PTN3356R1 NXP Semiconductors ROM-based low-power DP to VGA adapter Table 6. TESTMODE pin definition Pin value Mode selection LOW Configuration pin functionality is selected OPEN Configuration pin functionality is selected HIGH JTAG functionality is selected. CFG1, CFG2 can be used in configuration pin mode. PTN3356R1 automatically detects the mode in which these pins are used. If they are used as Configuration pins, Table 7 determines the possible and allowed combinations for these pin settings. Table 7. CFG1/CFG2 pin definitions Pin value System behavior 00 Compliant HPD behavior 01 Most interoperable (non-compliant) HPD behavior 10 Most interoperable (non-compliant) HPD behavior 11 (Default) Compliant behavior 10. Application design-in information With its maximum integration features, the PTN3356R1 has low BOM requirement at the platform application level. Figure 4 illustrates the PTN3356R1 usage in a system application context. On the DP side, it is connected to DP source and the VGA side, it is connected to VGA connector. The PTN3356R1 system application requires the following components additionally: supply decoupling capacitors, DC blocking capacitors, pull-up/down resistors, (optional) inductor for DC-to-DC converter, crystal oscillator. For more details on reference design information, contact NXP team. PTN3356R1 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 16 July 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 12 of 38 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors +3V3 OSC_IN 2 OSC_OUT 1 2 DDC_SDA GRN_VGA 25 23 RSET 22 GRN 21 BLU 20 HSYNC 1 19 VSYNC 1 1.2K 1% 36 2HSYNC_VGA 2VSYNC_VGA 2 2.2K 1 2 2.2K 1 2 3 BAT54 74LVC2G125DP 2 1 2 22 Ohm 300mA 1 1 1 RED_VGA 1 2 22 Ohm 300mA GRN VS_5V GRN_VGA 1 2 22 Ohm 300mA 2 BLU 2 2 4 2 6 2 10K 2 8 10K VSYNC_VGA 3 PESD5V0U2BT CFG2 RED DNL 3 2 PI FILTER DESIGN IS CUSTOMER SPECIFIC CFG1 BLU_VGA 1 3.3pF 3.3pF 1 2 DNL 2 1 DNL 2 1 2 DNL 1 CFG1, CFG2: 00, DP Compliant mode 10, non-DP Compliant mode 2 HS_5V 1 2 0 2 0 1 1 3.3pF 3.3pF 3.3pF VS_5V aaa-013785 Part shaded in yellow is extra component required in DC-to-DC converter mode to achieve low power performance. Fig 4. Application with DC-to-DC converter mode PTN3356R1 13 of 38 © NXP Semiconductors N.V. 2015. All rights reserved. 1 VSYNC_VGA 1 DNL HSYNC_VGA 75 1 75 75 3.3pF 2 74LVC2G125DP ROM-based low-power DP to VGA adapter DNL HS_5V 1 DDC1_PU CFG3 CFG3 OPEN, NOT USED PESD5V0U2BT 1 VDD_3V3 2 (OPTIONAL) 1uF CFG5_XTAL CFG5 OPEN: 27 MHZ XTAL IS USED 3 4 1 OPTION DESIGN: ESD PROTECTION CIRCUITRY. 1 2 VDD_5V 10K 5 HSYNC_VGA 10pF 1 GND 33 0.1uF DDC_SCL 1 2 2 DNL 10pF 3 DDC_SCL1 VDD_3V3 1 17 2 DDC_SDA 2 18 2 36 HPD 7 0.1uF 16 17 VGA_CONN 1 0.1uF VDD_5V RED_RTN NC1 RED GREEN_RTN SDA GREEN BLUE_RTN HS BLUE +5V VS NC2 GND1 SCL GND2 GND3 GND4 RED 1 VDDE33_IO 24 PESD5V0U2BT ML1_N PTN3356 RED_VGA 12pF DNL OSC_IN 27 DDC_SDA1 9 VDD_3V3 26 ML1_P VDDE33_IO 2 VSYNC1 16 8 HSYNC1 VDDA15_DP CFG2_SDA/TMS ML1_N ML0_N CFG3/TDO 7 BLU1 CFG5/TCK 1 ML1_P 0.1uF ML0_P CFG1_SCL/TDI 5 GRN1 13 ML0_N RSET AUX_N 12 2 4 6 8 Rev. 2.1 — 16 July 2015 All information provided in this document is subject to legal disclaimers. VBUCK_1V5 ML0_P 6 11 1 7 12 2 8 13 3 9 14 4 10 15 5 BAT54 VS_5V AUX_P HPD 3 RST_N 2 AUX_N 3 2 DDC_SCL RED1 11 1 AUX_P 0.1uF VDD_CONN_5V HS_5V BLU_VGA VDDA33_DNW 10 1 100K 1 OPTION DESIGN: Install U3 to support 5V H/V for legacy projector and CRTs. 1 3 VDD_3V3 (OPTIONAL) OSC_OUT PGND 2 HPD 15 AUX_N 0.1uF TESTMODE 2 VDD_5V 1 1 0.1uF 28 AUX_P 1 29 1 0.1uF 2 32 0.1uF VDDD15 0.1uF 2 1 SWOUT 1 ML1_N 31 2 SWOUT ML1_P 1 VDD_3V3 TESTMODE 2 1 0.1uF 2 Resonator (with built-in capacitors) 2 4.7uH 2 CPU/GPU + 4.7uF VDDA15_DAC 2.2uF 2 12pF DNL 27MHz 2 1 2 FB 0.1uF 30 ML0_N 0.1uF PVDD33 2 1 1 VBUCK_1V5 2 1 ML0_P 14 1 0.1uF 2 1 VDD_3V3 +3V3 1 1 PTN3356R1 Product data sheet VDD_5V xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors VDD_3V3 VDD_3V3 ML0_N 1 1 3 2 VDD_5V VDD_CONN_5V OSC_IN 2 OSC_OUT 1 TESTMODE 2 25 OSC_IN 27 VDDA15_DAC ML1_P DDC_SDA1 ML1_N VDDE33_IO 24 RED 16 17 VGA_CONN 23 RSET 22 GRN 21 BLU 20 HSYNC 1 19 VSYNC 1 1.2K 1% 36 2 HSYNC_VGA 2 VSYNC_VGA 36 18 DDC_SDA 17 VDD_3V3 GND 0.1uF 33 9 PTN3356 DDC_SDA GRN_VGA RED_RTN NC1 RED GREEN_RTN SDA GREEN BLUE_RTN HS BLUE +5V VS NC2 GND1 SCL GND2 GND3 GND4 VDD_5V 1 VDD_3V3 28 VSYNC1 VDDE33_IO 2 VDDA15_DP DDC_SCL1 8 HSYNC1 16 ML1_N BLU1 ML0_N CFG3/TDO 7 ML0_P 14 1 ML1_P 0.1uF DDC_SCL 0.1uF HPD 2 VDD_3V3 2.2K 1 2 2.2K 1 2 DDC1_PU 1 CFG3 CFG3 OPEN, NOT USED CFG5_XTAL CFG5 OPEN: 27 MHZ XTAL IS USED 10K DNL 2 1 CFG2 10K 1 2 22 Ohm 300mA RED RED_VGA 1 2 22 Ohm 300mA GRN 10K GRN_VGA 1 2 22 Ohm 300mA 1 3.3pF 3.3pF 1 2 DNL 2 1 DNL 2 1 3.3pF 3.3pF 2 DNL 3.3pF 1 3.3pF 2 1 1 75 2 75 1 CFG1, CFG2: 00, DP Compliant mode 10, non-DP Compliant mode 1 75 2 2 2 2 2 BLU BLU_VGA Fig 5. Application with LDO mode PTN3356R1 14 of 38 © NXP Semiconductors N.V. 2015. All rights reserved. aaa-013786 ROM-based low-power DP to VGA adapter PI FILTER DESIGN IS CUSTOMER SPECIFIC CFG1 1 Rev. 2.1 — 16 July 2015 All information provided in this document is subject to legal disclaimers. 6 RSET GRN1 CFG5/TCK 5 AUX_P 13 ML0_N 6 11 1 7 12 2 8 13 3 9 14 4 10 15 5 RED_VGA 12pF DNL VSYNC_VGA AUX_N CFG1_SCL/TDI 2 VBUCK_1V5 4 HPD 3 ML0_P 3 BAT54 DDC_SCL RED1 RST_N AUX_N 0.1uF 2 HSYNC_VGA BLU_VGA VDDA33_DNW 11 AUX_P 2 10 1 1 29 30 VDD_3V3 1 1 0.1uF VDDD15 HPD TESTMODE PGND 0.1uF 31 AUX_N SWOUT AUX_P 2 PVDD33 0.1uF 2 1 32 0.1uF 1 Resonator (with built-in capacitors) 2 0.1uF 2 1 26 ML1_N OSC_OUT 2 CFG2_SDA/TMS ML1_P 1 VDD_3V3 15 1 0.1uF 2 12 CPU/GPU 4.7uF 2 0.1uF 2 + 2.2uF 2 12pF DNL 27MHz 1 2 0.1uF 2 ML0_P 1 1 VBUCK_1V5 1 1 0.1uF 2 1 PTN3356R1 Product data sheet VDD_5V PTN3356R1 NXP Semiconductors ROM-based low-power DP to VGA adapter 10.1 Display resolution Table 8 lists some example display resolutions and clock rates that PTN3356R1 supports. (Refer to Footnote 1 on page 2.) Table 8. Display resolution and pixel clock rate[1] Display type Active video Total frame VGA 640 480 800 525 24 59.94 25.175 0.76 Industry standard SVGA 800 600 1056 628 24 60.317 40.000 1.20 VESA guidelines XGA 1024 768 1344 806 24 60.004 65.000 1.95 VESA guidelines XGA+ 1152 864 1600 900 24 75 108.000 3.24 VESA standard HD 1360 768 1792 795 24 60.015 85.500 2.56 VESA standard HD/WXGA 1366 768 1792 798 24 59.79 85.501 2.57 VESA standard HD/WXGA 1280 720 1650 750 24 60 74.250 2.23 CEA standard WXGA 1280 800 1680 831 24 59.81 83.500 2.50 CVT Horizontal Vertical Horizontal Vertical total (pixel) total (line) Bits per pixel Vertical Pixel frequency clock (Hz) (MHz) Data Standard type rate (Gbit/s) WXGA 1280 800 1696 838 24 74.934 106.500 3.19 CVT WXGA 1280 800 1712 843 24 84.88 122.500 3.68 CVT SXGA 1280 960 1800 1000 24 60 108.000 3.24 VESA standard SXGA 1280 1024 1688 1066 24 60.02 108.000 3.24 VESA standard SXGA 1280 1024 1688 1066 24 75.025 135.001 4.05 VESA standard SXGA 1280 1024 1728 1072 24 85.024 157.500 4.72 VESA standard SXGA+ 1400 1050 1864 1089 24 59.978 121.749 3.65 CVT WXGA+ 1440 900 1904 934 24 59.887 106.499 3.19 CVT HD+ 1600 900 1800 1000 24 60 (RB) 108.000 3.24 VESA standard UXGA 1600 1200 2160 1250 24 60 162.000 4.86 VESA standard UXGA 1600 1200 2160 1250 24 65 175.500 5.27 VESA standard WSXGA+ 1680 1050 2240 1089 24 59.954 146.249 4.39 CVT FHD 1920 1080 2200 1125 24 60 148.500 4.46 CEA standard WUXGA 1920 1200 2592 1245 18 59.885 193.251 4.35 CVT WUXGA 1920 1200 2080 1235 24 59.95 (RB) 154.000 4.62 CVT RB 2.76M3 1920 1440 2600 1500 18 60 234.000 5.27 VESA standard QWXGA 2048 1152 2250 1200 24 60 (RB) 162.000 4.86 CVT RB QXGA 2048 1536 2128 1573 24 49.95 (RB) 167.20 5.02 CVT RB [1] Contact NXP team for other monitor timings not listed in this table. The available bandwidth over a 2-lane HBR DisplayPort v1.2a link limits pixel clock rate support to: • 240 MHz at 6 bpc • 180 MHz at 8 bpc PTN3356R1 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 16 July 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 15 of 38 PTN3356R1 NXP Semiconductors ROM-based low-power DP to VGA adapter 10.2 Power supply filter Sufficient decoupling capacitance to ground should be connected from each VDD pin directly to ground to filter supply noise. 10.3 DAC terminations Typically, the VGA RGB outputs are (doubly) terminated. Figure 6 shows an example VGA application. A 75 termination is used to terminate inside the motherboard, and another 75 termination is typically used inside the RGB monitor. The load sensing mechanism assumes this double termination. Figure 7 is another example of VGA application with 50 PCB trace impedance with 150 terminations. In general, it is left to the system integrator to decide on their specific implementation. close to PTN3356R1 37.5 Ω PCB traces close to VGA connector 75 Ω PCB traces 75 Ω PCB traces PCB EMI filter RED, GRN, BLU DAC GND 75 Ω cable 75 Ω 75 Ω MOTHERBOARD MONITOR aaa-014242 Fig 6. PTN3356R1 DAC termination example 1 close to PTN3356R1 37.5 Ω PCB traces close to VGA connector 50 Ω PCB traces 75 Ω PCB traces PCB EMI filter RED, GRN, BLU DAC GND 150 Ω 150 Ω MOTHERBOARD 75 Ω cable 75 Ω MONITOR aaa-013787 Fig 7. PTN3356R1 Product data sheet PTN3356R1 DAC termination example 2 All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 16 July 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 16 of 38 PTN3356R1 NXP Semiconductors ROM-based low-power DP to VGA adapter 10.4 Timing reference PTN3356R1 requires a crystal or ceramic resonator for a stable VGA clock timing reference. Resonators have a higher frequency tolerance than crystals, but have the advantage of integrated capacitors and therefore a small PCB area and potentially lower cost. Table 9. PTN3356R1 Product data sheet Required crystal specifications (SMD components) Crystal parameters Specifications Frequency 24 MHz, 25 MHz or 27 MHz Operation mode Fundamental Frequency tolerance 1 % maximum Frequency stability over temperature 0.4 % maximum Load capacitance (CL) 18 pF Shunt capacitance < 2 pF Equivalent Series Resistance (ESR) < 150 All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 16 July 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 17 of 38 PTN3356R1 NXP Semiconductors ROM-based low-power DP to VGA adapter 11. Limiting values Table 10. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD(3V3) supply voltage (3.3 V) Conditions VI input voltage Tstg storage temperature 3.3 V CMOS inputs VESD electrostatic discharge voltage Min Max Unit 0.3 +4.6 V 0.3 VDD(3V3) + 0.5 V 65 +150 C HBM [1] - 7000 V CDM [2] - 1000 V [1] Human Body Model: ANSI/ESDA/JEDEC JDS-001-2012 (Revision of ANSI/ESDA/JEDEC JS-001-2011), ESDA/JEDEC Joint standard for ESD sensitivity testing, Human Body Model - Component level; Electrostatic Discharge Association, Rome, NY, USA; JEDEC Solid State Technology Association, Arlington, VA, USA. [2] Charged Device Model: JESD22-C101E December 2009 (Revision of JESD22-C101D, October 2008), standard for ESD sensitivity testing, Charged Device Model - Component level; JEDEC Solid State Technology Association, Arlington, VA, USA. 12. Recommended operating conditions Table 11. Operating conditions Symbol Parameter Min Typ VDD(3V3) supply voltage (3.3 V) tr rise time supply voltage 2.8 3.3 3.6 V - - 10 ms VI input voltage 3.3 V CMOS inputs 0 3.3 3.6 V SDA and SCL inputs with respect to ground 0 5 5.5 V Rext(RSET) external resistance on pin RSET between RSET (pin 21) and GND - 1.20 1 % - k Tamb ambient temperature 0 - 85 C PTN3356R1 Product data sheet Conditions commercial grade All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 16 July 2015 Max Unit © NXP Semiconductors N.V. 2015. All rights reserved. 18 of 38 PTN3356R1 NXP Semiconductors ROM-based low-power DP to VGA adapter 13. Characteristics 13.1 Current consumption, power dissipation and thermal characteristics Table 12. Current consumption, power dissipation and thermal characteristics Over operating free-air temperature range, unless otherwise noted. Symbol Parameter Conditions Min Typ Max Unit IDD supply current normal operation, WUXGA / 193 MHz pixel clock; VDD(3V3) = 3.3 V - 60 - mA Low power D3 mode; VDD(3V3) = 3.3 V - 124 - A Buck converter mode; PTN3356R1 being used as per Figure 4 - 200 - mW LDO mode; PTN3356R1 being used as per Figure 5 - 405 - mW - 45 - K/W P power dissipation Rth(j-a) normal operation, WUXGA / 193 MHz pixel clock (reduced blanking) thermal resistance from junction to ambient in free air for SOT617-3 Table 13. Device characteristics Over operating free-air temperature range, unless otherwise noted. Symbol Parameter Conditions Min Typ Max Unit tstartup start-up time device start-up time from power-on to HPD = HIGH; VGA monitor remains connected at power-on[1]; RST_N = HIGH; supply voltage within operating range to specified operating characteristics - - 100 ms tw(rst) reset pulse width device is supplied with valid supply voltage 10 - - s td(rst) reset delay time device reset delay time from RST_N toggling (LOW to HIGH) until HPD goes HIGH; VGA monitor remains connected at power-on[1]; supply voltage within operating range to specified operating characteristics - - 100 ms [1] VGA monitor remains connected at power-on — this condition is applicable only when PTN3356R1 is used in most interoperable (non-compliant) HPD mode (that is, CFG1/CFG2 is ‘01’ or ‘10’). PTN3356R1 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 16 July 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 19 of 38 PTN3356R1 NXP Semiconductors ROM-based low-power DP to VGA adapter 13.2 DisplayPort receiver main link Table 14. DisplayPort receiver main link characteristics[1] Over operating free-air temperature range, unless otherwise noted. Symbol Parameter Conditions Min Typ Max Unit UI unit interval for high bit rate (2.7 Gbit/s per lane) - 370 - ps for low bit rate (1.62 Gbit/s per lane) - 617 - ps [2] 0.0 - 0.5 % for high bit rate [3] 120 - - mV for reduced bit rate [3] 40 - - mV RX DC common mode voltage [4] 0 - 2.0 V IRX_SHORT RX short-circuit current limit [5] CRX AC coupling capacitor fRX_TRACK_BW_HBR jitter closed loop tracking bandwidth (High Bit Rate) fRX_TRACK_BW_RBR jitter closed loop tracking bandwidth (Reduced Bit Rate) fDOWN_SPREAD link clock down spreading VRX_DIFFp-p differential input peak-to-peak voltage VRX_DC_CM at RX package pins - - 50 mA 75 - 200 nF [6] 10 - 20 MHz [6] 5.4 - 20 MHz on DP Main Link and AUX inputs [1] Ref. 1 supersedes in case of any mismatch of specification items. [2] Up to 0.5 % down spread is supported. Modulation frequency range of 30 kHz to 33 kHz must be supported. [3] Informative; refer to Figure 8 for definition of differential voltage. [4] Common mode voltage is equal to Vbias_RX voltage. [5] Total drive current of the input bias circuit when it is shorted to its ground. [6] The measurements are always taken with PRBS7 test signal. Minimum CDR closed loop tracking bandwidth at the receiver when the input is a PRBS7 pattern. VD+ VDIFF_PRE VCM VDIFF VD- aaa-014244 pre-emphasis = 20Log(VDIFF_PRE / VDIFF) Fig 8. PTN3356R1 Product data sheet Definitions of pre-emphasis and differential voltage All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 16 July 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 20 of 38 PTN3356R1 NXP Semiconductors ROM-based low-power DP to VGA adapter 13.3 DisplayPort receiver AUX CH Table 15. DisplayPort receiver AUX CH characteristics[1] Over operating free-air temperature range, unless otherwise noted. Symbol UI Parameter Conditions unit interval tjit(cc) VAUX_DIFFp-p cycle-to-cycle jitter time AUX differential peak-to-peak voltage Min Typ Max Unit AUX [2] 0.4 0.5 0.6 s transmitting device [3] - - 0.04 UI receiving device [4] - - 0.05 UI transmitting device [5] 0.39 - 1.38 V receiving device [5] 0.32 - 1.36 V RAUX_TERM(DC) AUX CH termination DC resistance informative - 100 - VAUX_DC_CM AUX DC common-mode voltage [6] 0 - 2.0 V VAUX_TURN_CM AUX turnaround common-mode voltage [7] - - 0.3 V IAUX_SHORT AUX short-circuit current limit [8] - - 90 mA CAUX AUX AC coupling capacitor [9] 75 - 200 nF [1] Ref. 1 supersedes in case of any mismatch of specification items. [2] Results in the bit rate of 1 Mbit/s including the overhead of Manchester II coding. [3] Maximum allowable UI variation within a single transaction at connector pins of a transmitting device. Equal to 24 ns maximum. The transmitting device is a source device for a request transaction and a sink device for a reply transaction. [4] Maximum allowable UI variation within a single transaction at connector pins of a receiving device. Equal to 30 ns maximum. The transmitting device is a source device for a request transaction and a sink device for a reply transaction. [5] VAUX_DIFFp-p = 2 VAUX+ VAUX. [6] Common-mode voltage is equal to Vbias_TX (or Vbias_RX) voltage. [7] Steady-state common-mode voltage shift between transmit and receive modes of operation. [8] Total drive current of the transmitter when it is shorted to its ground. [9] The AUX CH AC coupling capacitor placed both on the DisplayPort source and sink devices. PTN3356R1 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 16 July 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 21 of 38 PTN3356R1 NXP Semiconductors ROM-based low-power DP to VGA adapter 13.4 HPD characteristics Table 16. HPD characteristics[1] Over operating free-air temperature range, unless otherwise noted. Symbol Parameter Conditions Min Typ Max Unit Output characteristics VOH HIGH-level output voltage IOH = 2 mA 2.4 - - V VOL LOW-level output voltage IOL = 2 mA - - 0.4 V IOSH HIGH-level short-circuit output current drive HIGH; cell connected to ground - - 16 mA IOSL LOW-level short-circuit output current drive LOW; cell connected to VDD - - 15 mA [1] Ref. 1 supersedes in case of any mismatch of specification items. 13.5 DDC/CFG1, CFG2 characteristics Table 17. DDC/CFG1, CFG2 characteristics VCC = 4.5 V to 5.5 V[1]. Over operating free-air temperature range, unless otherwise noted. Symbol Parameter Conditions Min Typ Max Unit Input characteristics VIH HIGH-level input voltage 0.7 VDD(3V3) - 5.5 V VIL LOW-level input voltage 0.5 - +0.3 VDD(3V3) V VI(hys) hysteresis of input voltage 0.1 VDD(3V3) - - V ILI input leakage current VI = 5 V - - 10 A Output characteristics IOL LOW-level output current VOL = 0.4 V 3.0 - - mA IO(sc) short-circuit output current drive LOW; cell connected to VDD(3V3) - - 40.0 mA Cio input/output capacitance VI = 3 V or 0 V VDD(3V3) = 3.3 V - 6 7 pF VDD(3V3) = 0 V - 6 7 pF [1] VCC is the pull-up voltage for DDC/CFG1, CFG2. [2] Table 17 applies to CFG1 and CFG2 pins as they operate as I2C-bus I/O but only used as CFG pins. PTN3356R1 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 16 July 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 22 of 38 PTN3356R1 NXP Semiconductors ROM-based low-power DP to VGA adapter 13.6 DAC Table 18. DAC characteristics Over operating free-air temperature range, unless otherwise noted. Symbol Parameter Conditions Min Typ Max Unit Nres(DAC) DAC resolution - - 8 bit fclk clock frequency Io(DAC) DAC output current variation - - 240 MHz - - 4 % INL integral non-linearity 1 0.25 +1 LSB DNL differential non-linearity 0.5 0.1 +0.5 LSB Vo(DAC)max maximum DAC output voltage 665 700 770 mV Co(DAC) DAC output capacitance - 3.5 - pF DAC noise injection ratio 1.5 - +1.5 % DAC-to-DAC 13.7 HSYNC, VSYNC characteristics Table 19. HSYNC and VSYNC characteristics Over operating free-air temperature range, unless otherwise noted. Symbol Parameter Conditions Min Typ Max Unit 2.4 - - V Output characteristics VOH HIGH-level output voltage IOH = 8 mA; VDD(3V3) = 3.3 V 10 % VOL LOW-level output voltage IOL = 8 mA IOSH HIGH-level short-circuit output current drive HIGH; cell connected to ground [1] IOSL LOW-level short-circuit output current drive LOW; cell connected to VDD [1] [1] - - 0.5 V - - 100 mA - - 100 mA The parameter values specified are simulated and absolute values. 13.8 Configuration pins CFG3, CFG5, TESTMODE Table 20. Configuration pins characteristics Over operating free-air temperature range, unless otherwise noted. Symbol Parameter Conditions Min Typ Max Unit - V Input characteristics VIH HIGH-level input voltage VIL LOW-level input voltage 0.7 VDD(3V3) - 0.3 VDD(3V3) V Weak pull-down characteristics Ipd pull-down current VI = VDD(3V3) 15 30 70 A Ipu pull-up current VI = 0 V 25 55 90 A Rext external resistance external resistor used on configuration pins - - 10 k PTN3356R1 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 16 July 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 23 of 38 PTN3356R1 NXP Semiconductors ROM-based low-power DP to VGA adapter 13.9 RST_N Table 21. RST_N characteristics Over operating free-air temperature range, unless otherwise noted. Symbol Parameter Conditions Min Typ Max Unit V Input characteristics VIH HIGH-level input voltage 0.7 VDD(3V3) - - VIL LOW-level input voltage - - 0.3 VDD(3V3) V 25 55 90 Ipu(RST_N) pull-up current on pin RST_N PTN3356R1 Product data sheet VI = 0 V All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 16 July 2015 A © NXP Semiconductors N.V. 2015. All rights reserved. 24 of 38 PTN3356R1 NXP Semiconductors ROM-based low-power DP to VGA adapter 14. Package outline HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm D B SOT617-3 A terminal 1 index area A A1 E detail X C e1 e 9 y1 C C A B C v w 1/2 e b y 16 L 17 8 e e2 Eh 1/2 e 24 1 terminal 1 index area 32 25 X Dh 0 2.5 Dimensions Unit(1) mm 5 mm scale A(1) A1 b max 0.05 0.30 nom 0.85 min 0.00 0.18 c D(1) Dh E(1) Eh 5.1 3.75 5.1 3.75 0.2 4.9 3.45 4.9 e e1 e2 0.5 3.5 3.5 L v w y y1 0.5 0.1 0.05 0.05 0.1 0.3 3.45 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline version SOT617-3 Fig 9. References IEC JEDEC JEITA sot617-3_po European projection Issue date 11-06-14 11-06-21 MO-220 Package outline SOT617-3 (HVQFN32) PTN3356R1 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 16 July 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 25 of 38 PTN3356R1 NXP Semiconductors ROM-based low-power DP to VGA adapter 15. Packing information 15.1 Packing method Barcode label Dry-agent Bag ESD print Relative humidity indicator Moisture caution print ESD embossed Tape Reel assembly Barcode label Guard band Printed plano box Cover tape QA seal Carrier tape Space for additional label Preprinted ESD warning Barcode label Drypack ID sticker Printed plano box aaa-005677 Fig 10. Reel dry pack for SMD Table 22. Reel dimensions d w (mm)[1] SPQ/PQ (pcs) Reels per box Outer box dimensions l w h (mm) 330 12 6000 1 341 338 39 [1] PTN3356R1 Product data sheet Dimensions and quantities d = reel diameter; w = tape width. All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 16 July 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 26 of 38 PTN3356R1 NXP Semiconductors ROM-based low-power DP to VGA adapter 15.2 Product orientation pin 1 aaa-006538 Pin 1 is in quadrant 2. Fig 11. Product orientation in carrier tape 15.3 Carrier tape dimensions 4 mm W K0 A0 B0 P1 T direction of feed 001aao148 Fig 12. Carrier tape dimensions Table 23. Carrier tape dimensions In accordance with IEC 60286-3. PTN3356R1 Product data sheet A0 (mm) B0 (mm) K0 (mm) T (mm) P1 (mm) W (mm) 5.3 0.1 5.3 0.1 1.10 0.1 0.30 0.05 8 0.1 12 0.3 All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 16 July 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 27 of 38 PTN3356R1 NXP Semiconductors ROM-based low-power DP to VGA adapter 15.4 Reel dimensions A Z W2 B ØC ØD detail Z 001aao149 Fig 13. Schematic view of reel Table 24. Reel dimensions In accordance with IEC 60286-3. PTN3356R1 Product data sheet A [nom] (mm) W2 [max] (mm) B [min] (mm) C [min] (mm) D [min] (mm) 330 18.4 1.5 12.8 20.2 All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 16 July 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 28 of 38 PTN3356R1 NXP Semiconductors ROM-based low-power DP to VGA adapter 15.5 Barcode label Fixed text Country of origin i.e. "Made in....." or "Diffused in EU [+] Assembled in...... Packing unit (PQ) identification 2nd traceability lot number* 2nd (youngest) date code* 2nd Quantity* Traceability lot number Date code With linear barcode Quantity With linear barcode Type number NXP 12NC With linear barcode NXP SEMICONDUCTORS MADE IN >COUNTRY< [PRODUCT INFO] (Q) QTY Optional product information* Re-approval date code* Origin code Product Manufacturing Code MSL at the Peak Body solder temperature with tin/lead* MSL at the higher lead-free Peak Body Temperature* 2D matrix with all data (including the data identifiers) HALOGEN FREE (30P) TYPE RoHS compliant (1P) CODENO Additional info if halogen free product Additional info on RoHS (33T) PUID: B.0987654321 (30T) LOT2 (31D) REDATE (30D) DATE2 (32T) ORIG (30Q) QTY2 (31T) PMC (31P) MSL/PBT (1T) LOT MSL/PBT (9D) DATE Lead-free symbol 001aak714 Fig 14. Example of typical box and reel information barcode label Table 25. PTN3356R1 Product data sheet Barcode label dimensions Box barcode label l w (mm) Reel barcode label l w (mm) 100 75 100 75 All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 16 July 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 29 of 38 PTN3356R1 NXP Semiconductors ROM-based low-power DP to VGA adapter 16. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 16.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 16.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 16.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities PTN3356R1 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 16 July 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 30 of 38 PTN3356R1 NXP Semiconductors ROM-based low-power DP to VGA adapter 16.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 15) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 26 and 27 Table 26. SnPb eutectic process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 < 2.5 235 220 2.5 220 220 Table 27. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 15. PTN3356R1 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 16 July 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 31 of 38 PTN3356R1 NXP Semiconductors ROM-based low-power DP to VGA adapter temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 15. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. PTN3356R1 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 16 July 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 32 of 38 PTN3356R1 NXP Semiconductors ROM-based low-power DP to VGA adapter 17. Soldering: PCB footprints Footprint information for reflow soldering of HVQFN32 package SOT617-3 Hx Gx see detail X P nSPx By Hy Gy SLy Ay nSPy C D SLx Bx Ax 0.60 solder land 0.30 solder paste detail X occupied area Dimensions in mm P Ax Ay Bx By C D Gx Gy Hx Hy SLx SLy nSPx nSPy 0.5 5.95 5.95 4.25 4.25 0.85 0.27 5.25 5.25 6.2 6.2 3.75 3.75 3 3 Issue date 11-11-15 11-11-20 sot617-3_fr Fig 16. PCB footprint for SOT617-3 (HVQFN32); reflow soldering PTN3356R1 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 16 July 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 33 of 38 PTN3356R1 NXP Semiconductors ROM-based low-power DP to VGA adapter 18. Abbreviations Table 28. PTN3356R1 Product data sheet Abbreviations Acronym Description AUX CH Auxiliary Channel BER Bit Error Rate bpc bits per color bpp bits per pixel BoM Bill of Materials CDM Charged-Device Model CEA Consumer Electronic Association CMOS Complementary Metal-Oxide Semiconductor CVT Coordinated Video Timings CVT RB CVT Reduced Blanking DAC Digital-to-Analog Converter DDC Display Data Channel DJ Deterministic Jitter DP DisplayPort (VESA) DPCD DisplayPort Configuration Data ECC Error Correction Code EDID Extended Display Identification Data eDP embedded DisplayPort ESD ElectroStatic Discharge HBM Human Body Model HBR High Bit Rate HDCP High-bandwidth Digital Content Protection HPD Hot Plug Detect I2C-bus Inter-Integrated Circuit bus IEC International Electrotechnical Commission I/O Input/Output LSB Least Significant Bit MCCS Monitor Control Command Set (VESA) MSB Most Significant Bit QXGA Quad eXtended Graphics Array RB Reduced Blanking RBR Reduced Bit Rate RGB Red/Green/Blue ROM Read-Only Memory SSC Spread Spectrum Clocking SVGA Super Video Graphics Array SXGA Super eXtended Graphics Array TJ Total Jitter UI Unit Interval All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 16 July 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 34 of 38 PTN3356R1 NXP Semiconductors ROM-based low-power DP to VGA adapter Table 28. Abbreviations …continued Acronym Description UXGA Ultra eXtended Graphics Array VESA Video Electronics Standards Association VGA Video Graphics Array VSIS Video Signal Interface Standard WUXGA Wide Ultra eXtended Graphics Array XGA eXtended Graphics Array 19. References [1] VESA DisplayPort Standard — Version 1, Revision 2a; March 2012 [2] Display Data Channel Command Interface Standard — Version 1.1; October 29, 2004 [3] Video Signal Standard (VSIS) — Version 1, Rev. 2; December 12, 2002 [4] IEC 61000-4-2, Electromagnetic compatibility (EMC) - Part 4-2: Testing and measurement techniques — ElectroStatic Discharge (ESD) immunity test, edition 2.0, 2008-12 20. Revision history Table 29. Revision history Document ID Release date Data sheet status Change notice Supersedes PTN3356R1 v.2.1 20150716 Product data sheet - PTN3356R1 v.2 Modifications: PTN3356R1 v.2 Modifications: PTN3356R1 v.1 PTN3356R1 Product data sheet • Removed “COMPANY CONFIDENTIAL” watermark 20150629 • • • • Product data sheet - PTN3356R1 v.1 Updated Figure 7 Changed data sheet status to Product ESD HBM changed to 7 kV Table 2: Added 500 piece minimum order quantity 20140911 Objective data sheet - All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 16 July 2015 - © NXP Semiconductors N.V. 2015. All rights reserved. 35 of 38 PTN3356R1 NXP Semiconductors ROM-based low-power DP to VGA adapter 21. Legal information 21.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 21.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 21.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. PTN3356R1 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 16 July 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 36 of 38 PTN3356R1 NXP Semiconductors ROM-based low-power DP to VGA adapter Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 21.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 22. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] PTN3356R1 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 16 July 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 37 of 38 PTN3356R1 NXP Semiconductors ROM-based low-power DP to VGA adapter 23. Contents 1 2 2.1 2.2 2.3 2.4 2.5 3 4 4.1 5 6 6.1 6.2 7 7.1 7.2 7.3 7.3.1 7.4 7.5 7.6 7.6.1 8 9 10 10.1 10.2 10.3 10.4 11 12 13 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9 14 15 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 VESA-compliant DisplayPort converter . . . . . . 1 VESA-compliant eDP extensions . . . . . . . . . . . 1 DDC channel output . . . . . . . . . . . . . . . . . . . . . 1 Analog video output . . . . . . . . . . . . . . . . . . . . . 2 General features . . . . . . . . . . . . . . . . . . . . . . . . 2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 7 DisplayPort Main Link . . . . . . . . . . . . . . . . . . . . 7 DisplayPort auxiliary channel (AUX CH). . . . . . 7 DPCD registers. . . . . . . . . . . . . . . . . . . . . . . . . 8 PTN3356R1 specific DPCD register settings . . 8 VGA monitor detection . . . . . . . . . . . . . . . . . . 10 EDID handling . . . . . . . . . . . . . . . . . . . . . . . . 10 Triple 8-bit video DACs and VGA outputs . . . 10 DAC reference resistor . . . . . . . . . . . . . . . . . . 10 Power-up and reset . . . . . . . . . . . . . . . . . . . . . 11 Configurability . . . . . . . . . . . . . . . . . . . . . . . . . 11 Application design-in information . . . . . . . . . 12 Display resolution . . . . . . . . . . . . . . . . . . . . . . 15 Power supply filter . . . . . . . . . . . . . . . . . . . . . 16 DAC terminations . . . . . . . . . . . . . . . . . . . . . . 16 Timing reference. . . . . . . . . . . . . . . . . . . . . . . 17 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 18 Recommended operating conditions. . . . . . . 18 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 19 Current consumption, power dissipation and thermal characteristics . . . . . . . . . . . . . . . . . . 19 DisplayPort receiver main link . . . . . . . . . . . . 20 DisplayPort receiver AUX CH . . . . . . . . . . . . . 21 HPD characteristics . . . . . . . . . . . . . . . . . . . . 22 DDC/CFG1, CFG2 characteristics . . . . . . . . . 22 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 HSYNC, VSYNC characteristics. . . . . . . . . . . 23 Configuration pins CFG3, CFG5, TESTMODE 23 RST_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 25 Packing information . . . . . . . . . . . . . . . . . . . . 26 15.1 15.2 15.3 15.4 15.5 16 16.1 16.2 16.3 16.4 17 18 19 20 21 21.1 21.2 21.3 21.4 22 23 Packing method . . . . . . . . . . . . . . . . . . . . . . . Product orientation . . . . . . . . . . . . . . . . . . . . . Carrier tape dimensions . . . . . . . . . . . . . . . . . Reel dimensions . . . . . . . . . . . . . . . . . . . . . . Barcode label . . . . . . . . . . . . . . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering. . . . . . . . . . . . . . . Wave soldering . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering . . . . . . . . . . . . . . . . . . . . . . Soldering: PCB footprints . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 27 27 28 29 30 30 30 30 31 33 34 35 35 36 36 36 36 37 37 38 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP Semiconductors N.V. 2015. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 16 July 2015 Document identifier: PTN3356R1