Data Sheet

INTEGRATED CIRCUITS
DATA SHEET
PCF8584
I2C-bus controller
Product specification
Supersedes data of 1997 Mar 19
File under Integrated Circuits, IC12
1997 Oct 21
Philips Semiconductors
Product specification
I2C-bus controller
PCF8584
CONTENTS
7
SOFTWARE FLOWCHART EXAMPLES
1
FEATURES
7.1
7.2
Initialization
Implementation
2
GENERAL DESCRIPTION
8
I2C-BUS TIMING DIAGRAMS
3
ORDERING INFORMATION
9
LIMITING VALUES
4
BLOCK DIAGRAM
10
HANDLING
5
PINNING
11
DC CHARACTERISTICS
6
FUNCTIONAL DESCRIPTION
12
I2C-BUS TIMING SPECIFICATIONS
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.8.1
6.8.1.1
6.8.1.2
6.8.1.3
6.8.1.4
6.8.1.5
6.8.1.6
6.8.2
6.8.2.1
6.8.2.2
6.8.2.3
6.8.2.4
6.8.2.5
6.8.2.6
6.8.2.7
6.9
6.10
6.11
6.11.1
6.11.2
6.12
6.12.1
6.12.2
6.12.3
General
Interface Mode Control (IMC)
Set-up registers S0', S2 and S3
Own address register S0'
Clock register S2
Interrupt vector S3
Data shift register/read buffer S0
Control/status register S1
Register S1 control section
PIN (Pending Interrupt Not)
ESO (Enable Serial Output)
ES1 and ES2
ENI
STA and STO
ACK
Register S1 status section
PIN bit
STS
BER
LRB/AD0
AAS
LAB
BB
Multi-master operation
Reset
Comparison to the MAB8400 I2C-bus interface
Deleted functions
added functions
Special function modes
Strobe
Long-distance mode
Monitor mode
13
PARALLEL INTERFACE TIMING
14
APPLICATION INFORMATION
14.1
Application Notes
15
PACKAGE OUTLINES
16
SOLDERING
16.1
16.2
16.2.1
16.2.2
16.3
16.3.1
16.3.2
16.3.3
Introduction
DIP
Soldering by dipping or by wave
Repairing soldered joints
SO
Reflow soldering
Wave soldering
Repairing soldered joints
17
DEFINITIONS
18
LIFE SUPPORT APPLICATIONS
1997 Oct 21
19 PURCHASE OF PHILIPS I2C COMPONENTS
2
Philips Semiconductors
Product specification
I2C-bus controller
1
PCF8584
FEATURES
• Parallel-bus to
2
I2C-bus
protocol converter and interface
GENERAL DESCRIPTION
The PCF8584 is an integrated circuit designed in CMOS
technology which serves as an interface between most
standard parallel-bus microcontrollers/microprocessors
and the serial I2C-bus. The PCF8584 provides both master
and slave functions.
• Compatible with most parallel-bus
microcontrollers/microprocessors including 8049, 8051,
6800, 68000 and Z80
• Both master and slave functions
Communication with the I2C-bus is carried out on a
byte-wise basis using interrupt or polled handshake.
It controls all the I2C-bus specific sequences, protocol,
arbitration and timing. The PCF8584 allows parallel-bus
systems to communicate bidirectionally with the I2C-bus.
• Automatic detection and adaption to bus interface type
• Programmable interrupt vector
• Multi-master capability
• I2C-bus monitor mode
• Long-distance mode (4-wire)
• Operating supply voltage 4.5 to 5.5 V
• Operating temperature range: −40 to +85 °C.
3
ORDERING INFORMATION
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
PCF8584P
DIP20
plastic dual in-line package; 20 leads (300 mil)
SOT146-1
PCF8584T
SO20
plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
1997 Oct 21
3
Philips Semiconductors
Product specification
I2C-bus controller
4
PCF8584
BLOCK DIAGRAM
PARALLEL BUS
handbook, full pagewidth
SDA/
(3)
SDA OUT
2
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
V DD
V SS
15
14
13
12
11
9
8
7
20
10
MSB
DIGITAL
FILTER
READ BUFFER
read
only
DATA SHIFT REGISTER S0 AND READ BUFFER
write
only
SHIFT REGISTER
8
DATA CONTROL
X
COMPARATOR S0, S0'
(1)
8
MSB
(1)
LSB
X
OWN ADDRESS S0'
8
PCF8584
INTERRUPT VECTOR S3
SCL/
(3)
SCL IN
3
DIGITAL
FILTER
CLOCK REGISTER S2
0
0
0
default: 00H 80XX
0FH 68XXX
8
S24
S23
S22
S21
S20
CLOCK REGISTER S2
8
REGISTER S1
CONTROL STATUS
PIN
SCL CONTROL
ES0
ES1
ES2
ENI
STA
STO
ACK
write only
CONTROL STATUS REGISTER S1
PIN
CLOCK PRESCALER
SCL MULTIPLEXER
BUS BUSY LOGIC
ARBITRATION LOGIC
19
RESET/
STROBE
(O.C.)
17
CS
0
STS
BER
AD0/
LRB
6
A0
18
16
WR (R/W)
(2)
RD (DTACK)
LAB
BB
read only
REGISTER ACCESS CONTROL
BUS BUFFER CONTROL
INTERRUPT CONTROL
RESET/STROBE CONTROL
PARALLEL BUS CONTROL
(2)
5
4
1
INT
(3)
SCL OUT
IACK
CLK
(3)
SDA IN
MBD908 - 1
(1) X = don’t care.
(2) Pin mnemonics between parenthesis indicate the 68000 mode pin designations.
(3) These pin mnemonics represent the long-distance mode pin designations.
Fig.1 Block diagram.
1997 Oct 21
AAS
4
Philips Semiconductors
Product specification
I2C-bus controller
5
PCF8584
PINNING
SYMBOL
PIN
I/O
DESCRIPTION
CLK
1
I
SDA or
SDA OUT
2
I/O
I2C-bus serial data input/output (open-drain). Serial data output in long-distance
mode.
SCL or SCL IN
3
I/O
I2C-serial clock input/output (open-drain). Serial clock input in long-distance mode.
IACK or
SDA IN
4
I
Interrupt acknowledge input (internal pull-up); when this signal is asserted the
interrupt vector in register S3 will be available at the bus Port if the ENI flag is set.
Serial data input in long-distance mode.
INT or
SCL OUT
5
O
Interrupt output (open-drain); this signal is enabled by the ENI flag in register S1.
It is asserted when the PIN flag is reset. (PIN is reset after 1 byte is transmitted or
received over the I2C-bus). Serial clock output in long-distance mode.
A0
6
I
Register select input (internal pull-up); this input selects between the control/status
register and the other registers. Logic 1 selects register S1, logic 0 selects one of
the other registers depending on bits loaded in ESO, ES1 and ES2 of register S1.
DB0
7
I/O
bidirectional 8-bit bus Port 0
DB1
8
I/O
bidirectional 8-bit bus Port 1
DB2
9
I/O
bidirectional 8-bit bus Port 2
VSS
10
−
DB3
11
I/O
bidirectional 8-bit bus Port 3
DB4
12
I/O
bidirectional 8-bit bus Port 4
DB5
13
I/O
bidirectional 8-bit bus Port 5
DB6
14
I/O
bidirectional 8-bit bus Port 6
DB7
15
I/O
bidirectional 8-bit bus Port 7
RD (DTACK)
16
I/(O)
CS
17
I
chip select input (internal pull-up)
WR (R/W)
18
I
WR is the write control input for MAB8048, MAB8051, or Z80-types
(internal pull-up). R/W control input for 68000-types.
RESET/
STROBE
19
I/O
VDD
20
−
1997 Oct 21
clock input from microcontroller clock generator (internal pull-up)
ground
RD is the read control input for MAB8049, MAB8051 or Z80-types. DTACK is the
data transfer control output for 68000-types (open-drain).
Reset input (open-drain); this input forces the I2C-bus controller into a predefined
state; all flags are reset, except PIN, which is set. Also functions as strobe output.
supply voltage
5
Philips Semiconductors
Product specification
I2C-bus controller
PCF8584
Table 1
TYPE
handbook, halfpage
CLK
1
20 VDD
SDA or SDA OUT
2
19 RESET / STROBE
(1)
SCL or SCL IN
3
18 WR (R/W)
IACK or SDA IN
4
17 CS
INT or SCL OUT
5
16 RD (DTACK)
A0
6
15 DB7
DB0
7
14 DB6
DB1
8
13 DB5
DB2
9
12 DB4
VSS 10
11 DB3
(1) Pin mnemonics between parenthesis indicate the 68000 mode
pin designations.
R
DTACK
IACK
8048/
8051
no
yes
yes
no
no
68000
yes
no
no
yes
yes
Z80
no
yes
yes
no
yes
Register S0 performs all serial-to-parallel interfacing with
the I2C-bus.
Fig.2 Pin configuration.
Register S1 contains I2C-bus status information required
for bus access and/or monitoring.
FUNCTIONAL DESCRIPTION
6.2
General
Interface Mode Control (IMC)
Selection of either an 80XX mode or 68000 mode
interface is achieved by detection of the first WR-CS signal
sequence. The concept takes advantage of the fact that
the write control input is common for both types of
interfaces. An 80XX-type interface is default. If a
HIGH-to-LOW transition of WR (R/W) is detected while CS
is HIGH, the 68000-type interface mode is selected and
the DTACK output is enabled. Care must be taken that WR
and CS are stable after reset.
The PCF8584 acts as an interface device between
standard high-speed parallel buses and the serial I2C-bus.
On the I2C-bus, it can act either as master or slave.
Bidirectional data transfer between the I2C-bus and the
parallel-bus microcontroller is carried out on a byte-wise
basis, using either an interrupt or polled handshake.
Interface to either 80XX-type (e.g. 8048, 8051, Z80) or
68000-type buses is possible. Selection of bus type is
automatically performed (see Section 6.2).
1997 Oct 21
WR
The remaining two registers function as double registers
(data buffer/shift register S0, and control/status
register S1) which are used during actual data
transmission/reception. By using these double registers,
which are separately write and read accessible, overhead
for register access is reduced. Register S0 is a
combination of a shift register and data buffer.
MLA012 - 1
6.1
R/W
The structure of the PCF8584 is similar to that of the
I2C-bus interface section of the Philips’
MABXXXX/PCF84(C)XX-series of microcontrollers, but
with a modified control structure. The PCF8584 has five
internal register locations. Three of these (own address
register S0', clock register S2 and interrupt vector S3) are
used for initialization of the PCF8584. Normally they are
only written once directly after resetting of the PCF8584.
(1)
PCF8584
6
Control signals utilized by the PCF8584 for
microcontroller/microprocessor interfacing
6
Philips Semiconductors
Product specification
I2C-bus controller
PCF8584
I2C-bus
SCL
(1.5 MHz)
EN
ENRD
D
EN
D
handbook, full pagewidth
SIO DIVIDER
(S21 and S20)
DIVIDER
(S24, S23, S22)
/2, 3, 4, 5, 8
FILTER
t = 16CLK
MBE706
RESET
STROBE
CS
A0
WR/
RD/
R/W DTACK
INT
IACK
CLK
(50 : 50)
mode locked
handbook, full pagewidth
mode select
R/W
(1)
CS
DTACK
mode select
WR
(2)
CS
MBE707
(1) Bus timing; 68000 mode write cycle.
(2) Bus timing; 80XX mode.
Fig.3 68000/80XX timing sequence utilized by the Interface Mode Control (IMC).
1997 Oct 21
7
Philips Semiconductors
Product specification
I2C-bus controller
6.3
PCF8584
Programming of S2 is accomplished via the parallel-bus
when A0 = LOW, with the appropriate bit combinations set
in control status register S1 (S1 is written when
A0 = HIGH). Bit combinations for accessing all registers
are given in Table 5.
Set-up registers S0', S2 and S3
Registers S0', S2 and S3 are used for initialization of the
PCF8584 (see Fig.5 ‘Initialization sequence’ flowchart).
6.4
Own address register S0'
When the PCF8584 is addressed as slave, this register
must be loaded with the 7-bit I2C-bus address to which the
PCF8584 is to respond. During initialization, the own
address register S0' must be written to, regardless
whether it is later used. The Addressed As Slave (AAS) bit
in status register S1 is set when this address is received
(the value in S0 is compared with the value in S0'). Note
that the S0 and S0' registers are offset by one bit; hence,
programming the own address register S0' with a value of
55H will result in the value AAH being recognized as the
PCF8584’s slave address (see Fig.1).
Table 3
Programming of S0' is accomplished via the parallel-bus
when A0 is LOW, with the appropriate bit combinations set
in control status register S1 (S1 is written when
pin A0 = HIGH). Bit combinations for accessing all
registers are given in Table 5. After reset, S0' has default
address 00H (PCF8584 is thus initially in monitor mode,
see Section 6.12.3).
Note
6.5
INTERNAL CLOCK FREQUENCY
6.6
S21
S20
0
0
90
0
1
45
1
0
11
1
1
1.5
0
X(1)
3
1
0
0
4.43
1
0
1
6
1
1
0
8
1
1
1
12
Interrupt vector S3
• Vector is ‘0FH’ in 68000 mode.
On reset the PCF8584 is in the 80XX mode, thus the
default interrupt vector is ‘00H’.
6.7
Data shift register/read buffer S0
Register S0 acts as serial shift register and read buffer
interfacing to the I2C-bus. All read and write operations
to/from the I2C-bus are done via this register. S0 is a
combination of a shift register and a data buffer; parallel
data is always written to the shift register, and read from
the data buffer. I2C-bus data is always shifted in or out of
shift register S0.
S22, S23 and S24 are used for control of the internal clock
prescaler. Due to the possibility of varying microcontroller
clock signals, the prescaler can be programmed to adapt
to 5 different clock rates, thus providing a constant internal
clock. This is required to provide a stable time base for the
SCL generator and the digital filters associated with the
I2C-bus signals SCL and SDA. Selection for adaption to
external clock rates is shown in Table 3.
1997 Oct 21
S22
X(1)
• Vector is ‘00H’ in 80XX mode
Register S2 selection of SCL frequency
APPROXIMATE SCL
FREQUENCY fSCL (kHz)
S23
The interrupt vector register provides an 8-bit
user-programmable vector for vectored-interrupt
microcontrollers. The vector is sent to the bus port
(DB7 to DB0) when an interrupt acknowledge signal is
asserted and the ENI (enable interrupt) flag is set. Default
vector values are:
Register S2 provides control over chip clock frequency
and SCL clock frequency. S20 and S21 provide a selection
of 4 different I2C-bus SCL frequencies which are shown in
Table 2. Note that these SCL frequencies are only
obtained when bits S24, S23 and S22 are programmed to
the correct input clock frequency (fclk).
BIT
fclk (MHz)
S24
1. X = don’t care.
Clock register S2
Table 2
Register S2 selection of clock frequency
8
Philips Semiconductors
Product specification
I2C-bus controller
PCF8584
to/from microcontroller parallel bus
andbook, full pagewidth
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Read
only
Read Buffer
Data Shift Register S0 and Read Buffer
Shift register
to/from
I2C-Bus SDA line
Write
only
MBE705
Fig.4 Data shift register/bus buffer S0.
In receiver mode the data from the shift register is copied to the read buffer during the acknowledge phase. Further
reception of data is inhibited (SCL held LOW) until the S0 read buffer is read (see Section 6.8.1.1).
In the transmitter mode data is transmitted to the I2C-bus as soon as it is written to the S0 shift register if the serial I/O is
enabled (ESO = 1).
Remarks:
1. A minimum of 6 clock cycles must elapse between consecutive parallel-bus accesses to the PCF8584 when the
I2C-bus controller operates at 8 or 12 MHz. This may be reduced to 3 clock cycles for lower operating frequencies.
2. To start a read operation immediately after a write, it is necessary to read the S0 read buffer in order to invoke
reception of the first byte (‘dummy read’ of the address). Immediately after the acknowledgement, this first byte will
be transferred from the shift register to the read buffer. The next read will then transfer the correct value of the first
byte to the microcontroller bus (see Fig.7).
6.8
Control/status register S1
Register S1 controls I2C-bus operation and provides I2C-bus status information. Register S1 is accessed by a HIGH
signal on register select input A0. For more efficient communication between microcontroller/processor and the I2C-bus,
register S1 has separate read and write functions for all bit positions (see Fig.3). The write-only section provides register
access control and control over I2C-bus signals, while the read-only section provides I2C-bus status information.
Table 4
Control/status register S1
CONTROL/STATUS
Control(1)
Status(2)
BITS
PIN
ESO
ES1
ES2
ENI
STA
STO
ACK
write only
PIN
0(3)
STS
BER
AD0/LRB
AAS
LAB
BB
read only
Notes
1. For further information see Section 6.8.1.
2. For further information see Section 6.8.2.
3. Logic 1 if not-initialized.
1997 Oct 21
MODE
9
Philips Semiconductors
Product specification
I2C-bus controller
6.8.1
PCF8584
REGISTER S1 CONTROL SECTION
The write-only section of S1 enables access to registers S0, S0', S1, S2 and S3, and controls I2C-bus operation; see
Table 4.
6.8.1.1
PIN (Pending Interrupt Not)
When the PIN bit is written with a logic 1, all status bits are reset to logic 0. This may serve as a software reset function
(see Figs 5 to 9). PIN is the only bit in S1 which may be both read and written to. PIN is mostly used as a status bit for
synchronizing serial communication, see Section 6.8.2.
6.8.1.2
ESO (Enable Serial Output)
ESO enables or disables the serial I2C-bus I/O. When ESO is LOW, register access for initialization is possible. When
ESO is HIGH, I2C-bus communication is enabled; communication with serial shift register S0 is enabled and the S1 bus
status bits are made available for reading.
Table 5
Register access control; ESO = 0 (serial interface off) and ESO = 1 (serial interface on)
INTERNAL REGISTER ADDRESSING 2-WIRE MODE
A0
ES1
IACK
ES2
FUNCTION
ESO = 0; serial interface off (see note 1)
1
0
X
1(2)
R/W S1: control
0
0
0
1(2)
R/W S0': (own address)
1
1(2)
R/W S3: (interrupt vector)
0
1(2)
R/W S2: (clock register)
W S1: control
0
0
0
1
ESO = 1; serial interface on
1
0
X
1
1
0
X
1
R S1; status
0
0
0
1
R/W S0: (data)
0
0
1
1
R/W S3: (interrupt vector)
X
0
X
0
R S3: (interrupt vector ACK cycle))
Notes
1. With ESO = 0, bits ENI, STA, STO and ACK of S1 can be read for test purposes.
2. ‘X’ if ENI = 0.
6.8.1.3
ES1 and ES2
ES1 and ES2 control selection of other registers for initialization and control of normal operation. After these bits are
programmed for access to the desired register (shown in Table 5), the register is selected by a logic LOW level on
register select pin A0.
6.8.1.4
ENI
This bit enables the external interrupt output INT, which is generated when the PIN bit is active (logic 0).
This bit must be set to logic 0 before entering the long-distance mode, and remain at logic 0 during operation in
long-distance mode.
1997 Oct 21
10
Philips Semiconductors
Product specification
I2C-bus controller
6.8.1.5
PCF8584
STA and STO
These bits control the generation of the I2C-bus START condition and transmission of slave address and R/W bit,
generation of repeated START condition, and generation of the STOP condition (see Table 7).
Table 6
Register access control; ESO = 1 (serial interface on) and ES1 = 1; long-distance (4-wire) mode; note 1
INTERNAL REGISTER ADDRESSING: LONG-DISTANCE (4-WIRE) MODE
A0
ES1
ES2
IACK
1
1
X
1
W S1: control
1
1
X
X
R S1; status
0
1
X
X
R/W S0; (data)
FUNCTION
Note
1. Trying to read from or write to registers other than S0 and S1 (setting ESO = 0) brings the PCF8584 out of the
long-distance mode.
Table 7
Instruction table for serial bus control
STA
STO
PRESENT
MODE
FUNCTION
1
0
SLV/REC
START
1
0
MST/TRM
REPEAT
START
0
1
MST/REC;
MST/TRM
STOP READ;
STOP WRITE
1
1
MST
DATA
CHAINING
0
0
ANY
NOP
OPERATION
transmit START + address, remain
MST/TRM if R/W = 0;
go to MST/REC if R/W = 1
same as for SLV/REC
transmit STOP go to SLV/REC mode; note 1
send STOP, START and address after last
master frame without STOP sent; note 2
no operation; note 3
Notes
1. In master receiver mode, the last byte must be terminated with ACK bit HIGH (‘negative acknowledge’).
2. If both STA and STO are set HIGH simultaneously in master mode, a STOP condition followed by a START
condition + address will be generated. This allows ‘chaining’ of transmissions without relinquishing bus control.
3. All other STA and STO mode combinations not mentioned in Table 7 are NOPs.
6.8.1.6
ACK
This bit must be set normally to a logic 1. This causes the I2C-bus controller to send an acknowledge automatically after
each byte (this occurs during the 9th clock pulse). The bit must be reset (to logic 0) when the I2C-bus controller is
operating in master/receiver mode and requires no further data to be sent from the slave transmitter. This causes a
negative acknowledge on the I2C-bus, which halts further transmission from the slave device.
6.8.2
REGISTER S1 STATUS SECTION
The read-only section of S1 enables access to I2C-bus status information; see Table 4.
1997 Oct 21
11
Philips Semiconductors
Product specification
I2C-bus controller
6.8.2.1
PCF8584
• In receiver mode, PIN is set to logic 0 (active) on
completion of each received byte. Subsequently, the
SCL line will be held LOW until PIN is set to logic 1.
PIN bit
‘Pending Interrupt Not’ (MSB of register S1) is a status flag
which is used to synchronize serial communication and is
set to logic 0 whenever the PCF8584 requires servicing.
The PIN bit is normally read in polled applications to
determine when an I2C-bus byte transmission/reception is
completed. The PIN bit may also be written, see
Section 6.8.1.
• In receiver mode, when register S0 is read, PIN is set to
logic 1 (inactive).
• In slave receiver mode, an I2C-bus STOP condition will
set PIN = 0 (active).
• PIN = 0 if a bus error (BER) occurs.
Each time a serial data transmission is initiated (by setting
the STA bit in the same register), the PIN bit will be set to
logic 1 automatically (inactive). When acting as
transmitter, PIN is also set to logic 1 (inactive) each time
S0 is written. In receiver mode, the PIN bit is automatically
set to logic 1 (inactive) each time the data register S0 is
read.
6.8.2.2
When in slave receiver mode, this flag is asserted when an
externally generated STOP condition is detected (used
only in slave receiver mode).
6.8.2.3
After transmission or reception of one byte on the I2C-bus
(9 clock pulses, including acknowledge), the PIN bit will be
automatically reset to logic 0 (active) indicating a complete
byte transmission/reception. When the PIN bit is
subsequently set to logic 1 (inactive), all status bits will be
reset to logic 0. PIN is also set to zero on a BER (bus error)
condition.
BER
Bus error; a misplaced START or STOP condition has
been detected. Resets BB (to logic 1; inactive), sets
PIN = 0 (active).
6.8.2.4
LRB/AD0
‘Last Received Bit’ or ‘Address 0 (General Call) bit’. This
status bit serves a dual function, and is valid only while
PIN = 0:
In polled applications, the PIN bit is tested to determine
when a serial transmission/reception has been completed.
When the ENI bit (bit 4 of write-only section of register S1)
is also set to logic 1 the hardware interrupt is enabled.
In this case, the PIN flag also triggers an external interrupt
(active LOW) via the INT output each time PIN is reset to
logic 0 (active).
1. LRB holds the value of the last received bit over the
I2C-bus while AAS = 0 (not addressed as slave).
Normally this will be the value of the slave
acknowledgement; thus checking for slave
acknowledgement is done via testing of the LRB.
2. AD0; when AAS = 1 (‘Addressed As Slave’ condition),
the I2C-bus controller has been addressed as a slave.
Under this condition, this bit becomes the ‘AD0’ bit and
will be set to logic 1 if the slave address received was
the ‘general call’ (00H) address, or logic 0 if it was the
I2C-bus controller’s own slave address.
When acting as slave transmitter or slave receiver, while
PIN = 0, the PCF8584 will suspend I2C-bus transmission
by holding the SCL line LOW until the PIN bit is set to
logic 1 (inactive). This prevents further data from being
transmitted or received until the current data byte in S0 has
been read (when acting as slave receiver) or the next data
byte is written to S0 (when acting as slave transmitter).
6.8.2.5
PIN bit summary:
AAS
‘Addressed As Slave’ bit. Valid only when PIN = 0. When
acting as slave receiver, this flag is set when an incoming
address over the I2C-bus matches the value in own
address register S0' (shifted by one bit, see Section 6.4),
or if the I2C-bus ‘General Call’ address (00H) has been
received (‘General Call’ is indicated when AD0 status bit is
also set to logic 1, see Section 6.8.2.4).
• The PIN bit can be used in polled applications to test
when a serial transmission has been completed. When
the ENI bit is also set, the PIN flag sets the external
interrupt via the INT output.
• Setting the STA bit (start bit) will set PIN = 1 (inactive).
• In transmitter mode, after successful transmission of
one byte on the I2C-bus the PIN bit will be automatically
reset to logic 0 (active) indicating a complete byte
transmission.
6.8.2.6
LAB
‘Lost Arbitration’ Bit. This bit is set when, in multi-master
operation, arbitration is lost to another master on the
I2C-bus.
• In transmitter mode, PIN is set to logic 1 (inactive) each
time register S0 is written.
1997 Oct 21
STS
12
Philips Semiconductors
Product specification
I2C-bus controller
6.8.2.7
PCF8584
BB
6.11.1
DELETED FUNCTIONS
‘Bus Busy’ bit. This is a read-only flag indicating when the
I2C-bus is in use. A zero indicates that the bus is busy, and
access is not possible. This bit is set/reset (logic 1/logic 0)
by STOP/START conditions.
The following functions are not available in the PCF8584:
6.9
• The non-acknowledge mode (ACK flag)
• Always selected (ALS flag)
• Access to the bit counter (BC0 to BC2)
• Full SCL frequency selection (2 bits instead of 5 bits)
Multi-master operation
• Asymmetrical clock (ASC flag).
To avoid conflict between data and repeated START and
STOP operations, multi-master systems have some
limitations:
6.11.2
• When powering up multiple PCF8584s in multi-master
systems, the possibility exists that one node may power
up slightly after another node has already begun an
I2C-bus transmission; the Bus Busy condition will thus
not have been detected. To avoid this condition, a delay
should be introduced in the initialization sequence of
each PCF8584 equal to the longest I2C-bus
transmission, see flowchart ‘PCF8584 initialization’
(Fig.5).
6.10
The following functions either replace the deleted
functions or are completely new:
• Chip clock prescaler
• Assert acknowledge bit (ACK flag)
• Register selection bits (ES1 and ES2 flags)
• Additional status flags (BER, ‘bus error’)
• Automatic interface control between 80XX and
68000-type microcontrollers
• Programmable interrupt vector
Reset
• Strobe generator
A LOW level pulse on the RESET (CLK must run) input
forces the I2C-bus controller into a well-defined state.
All flags in S1 are reset to logic 0, except the PIN flag and
the BB flag, which are set to logic 1. S0' and S3 are set
to 00H.
• Bus monitor function
• Long-distance mode [non-I2C-bus mode (4-wire); only
for communication between parallel-bus processors
using the PCF8584 at each interface point].
The RESET pin is also used for the STROBE output
signal. Both functions are separated on-chip by a digital
filter. The reset input signal has to be sufficiently long
(minimum 30 clock cycles) to pass through the filter.
The STROBE output signal is sufficiently short (8 clock
cycles) to be blocked by the filter. For more detailed
information on the strobe function see Section 6.12.
6.11
6.12
6.12.1
Special function modes
STROBE
When the I2C-bus controller receives its own address (or
the ‘00H’ general call address) followed immediately by a
STOP condition (i.e. no further data transmitted after the
address), a strobe output signal is generated at the
RESET/STROBE pin (pin 19). The STROBE signal
consists of a monostable output pulse (active LOW),
8 clock cycles long (see Fig.9). It is generated after the
STOP condition is received, preceded by the correct slave
address. This output can be used as a bus access
controller for multi-master parallel-bus systems.
Comparison to the MAB8400 I2C-bus interface
The structure of the PCF8584 is similar to that of the
MAB8400 series of microcontrollers, but with a modified
control structure. Access to all I2C-bus control and status
registers is done via the parallel-bus port in conjunction
with register select input A0, and control bits ESO, ES1
and ES2.
1997 Oct 21
ADDED FUNCTIONS
13
Philips Semiconductors
Product specification
I2C-bus controller
6.12.2
PCF8584
• The controller is always selected.
LONG-DISTANCE MODE
• The controller is always in the slave receiver mode.
The long-distance mode provides the possibility of
longer-distance serial communication between parallel
processors via two I2C-bus controllers. This mode is
selected by setting ES1 to logic 1 while the serial interface
is enabled (ESO = 1).
• The controller never generates an acknowledge.
• The controller never generates an interrupt request.
• A pending interrupt condition does not force SCL LOW.
• BB is set to logic 0 after detection of a START condition,
and reset to logic 1 after a STOP condition.
In this mode the I2C-bus protocol is transmitted over
4 unidirectional lines, SDA OUT, SCL IN, SDA IN and
SCL IN (pins 2, 3, 4 and 5). These communication lines
should be connected to line drivers/receivers
(example: RS422) for long-distance applications.
Hardware characteristics for long-distance transmission
are then given by the chosen standard. Control of data
transmission is the same as in normal I2C-bus mode. After
reading or writing data to shift register S0, long-distance
mode must be initialized by setting ESO and ES1 to
logic 1. Because the interrupt output INT is not available in
this operating mode, synchronization of data
transmission/reception must be polled via the PIN bit.
• Received data is automatically transferred to the read
buffer.
• Bus traffic is monitored by the PIN bit, which is reset to
logic 0 after the acknowledge bit of an incoming byte has
been received, and is set to logic 1 as soon as the first
bit of the next incoming byte is detected. Reading the
data buffer S0 sets the PIN bit to logic 1. Data in the read
buffer is valid from PIN = 0 and during the next 8 clock
pulses (until next acknowledge).
• AAS is set to logic 1 at every START condition, and
reset at every 9th clock pulse.
Remarks:
Before entering the long-distance mode, ENI must be
set to logic 0.
7
7.1
When powering up an PCF8584-node in long-distance
mode, the PCF8584 must be isolated from the 4-wire
bus via 3-state line drivers/receivers until the PCF8584
is properly initialized for long-distance mode. Failure to
implement this precaution will result in system
malfunction.
6.12.3
Initialization
The flowchart of Fig.5 gives an example of a proper
initialization sequence of the PCF8584.
7.2
Implementation
The flowcharts (Figs 6 to 9) illustrate proper programming
sequences for implementing master transmitter, master
receive, and master transmitter, repeated start and master
receiver modes in polled applications.
MONITOR MODE
When the 7-bit own address register S0' is loaded with all
zeros, the I2C-bus controller acts as a passive I2C monitor.
The main features of the monitor mode are:
1997 Oct 21
SOFTWARE FLOWCHART EXAMPLES
14
Philips Semiconductors
Product specification
I2C-bus controller
PCF8584
handbook, full pagewidth
START
power-on
address line A0
A0 = HIGH
enables data transfer to/from
register S1
A0 = LOW
Access to all other registers
defined by the bit pattern in
register S1
reset minimum
30 clock cycles
PCF8584 resets to
slave receiver mode
A0 = HIGH
Loads byte 80H into register S1'
i.e. next byte will be loaded into register S0'
(own address register); serial interface off.
send byte 80H
parallel bus interface
determined by
PCF8584 (80XX/68XXX)
A0 = LOW
Loads byte 55H into register S0';
effective own address becomes AAH.
send byte 55H
A0 = HIGH
Loads byte A0H into register S1, i.e. next byte
will be loaded into the clock control register S2.
send byte A0H
A0 = LOW
Loads byte 1CH into register S2;
system clock is 12 MHz; SCL = 90 kHz.
send byte 1CH
A0 = HIGH
Loads byte C1H into register S1; register enable
serial interface, set I2C-bus into idle mode;
SDA and SCL are HIGH. The next write or read
operation will be to/from data transfer register
S0 if A0 = LOW.
send byte C1H
delay: wait a time
equal to the longest I2C
message to synchronize
BB-bit. (multimaster
systems only
On power-on, if an PCF8584 node is powered-up
slightly after another node has already begun an
I2C-bus transmission, the bus busy condition will
not have been detected. Thus, introducing this
delay will insure that this condition will not occur.
initialization of
PCF8584 completed
END
MBE714
Fig.5 PCF8584 initialization sequence.
1997 Oct 21
15
Philips Semiconductors
Product specification
I2C-bus controller
PCF8584
START
handbook, full pagewidth
A0 = HIGH
read byte from S1 register
yes
is bus busy?
(BB = 0?)
no
A0 = LOW
send byte 'slave address'
A0 = HIGH
send C5H to control
register S1
PCF8584 remains in
master transmitter
mode if R/W bit of
'slave address' = 0
Load 'slave address' into S0 register:
'slave address' = value of slave address
(7-bits + R/W = 0). After reset, default = '0'
Load C5H into S1. 'C5H' = PCF8584 generates
the 'START' condition and clocks out the slave
address and the clock pulse for slave acknowledgement.
Next byte(s) sent to the S0 register will be immediately
transferred over the I2C-bus.
n = 0 (data byte counter);
m = number of data bytes
to be transferred
A0 = HIGH
read byte from S1 register
no
Poll for transmission finished.
PIN bit = 0?
yes
slave
acknowledged?
(LRB = 0?)
yes
transmission
completed
n=m
yes
A0 = HIGH
no
send byte C3H
n=n+1
A0 = LOW
send byte 'data'
Load 'data'
into bus
buffer register S0;
data is transmitted.
END
Fig.6 PCF8584 master transmitter mode.
1997 Oct 21
16
Load C3 into the S1 control
register: PCF8584 generates
'STOP' condition.
PCF8584 goes into
slave receiver mode
MBE715
Philips Semiconductors
Product specification
I2C-bus controller
handbook, full pagewidth
PCF8584
START
A0 = LOW
Load 'Slave Address' into S0 register:
'Slave Address' = 7 bits + R/W = 1.
send byte 'slave address' to S0
A0 = HIGH
read byte from S1 status register
yes
is bus busy?
(BB = 0?)
no
Is the I2C-bus busy?
A0 = HIGH
send byte C5H to S1 control register
n = 0 (data byte counter)
m = number of data bytes
to be read
PCF8584 generates 'START' condition,
sends out slave address + RD to I2C-bus and
generates 9th clock pulse for slave ACK.
Set-up software counters.
A0 = HIGH
read byte from S1 status register
A0 = HIGH
send byte 40H to control register S1
Set ACK bit S1 to 0 in
preparation for negative
acknowledgement.
A0 = LOW
read data byte from S0 register(1)
no
PIN = 0?
A0 = HIGH
read byte from S1 status register
yes
slave ACK?
(LRB = 0?)
n=n+1
yes
no
no
This command simultaneously
receives the final data byte
from the I2C-bus and loads
it into register S0.
Neg. ACK is also sent.
PIN = 0?
(an error
has occured)
yes
A0 = HIGH
send byte C3H to S1
n = m − 1?
A0 = LOW
read final data byte from S0 register
A0 = LOW
read data byte from S0 register(1)
END
PCF8584 generates
'STOP' condition.
PCF8584 goes into
slave receiver mode.
This command transfers
the final data byte from
the data buffer to accumulator.
Because the STOP condition
was previously executed, no
I2C-bus activity takes place.
MGL009
(1) The first read of the S0 register is a ‘dummy read’ of the slave address which should be discarded. The first read of the S0 register simultaneously
reads the current value of S0 and then transfers the first valid data byte from the I2C-bus to S0.
Fig.7 PCF8584 master receiver mode.
1997 Oct 21
17
Philips Semiconductors
Product specification
I2C-bus controller
ndbook, full pagewidth
PCF8584
START
PCF8584 configured as
master transmitter
I2C-bus write routine
(master transmitter mode
excluding final STOP)
A0 = HIGH
send byte 45H
A0 = LOW
send byte 'slave address'
PCF8584 configured as
master receiver
Load 45H into the S1 register; PCF8584
generates the repeated 'START condition' only.
The current contents of register S0 is NOT
clocked out onto the I2C-bus.
The next byte sent to register S0 should be the
'slave address' + read bit.
Load 'slave address' into the S0 register. Once
loaded, it is automatically clocked out over the I2C-bus.
'Slave address' = slave address (7 bits) + R/W bit set '1'.
I2C-bus read routine (master receiver mode)
END
MBE712
Fig.8 Master transmitter followed by repeated START and becoming master receiver.
1997 Oct 21
18
Philips Semiconductors
Product specification
I2C-bus controller
PCF8584
handbook, full pagewidth
START
A0 = HIGH
read byte from S1 register
no
Check whether
'addressed as slave'
addressed as slave
(AAS = 1?)
yes
Check that 'own address'
has arrived correctly
read byte from S1 register
no
PIN bit = 0?
yes
Read incoming address to
determine if the R/W bit is 0 or 1
This will differentiate between
slave receiver or slave
transmitter modes.
A0 = LOW
read byte from S0 register
R/W = 1
SLAVE
TRANSMITTER
MODE
read or write?
(LSB = 1 or 0?)
R/W = 0
SLAVE
RECEIVER
MODE
A0 = HIGH
no
read byte from S1 register
read byte from S1 register
PIN bit = 0?
PIN bit = 0?
yes
yes
yes
negative
ACK received?
(LRB = 1?)
STOP detected?
(STS = 1?)
A0 = LOW
no
read data from S0 register
write last data byte
to S0 register
read last data byte
from S0 register
PIN deactivated
(set to '1')
PCF8584 goes into
slave receiver
mode
END
RX
Fig.9 Slave receiver/slave transmitter modes.
1997 Oct 21
19
yes
no
write data to S0 register
END
TX
no
MBE713
Philips Semiconductors
Product specification
I2C-bus controller
8
PCF8584
I2C-BUS TIMING DIAGRAMS
The diagrams (Figs 10 to 13) illustrate typical timing diagrams for the PCF8584 in master/slave functions. For detailed
description of the I2C-bus protocol, please refer to “The I2C-bus and how to use it” ; Philips document
ordering number 9398 393 40011.
handbook,
SDA full pagewidth
SCL
INT
7-bit address (76H)
interrupt
first-byte (E4H)
R/W = 0
ACK
START
condition
interrupt
interrupt
nbyte
ACK
ACK
STOP
condition
MBE709
from slave receiver
Master PCF8584 writes data to slave transmitter.
Fig.10 Bus timing diagram; master transmitter mode.
handbook,
SDA full pagewidth
SCL
INT
7-bit address (76H)
interrupt
first-byte (discard)
interrupt
nbyte
R/W = 1
START
condition
ACK
ACK
no ACK
STOP
condition
'DUMMY READ'
must be executed here
from master
receiver
from slave
Master PCF8584 reads data from slave transmitter.
Fig.11 Bus timing diagram; master receiver mode.
1997 Oct 21
20
MBE710
Philips Semiconductors
Product specification
I2C-bus controller
PCF8584
handbook,
SDA full pagewidth
SCL
INT
7-bit address (0CH)
interrupt
first-byte: 1FH
interrupt
nbyte
interrupt
R/W = 1
START
condition
ACK
ACK
no ACK
STOP
condition
from master
receiver
from slave PCF8584
MBE711
External master receiver reads data from PCF8584.
Fig.12 Bus timing diagram; slave transmitter mode.
handbook,
SDA full pagewidth
SCL
INT
7-bit address (62H)
interrupt
first-byte (CCH)
interrupt
interrupt
nbyte
R/W = 0
START
condition
ACK
ACK
STOP
condition
MBE708
from slave PCF8584
Slave PCF8584 is written to by external master transmitter.
Fig.13 Bus timing diagram; slave receiver mode.
1997 Oct 21
ACK
interrupt
(after STOP)
21
Philips Semiconductors
Product specification
I2C-bus controller
PCF8584
9 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VDD
supply voltage
−0.3
+7.0
V
VI
voltage range (any input)
−0.8
VDD + 0.5
V
II
DC input current (any input)
−10
+10
mA
IO
DC output current (any output)
−10
+10
mA
Ptot
total power dissipation
−
300
mW
PO
power dissipation per output
−
50
mW
Tamb
operating ambient temperature
−40
+85
°C
Tstg
storage temperature
−65
+150
°C
10 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is good
practice to take normal precautions appropriate to handling MOS devices (see “Handling MOS Devices” ).
1997 Oct 21
22
Philips Semiconductors
Product specification
I2C-bus controller
PCF8584
11 DC CHARACTERISTICS
VDD = 5 V ±10%; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VDD
supply voltage
IDD
supply current
4.5
5.0
5.5
V
standby; note 1
−
−
2.5
µA
operating; notes 1 and 2
−
−
1.5
mA
Inputs
CLK, IACK, A0, CS, WR, RD, RESET AND D0 to D7
VIL
LOW level input voltage
note 3
0
−
0.8
V
VIH
HIGH level input voltage
note 3
2.0
−
VDD
V
SDA AND SCL
VIL
LOW level input voltage
note 4
0
−
0.3VDD
V
VIH
HIGH level input voltage
note 4
0.7VDD
−
VDD
V
Ri
resistance to VDD
Tamb = 25 °C; note 5
25
−
100
kΩ
IOH
HIGH level output current
VOH = 2.4 V; note 6 and 7
−2.4
−
−
mA
IOL
LOW level output current
VOL = 0.4 V; note 6
3.0
−
−
mA
IOL
leakage current
note 8
−1
−
+1
µA
Outputs
Notes
1. Test conditions: 22 kΩ pull-up resistors on D0 to D7; 10 kΩ pull-up resistors on SDA, SCL, RD; RESET connected
to VSS; remaining pins open-circuit.
2. CLK waveform of 12 MHz with 50% duty factor.
3. CLK, IACK, A0, CS, WR, RD, RESET and D0 to D7 are TTL level inputs.
4. SDA and SCL are CMOS level inputs.
5. CLK, IACK, A0, CS and WR.
6. D0 to D7.
7. DTACK, STROBE.
8. D0 to D7 3-state, SDA, SCL, INT, RD, RESET.
1997 Oct 21
23
Philips Semiconductors
Product specification
I2C-bus controller
PCF8584
12 I2C-BUS TIMING SPECIFICATIONS
All the timing limits are valid within the operating supply voltage and ambient temperature range; VDD = 5 V ±10%;
Tamb = −40 to +85 °C; and refer to VIL and VIH with an input voltage of VSS to VDD.
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
fSCL
SCL clock frequency
−
−
100
kHz
tSW
tolerable spike width on bus
−
−
100
ns
tBUF
bus free time
4.7
−
−
µs
tSU;STA
START condition set-up time
4.7
−
−
µs
tHD;STA
START condition hold time
4.0
−
−
µs
tLOW
SCL LOW time
4.7
−
−
µs
tHIGH
SCL HIGH time
4.0
−
−
µs
tr
SCL and SDA rise time
−
−
1.0
µs
tf
SCL and SDA fall time
−
−
0.3
µs
tSU;DAT
data set-up time
250
−
−
ns
tHD;DAT
data hold time
0
−
−
ns
tVD;DAT
SCL LOW to data out valid
−
−
3.4
µs
tSU;STO
STOP condition set-up time
4.0
−
−
µs
13 PARALLEL INTERFACE TIMING
All the timing limits are valid within the operating supply voltage and ambient temperature range: VDD = 5 V ±10%;
Tamb = −40 to +85 °C; and refer to VIL and VIH with an input voltage of VSS to VDD. CL = 100 pF; RL = 1.5 kΩ
(connected to VDD) for open-drain and high-impedance outputs, where applicable (for measurement purposes only).
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
tr
clock rise time
see Fig.14
−
−
6
ns
tf
clock fall time
see Fig.14
−
−
6
ns
tCLK
input clock period
(50% ±5% duty factor)
see Fig.14
83
−
333
ns
tCLRL
CS set-up to RD LOW
see Fig.16 and note 1 20
−
−
ns
tCLWL
CS set-up to WR LOW
see Fig.15 and note 1 20
−
−
ns
tRHCH
CS hold from RD HIGH
see Fig.16
0
−
−
ns
tWHCH
CS hold from WR HIGH
see Fig.15
0
−
−
ns
tAVWL
A0 set-up to WR LOW
see Fig.15
10
−
−
ns
tAVRL
A0 set-up to RD LOW
see Fig.16
10
−
−
ns
tWHAI
A0 hold from WR HIGH
see Fig.15
20
−
−
ns
tRHAI
A0 hold from RD HIGH
see Fig.16
10
−
−
ns
tWLWH
WR pulse width
see Fig.15
230
−
1000
ns
tRLRH
RD pulse width
see Fig.16
230
−
1000
ns
tDVWH
data set-up before WR HIGH
see Fig.15
150
−
−
ns
tRLDV
data valid after RD LOW
see Fig.16
−
160
180
ns
tWHDI
data hold after WR HIGH
see Fig.15
20
−
−
ns
tRHDF
data bus floating after RD
HIGH
see Fig.16
−
−
150
ns
1997 Oct 21
24
Philips Semiconductors
Product specification
I2C-bus controller
SYMBOL
PARAMETER
PCF8584
CONDITIONS
MIN.
TYP.
MAX.
UNIT
tAVCL
A0 set-up to CS LOW
see Figs 17 and 18
10
−
−
ns
tWLCL
R/WR set-up to CS LOW
see Fig.17
10
−
−
ns
tRHCL
R/WR set-up to CS LOW
see Fig.18
10
−
−
ns
tCLDV
data valid after CS LOW
see Fig.18 and note 2 −
160
180
ns
tCLDL
DTACK LOW after CS LOW
see Figs 17 and 18
−
2tCLK + 75
3tCLK + 150 ns
tCHAI
A0 hold from CS HIGH
see Fig.18
0
−
−
ns
tCHRL
R/WR hold from CS HIGH
see Fig.18
0
−
−
ns
tCHWH
R/WR hold from CS HIGH
see Fig.17
0
−
−
ns
tCHDF
data bus float after CS HIGH
see Fig.18
−
−
150
ns
tCHDE
DTACK HIGH from CS HIGH
see Figs 17 and 18
−
100
120
ns
tCHDI
data hold after CS HIGH
see Fig.17
0
−
−
ns
tDVCL
data set-up to CS LOW
see Fig.17
0
−
−
ns
tALIE
INT HIGH from IACK LOW
see Figs 19 and 20
−
130
180
ns
tALDV
data valid after IACK LOW
see Figs 19 and 20
−
200
250
ns
tALAE
IACK pulse width
see Fig.20
230
−
−
ns
tAHDI
data hold after IACK HIGH
see Fig.20
−
−
30
ns
tALDL
DTACK LOW from IACK LOW
see Fig.20
−
2tCLK + 75
3tCLK + 150 ns
tAHDE
DTACK HIGH from IACK HIGH
see Fig.20
−
120
140
ns
tW4
RESET pulse width
see Fig.21
30tCLK
−
−
ns
tW5
STROBE pulse width
see Fig.22
8tCLK
8tCLK + 90
−
ns
tCLCL
CS LOW
see Figs 17 and 18
−
tCLDL + tCHDE
−
ns
Notes
1. A minimum of 6 clock cycles must elapse between consecutive parallel-bus accesses when the I2C-bus controller
operates at 8 or 12 MHz. This may be reduced to 3 clock cycles for lower operating frequencies.
2. Not for S1.
1997 Oct 21
25
Philips Semiconductors
Product specification
I2C-bus controller
PCF8584
t CLK
handbook, full pagewidth
35.5 ns
min
35.5 ns
min
CLK
tr
6 ns max
tf
6 ns max
tf
MLA013 - 1
Fig.14 Clock input timing.
CS
t CLWL
t WHCH
A0
t AVWL
t WHAI
WR
t WLWH
DATA VALID
D0 to D7
t DVWH
MLA014 - 1
Fig.15 Bus timing (80XX mode); write cycle.
1997 Oct 21
26
t WHDI
Philips Semiconductors
Product specification
I2C-bus controller
PCF8584
handbook, full pagewidth
CS
t CLRL
t RHCH
A0
t AVRL
t RHAI
RD
t RLRH
DATA VALID
D0 to D7
MLA015 - 1
t RLDV
t RHDF
Fig.16 Bus timing (80XX mode); read cycle.
handbook, full pagewidth
A0
t CHAI
t AVCL
R/W
t WLCL
t CLCL
t CHWH
CS
D0 to D7
DATA VALID
t DVCL
t CHDI
DTACK
MLA017 - 1
t CLDL
t CHDE
Fig.17 Bus timing (68000 mode); write cycle.
1997 Oct 21
27
Philips Semiconductors
Product specification
I2C-bus controller
PCF8584
A0
t CHAL
t AVCL
R/W
t RHCL
t CLCL
t CHRL
CS
D0 to D7
DATA VALID
t CLDV
t CHDF
DTACK
t CLDL
MLA016 - 1
t CHDE
Fig.18 Bus timing (68000 mode); read cycle.
t ALIE
INT
t ALAE
IACK
t ALDV
t AHDI
D0 to D7
DATA VALID
MLA018 - 1
Fig.19 Interrupt timing (80XX mode).
1997 Oct 21
28
Philips Semiconductors
Product specification
I2C-bus controller
PCF8584
t ALIE
handbook, full pagewidth
INT
t ALAE
IACK
t ALDV
t AHDI
D0 to D7
DATA VALID
t ALDL
t AHDE
DTACK
MLA019 - 1
Fig.20 Interrupt timing (68000 mode).
CLK
RESET
t W4
Fig.21 Reset timing.
1997 Oct 21
29
MLA020 - 1
Philips Semiconductors
Product specification
I2C-bus controller
PCF8584
CLK
STROBE
t W5
Fig.22 Strobe timing.
1997 Oct 21
30
MLA021 - 1
Philips Semiconductors
Product specification
I2C-bus controller
PCF8584
14 APPLICATION INFORMATION
ADDRESS BUS
A0
DECODER
CS
ALE
SCL
8048/8051
DATA
PCF8584
RD
SDA
WR
INT
MBE704
Fig.23 Application diagram using the 8048/8051.
1997 Oct 21
31
Philips Semiconductors
Product specification
I2C-bus controller
PCF8584
AS
UDS
DECODER
LDS
CS
ADDRESS
A1
A1, A2, A3
68000
FCX
IPX
SCL
IACK
INTERRUPT
HANDLER
PCF8584
INT
SDA
R/W
DTACK
DATA
MBE702
Fig.24 Application diagram using the 68000.
1997 Oct 21
32
Philips Semiconductors
Product specification
I2C-bus controller
PCF8584
ADDRESS BUS
A0
DECODER
CS
ALE
SCL
IOR
8088
PCF8584
IOW
SDA
DATA
INTR
INT
IACK
MBE703
Fig.25 Application diagram using the 8088.
1997 Oct 21
33
Philips Semiconductors
Product specification
I2C-bus controller
PCF8584
handbook, full pagewidth
Substrate
CLK
1
20 VDD
SDA or SDA OUT
2
19 RESET/STROBE
SCL or SCL IN
3
18 WR (R/W)
IACK or SDA IN
4
17 CS
INT or SCL OUT
5
16 RD (DTACK)
A0
6
15 DB7
DB0
7
14 DB6
DB1
8
13 DB5
DB2
9
12 DB4
VSS 10
11 DB3
(1)
MBE701
Maximum forward current: 5 mA; maximum reverse voltage: 5 V.
Fig.26 PCF8584 diode protection.
14.1
Application notes
Additional application notes are available from Philips Semiconductors:
1. AN95068: “C Routines for the PCF8584”.
2. AN96040: “Using the PCF8584 with non-specified timings and other frequently asked questions”.
3. AN90001: “Interfacing PCF8584 I2C-bus controller to 80(C)51 family of microcontrollers”.
1997 Oct 21
34
Philips Semiconductors
Product specification
I2C-bus controller
PCF8584
15 PACKAGE OUTLINES
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
ME
seating plane
D
A2
A
A1
L
c
e
Z
b1
w M
(e 1)
b
MH
11
20
pin 1 index
E
1
10
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
c
mm
4.2
0.51
3.2
1.73
1.30
0.53
0.38
0.36
0.23
26.92
26.54
inches
0.17
0.020
0.13
0.068
0.051
0.021
0.015
0.014
0.009
1.060
1.045
D
e
e1
L
ME
MH
w
Z (1)
max.
6.40
6.22
2.54
7.62
3.60
3.05
8.25
7.80
10.0
8.3
0.254
2.0
0.25
0.24
0.10
0.30
0.14
0.12
0.32
0.31
0.39
0.33
0.01
0.078
(1)
E
(1)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT146-1
1997 Oct 21
REFERENCES
IEC
JEDEC
EIAJ
SC603
35
EUROPEAN
PROJECTION
ISSUE DATE
92-11-17
95-05-24
Philips Semiconductors
Product specification
I2C-bus controller
PCF8584
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
HE
y
v M A
Z
11
20
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
10
e
bp
detail X
w M
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
mm
2.65
0.30
0.10
2.45
2.25
0.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
1.27
10.65
10.00
1.4
1.1
0.4
1.1
1.0
0.25
0.25
0.1
0.9
0.4
inches
0.10
0.012 0.096
0.004 0.089
0.01
0.019 0.013
0.014 0.009
0.51
0.49
0.30
0.29
0.050
0.419
0.043
0.055
0.394
0.016
0.043
0.039
0.01
0.01
0.004
0.035
0.016
Z
(1)
θ
8o
0o
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT163-1
075E04
MS-013AC
1997 Oct 21
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
95-01-24
97-05-22
36
Philips Semiconductors
Product specification
I2C-bus controller
PCF8584
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
16 SOLDERING
16.1
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
16.3.2
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
16.2
16.2.1
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
DIP
SOLDERING BY DIPPING OR BY WAVE
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
• The package footprint must incorporate solder thieves at
the downstream end.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
16.2.2
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
REPAIRING SOLDERED JOINTS
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
16.3
16.3.1
16.3.3
REPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
SO
REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
1997 Oct 21
WAVE SOLDERING
37
Philips Semiconductors
Product specification
I2C-bus controller
PCF8584
17 DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
18 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
19 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1997 Oct 21
38
Philips Semiconductors
Product specification
I2C-bus controller
PCF8584
NOTES
1997 Oct 21
39
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Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1997
SCA55
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
417067/00/04/pp40
Date of release: 1997 Oct 21
Document order number:
9397 750 02932