Data Sheet

CBTL04GP043
Dual 2 x 2 differential channel crossbar switch
Rev. 1.1 — 27 July 2015
Product data sheet
1. General description
The CBTL04GP043 is a high-performance 4-channel bidirectional crossbar switch
supporting both high speed and large swing signals. The high-speed differential signals
include PCIe-Gen3, USB3 and DisplayPort. The large swing signals include UART,
USB 2.0 and HDMI 1.4 signals.
This chip can be configured as pair straight through or cross to the output ports through
the CROSS signal. It can be placed under Low-power mode using the XSDN pin.
This crossbar switch supports wide common-mode voltage range from 0 V to VDD on all
input and output ports.
CBTL04GP043 is available in 2.00 mm  4.00 mm  0.5 mm XFBGA28 package with
0.5 mm pitch.
2. Features and benefits
 4-channel, bidirectional crossbar switch
 The input of the CROSS pin
 CROSS is LOW for connecting input and output ports straight through
 CROSS is HIGH for crossbar connection between input and output ports
 When XSDN is LOW, the switch is in low-power sleep mode
 Low ON-state resistance: 11  (typical)
 Bandwidth: 8.5 GHz (typical) for VIC = 2.2 V
 Low insertion loss: 1.5 dB at 2.5 GHz; 1 dB at 100 MHz
 Low return loss: 20 dB at 2.5 GHz
 Low off-state isolation: 16 dB at 2.5 GHz; 40 dB at 100 MHz
 Low DDNEXT crosstalk: 20 dB at 2.5 GHz
 VIC common-mode input voltage VIC: 0 V to VDD
 Differential input voltage VID: 1.4 V (maximum)
 Intra-pair skew: 5 ps (typical)
 Supports power supply voltage range from 2.7 V to 3.5 V
 Back current protection on all I/O pins of these switches
 All channels support rail-to-rail input voltage
 XFBGA28 2 mm  4 mm  0.5 mm package with 0.5 mm pitch
 ESD: 2000 V HBM; 750 V CDM
 Operating temperature range: 20 C to +85 C
CBTL04GP043
NXP Semiconductors
Dual 2 x 2 differential channel crossbar switch
3. Ordering information
Table 1.
Ordering information
Type number
Topside
marking
CBTL04GP043EX
[1]
GP43*
[1]
Package
Name
Description
Version
XFBGA28
plastic, extremely thin fine-pitch ball grid array package;
28 balls; body 2.00  4.00  0.5 mm; 0.5 mm pitch
SOT1356-1
‘*’ changes based on date code.
3.1 Ordering options
Table 2.
Ordering options
Type number
Orderable
part number
Package
Packing method
Minimum
order
quantity
Temperature
CBTL04GP043EX
CBTL04GP043EXJ
XFBGA28
Reel 13” Q1/T1
*standard mark SMD
7000
Tamb = 20 C to +85 C
4. Block diagram
CBTL04GP043
A0_P
A1_P
A0_N
A1_N
B0_P
B1_P
B0_N
B1_N
C0_P
C1_P
C0_N
C1_N
D0_P
D1_P
D0_N
D1_N
CROSS
XSDN
aaa-012968
Fig 1.
CBTL04GP043
Product data sheet
Block diagram of CBTL04GP043
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 27 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
2 of 19
CBTL04GP043
NXP Semiconductors
Dual 2 x 2 differential channel crossbar switch
5. Pinning information
5.1 Pinning
CBTL04GP043EX
ball A1
index area
1
2
3
4
1
2
3
4
A
A1_P
B1_P
D1_P
C1_P
B
A1_N
B1_N
D1_N
C1_N
C
CROSS
D
n.c.
n.c.
n.c.
n.c.
E
n.c.
n.c.
n.c.
n.c.
F
VSS
G
A0_P
B0_P
C0_P
D0_P
H
A0_N
B0_N
C0_N
D0_N
A
B
C
D
E
F
VDD
XSDN
G
Transparent top view
An empty cell indicates no ball
is populated at that grid point.
H
aaa-012969
n.c. = ball present, but not internally connected.
Transparent top view
a. Pin configuration
Fig 2.
CBTL04GP043
Product data sheet
aaa-013489
b. Ball mapping
Pin configuration for XFBGA28
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 27 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
3 of 19
CBTL04GP043
NXP Semiconductors
Dual 2 x 2 differential channel crossbar switch
5.2 Pin description
Table 3.
Pin description
Symbol
Pin
Type
Description
I/O
Port A1
Data path signals
A1_P
A1
A1_N
B1
I/O
B1_P
A2
I/O
B1_N
B2
I/O
C1_P
A4
I/O
C1_N
B4
I/O
D1_P
A3
I/O
D1_N
B3
I/O
A0_P
G1
I/O
A0_N
H1
I/O
B0_P
G2
I/O
B0_N
H2
I/O
C0_P
G3
I/O
C0_N
H3
I/O
D0_P
G4
I/O
D0_N
H4
I/O
Port B1
Port C1
Port D1
Port A0
Port B0
Port C0
Port D0
Control signals
CROSS
C1
CMOS
input
When CROSS = HIGH, selects cross function.
When CROSS = LOW, selects pass-through function.
CROSS input must be LOW for more than 500 s during
start up time.
XSDN
F4
CMOS
input
When XSDN = HIGH, enables XBAR switches.
power
Power supply range from 3.0 V to 3.5 V.
When XSDN = LOW, all switches are 3-stated.
Power supply
VDD
C4
Ground connection
CBTL04GP043
Product data sheet
VSS
F1
ground
Supply ground (0 V).
n.c.
D1, D2, D3,
D4, E1, E2,
E3, E4
-
Not connected. These balls should be connected to solid
ground plane on PCB to improve signal integrity.
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 27 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
4 of 19
CBTL04GP043
NXP Semiconductors
Dual 2 x 2 differential channel crossbar switch
6. Functional description
Refer to Figure 1 “Block diagram of CBTL04GP043”.
When CROSS input is LOW, Port 0 pins are connected to their respective Port 1 pins.
When CROSS input is HIGH, Port 0 A and B are crossed to Port 1 B and A,
Port 0 C and D are crossed to Port 1 D and C.
When XSDN input is HIGH, the crossbar switch is in normal operation mode. When XSDN
input is LOW, the crossbar switch is placed under high-impedance state.
Table 4.
Function table
Port 1 connected to
Port 0
XSDN = 0
XSDN = 1,
CROSS = 0
XSDN = 1,
CROSS = 1
A1_P
high-Z
A0_P
B0_P
A1_N
high-Z
A0_N
B0_N
B1_P
high-Z
B0_P
A0_P
B1_N
high-Z
B0_N
A0_N
C1_P
high-Z
C0_P
D0_P
C1_N
high-Z
C0_N
D0_N
D1_P
high-Z
D0_P
C0_P
D1_N
high-Z
D0_N
C0_N
7. Power-up sequence
The CROSS pin must be LOW before start-up time has elapsed. After both VDD and
XSDN go HIGH for 500 s (tstartup time), CROSS input can be toggled to HIGH.
VDD
XSDN
tstartup
CROSS
aaa-014237
Fig 3.
CBTL04GP043
Product data sheet
CROSS pin power-up sequence
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Rev. 1.1 — 27 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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CBTL04GP043
NXP Semiconductors
Dual 2 x 2 differential channel crossbar switch
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDD
VI
Parameter
Conditions
Min
Max
Unit
supply voltage
[1]
0.3
+4.6
V
input voltage
control pins
[1]
0.3
+5.5
V
I/O pins of switches
[1]
0.3
+4.6
V
65
+150
C
HBM
[2]
-
2000
V
CDM
[3]
-
750
V
storage temperature
Tstg
VESD
electrostatic discharge
voltage
[1]
All voltage values, except differential voltages, are with respect to network ground terminal.
[2]
Human Body Model: ANSI/ESDA/JEDEC JDS-001-2012 (Revision of ANSI/ESDA/JEDEC JS-001-2011),
ESDA/JEDEC Joint standard for ESD sensitivity testing, Human Body Model - Component level;
Electrostatic Discharge Association, Rome, NY, USA; JEDEC Solid State Technology Association,
Arlington, VA, USA.
[3]
Charged Device Model; JESD22-C101E December 2009 (Revision of JESD22-C101D, October 2008),
standard for ESD sensitivity testing, Charged Device Model - Component level; JEDEC Solid State
Technology Association, Arlington, VA, USA.
9. Recommended operating conditions
Table 6.
Operating conditions
Over operating free-air temperature range (unless otherwise noted).
CBTL04GP043
Product data sheet
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD
supply voltage
3.3 V supply option
2.7
-
3.5
V
VI
input voltage
CMOS inputs
0.3
-
+5.5
V
MUX I/O pins
0.3
-
+3.5
V
Tamb
ambient temperature
operating in free air
20
-
+85
C
Rth(j-a)
thermal resistance from
junction to ambient
JEDEC still air test
environment
-
149
-
C/W
Rth(j-c)
thermal resistance from
junction to case
to case top; top cold plate
at ambient temperature of
85 C
-
69
-
C/W
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 27 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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CBTL04GP043
NXP Semiconductors
Dual 2 x 2 differential channel crossbar switch
10. Characteristics
10.1 Device general characteristics
Table 7.
General characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Pcons
power consumption
VDD = 3.5 V
-
-
1.75
mW
Pcons(sleep)
sleep mode power consumption XSDN = 0
-
-
42
W
IDD
supply current
VDD = 3.5 V
-
-
0.5
mA
tstartup
start-up time
supply voltage valid and XSDN goes
HIGH to channel-specified operating
characteristics
-
-
500
s
trcfg
reconfiguration time
CROSS pin
-
300
1000
s
10.2 Switch channel characteristics
Table 8.
Dynamic and static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
DDRL
differential return loss
f = 2.5 GHz
-
20
-
dB
DDIL
differential insertion loss
channel is OFF
f = 2.5 GHz
-
16
-
dB
f = 100 MHz
-
40
-
dB
f = 2.5 GHz
-
1.5
-
dB
f = 100 MHz
-
1
-
dB
f = 2.5 GHz
-
20
-
dB
f = 240 MHz
-
44
-
dB
f = 2.5 GHz
-
23
-
dB
f = 240 MHz
-
53
-
dB
channel is ON
DDNEXT
DDFEXT
differential near-end crosstalk
differential far-end crosstalk
channels among Port 0 or
channels among Port 1
between channels of Port 0 and Port 1
Ron
ON-state resistance
VDD = 2.7 V; VI = 2.2 V; II = 10 mA
-
11
15

Cin
input capacitance
single-ended; VDD = 2.8 V; VI = 2.2 V
-
3
-
pF
B3dB
3 dB bandwidth
VIC = 0 V
-
7
-
GHz
VIC = 2.2 V
-
8.5
-
GHz
tPD
propagation delay
from input to output pairs
-
70
-
ps
tsk(dif)
differential skew time
intra-pair
-
5
-
ps
VI
input voltage
for all switch ports
0
-
3.5
V
VIC
common-mode input voltage
for all switch ports
0
-
VDD
V
VI(dif)(p-p)
peak-to-peak differential
input voltage
for all switch ports
0
-
1.4
V
ILIH
HIGH-level input leakage
current
VDD = max.; VI = VDD
-
-
1
A
ILIL
LOW-level input leakage current VDD = max.; VI = VSS
-
-
1
A
CBTL04GP043
Product data sheet
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Rev. 1.1 — 27 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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CBTL04GP043
NXP Semiconductors
Dual 2 x 2 differential channel crossbar switch
10.3 Control signals characteristics
Table 9.
CROSS input buffer characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIH
HIGH-level input voltage
CMOS input
2.15
-
-
V
VIL
LOW-level input voltage
CMOS input
-
-
0.5
V
-
-
0.2
A
input leakage current
ILI
[1]
measured with input at
VIH = VDD and VIL = 0 V
[1]
This ILI value is guaranteed by design and bench test.
Table 10.
XSDN input buffer characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIH
HIGH-level input voltage
CMOS inputs
2.15
-
-
V
VIL
LOW-level input voltage
CMOS inputs
-
-
0.5
V
ILI
input leakage current
measured with input at
VIH = VDD and VIL = 0 V
-
-
1
A
CBTL04GP043
Product data sheet
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Rev. 1.1 — 27 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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CBTL04GP043
NXP Semiconductors
Dual 2 x 2 differential channel crossbar switch
11. Package outline
XFBGA28: plastic, extremely thin fine-pitch ball grid array package; 28 balls
D
B
SOT1356-1
A
ball A1
index area
A2
A
A1
E
detail X
e1
b
e
ZE1
C
C A B
C
Øv
Øw
y1 C
y
H
e
G
F
E
e2
D
C
B
A
1
2
ball A1
index area
3
4
X
ZD1
0
3 mm
scale
Dimensions (mm are the original dimensions)
Unit
max
nom
min
mm
A
0.5
A1
A2
b
0.15 0.35 0.25
0.10 0.34 0.20
0.05 0.33 0.15
D
E
2.10 4.10
2.00 4.00
1.90 3.90
e
e1
e2
0.5
1.5
3.5
v
w
0.15 0.05
y
y1
ZD1
0.1
0.1
0.35 0.35
0.25 0.25
0.15 0.15
ZE1
sot1356-1_po
References
Outline
version
IEC
JEDEC
JEITA
SOT1356-1
---
---
---
Fig 4.
European
projection
Issue date
13-08-02
13-09-09
Package outline SOT1356-1 (XFBGA28)
CBTL04GP043
Product data sheet
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Rev. 1.1 — 27 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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CBTL04GP043
NXP Semiconductors
Dual 2 x 2 differential channel crossbar switch
Cu land diameter (B)
Land open diameter (A)
Lead ball
height (D)
Lead ball diameter (C)
aaa-019163
Fig 5.
Table 11.
XFBGA28 Under Ball Metal (UBM) structure
For 2 x 4 mm HLA AEX device
Ball pitch (mm)
Land open diameter
(A) (mm)
Cu land diameter (B)
(mm)
Lead ball diameter
(C) (mm)
Lead ball height (D)
(mm)
0.5
0.180.013
0.25 0.05
0.2  0.05
0.1  0.05
12. Packing information
pin 1
aaa-006540
Fig 6.
CBTL04GP043
Product data sheet
Product orientation in carrier tape
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Rev. 1.1 — 27 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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CBTL04GP043
NXP Semiconductors
Dual 2 x 2 differential channel crossbar switch
4.00 ± 0.10 (P0)
0.25 ± 0.05
(T)
2.00 ± 0.05 (P2)
Ø 1.50
+ 0.10
(D )
− 0.00 0
1.75 ± 0.10 (E1)
5.50 ± 0.05
(F)
12.00 ± 0.30
(W)
4.25 ± 0.10
(B0)
8.00 ± 0.10
(P1)
Ø 1.60 ± 0.10 (D1)
2.25 ± 0.10
(A0)
0.60 ± 0.05
(K0)
Notes:
1. Dimensions in mm.
2. 10 sprocket hole pitches cumulative tolerance ±0.20 mm.
3. Camber not to exceed 1 mm in 250 mm.
4. Pocket position relative to sprocket hole measured as true position
of pocket, not pocket hole.
5. (S.R. Ohms/Sq.) means surface electric resistivity of the carrier tape.
aaa-009530
Fig 7.
Carrier tape
CBTL04GP043
Product data sheet
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Rev. 1.1 — 27 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
11 of 19
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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
NXP Semiconductors
CBTL04GP043
Product data sheet
see Detail C
6.5 ± 1
Ø
Ø 6.8
2.8
R56
Ø 6.2
Ø 2.2
R47.39
2
R50
5
Ø13 ± 0.2
R135
R135
R6
R6
Detail C
2.5
0.5
06
PS
2.4 ± 0.4
2 × 30°
Ø 2.5
12 of 19
12.4 ± 2.0
0.0
© NXP Semiconductors N.V. 2015. All rights reserved.
Ø 100 ± 2.0
Ø 330 ± 0.25
4.00
Notes:
1. Material: polystyrene (blue)
2. Antistatic coated
3. Flange warpage: 3 mm maximum
4. All dimensions are in mm
5. ESD – surface resistivity – 105 to 1012 Ohms/Sq.
6. General tolerance: ±0.25 mm
7. Total thickness of reel: 18.4 mm max.
aaa-009531
Fig 8.
13-inch reel
CBTL04GP043
2.0
Dual 2 x 2 differential channel crossbar switch
Rev. 1.1 — 27 July 2015
All information provided in this document is subject to legal disclaimers.
Ø 21
CBTL04GP043
NXP Semiconductors
Dual 2 x 2 differential channel crossbar switch
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Box barcode label: 76 mm  102 mm
Fig 9.
Box information barcode
13. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
CBTL04GP043
Product data sheet
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Rev. 1.1 — 27 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
13 of 19
CBTL04GP043
NXP Semiconductors
Dual 2 x 2 differential channel crossbar switch
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
13.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 10) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 12 and 13
Table 12.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
 350
< 350
< 2.5
235
220
 2.5
220
220
Table 13.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
CBTL04GP043
Product data sheet
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
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Rev. 1.1 — 27 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 10.
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 10. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
14. Abbreviations
Table 14.
CBTL04GP043
Product data sheet
Abbreviations
Acronym
Description
CDM
Charged-Device Model
CMOS
Complementary Metal-Oxide Semiconductor
ESD
ElectroStatic Discharge
HBM
Human Body Model
MUX
Multiplexer
POR
Power-On Reset
UART
Universal Asynchronous Receiver/Transmitter
USB
Universal Serial Bus
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 27 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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15. Revision history
Table 15.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
CBTL04043A1 v.1.1
20150727
Product data sheet
-
CBTL04043A1 v.1
Modifications:
CBTL04GP043 v.1
CBTL04GP043
Product data sheet
•
Added Figure 5 “XFBGA28 Under Ball Metal (UBM) structure” and Table 11 “For 2 x 4 mm HLA
AEX device”.
20141024
Product data sheet
-
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 27 July 2015
-
© NXP Semiconductors N.V. 2015. All rights reserved.
16 of 19
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16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
CBTL04GP043
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 27 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
16.4 Licenses
Purchase of NXP ICs with HDMI technology
Use of an NXP IC with HDMI technology in equipment that complies with
the HDMI standard requires a license from HDMI Licensing LLC, 1060 E.
Arques Avenue Suite 100, Sunnyvale CA 94085, USA, e-mail:
[email protected]
16.5 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
CBTL04GP043
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 27 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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18. Contents
1
2
3
3.1
4
5
5.1
5.2
6
7
8
9
10
10.1
10.2
10.3
11
12
13
13.1
13.2
13.3
13.4
14
15
16
16.1
16.2
16.3
16.4
16.5
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Power-up sequence . . . . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 6
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Device general characteristics . . . . . . . . . . . . . 7
Switch channel characteristics . . . . . . . . . . . . . 7
Control signals characteristics . . . . . . . . . . . . . 8
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Packing information . . . . . . . . . . . . . . . . . . . . 10
Soldering of SMD packages . . . . . . . . . . . . . . 13
Introduction to soldering . . . . . . . . . . . . . . . . . 13
Wave and reflow soldering . . . . . . . . . . . . . . . 13
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 14
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 14
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Contact information. . . . . . . . . . . . . . . . . . . . . 18
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2015.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 27 July 2015
Document identifier: CBTL04GP043