Data Sheet

PTN3460I
eDP to LVDS bridge for industrial and embedded applications
Rev. 2 — 19 December 2014
Product data sheet
1. General description
PTN3460I is an (embedded) DisplayPort to LVDS bridge device that enables connectivity
between an (embedded) DisplayPort (eDP) source and LVDS display panel. It processes
the incoming DisplayPort (DP) stream, performs DP to LVDS protocol conversion and
transmits processed stream in LVDS format.
PTN3460I has two high-speed ports: Receive port facing DP Source (for example,
CPU/GPU/chip set), Transmit port facing the LVDS receiver (for example, LVDS display
panel controller). The PTN3460I can receive DP stream at link rate 1.62 Gbit/s or
2.7 Gbit/s and it can support 1-lane or 2-lane DP operation. It interacts with DP source via
DP Auxiliary (AUX) channel transactions for DP link training and setup.
It supports single bus or dual bus LVDS signaling with color depths of 18 bits per pixel or
24 bits per pixel and pixel clock frequency up to 112 MHz. The LVDS data packing can be
done either in VESA or JEIDA format. Also, the DP AUX interface transports
I2C-over-AUX commands and support EDID-DDC communication with LVDS panel. To
support panels without EDID ROM, the PTN3460I can emulate EDID ROM behavior
avoiding specific changes in system video BIOS.
PTN3460I is suitable for industrial design due to its wide temperature range of 40 C to
+85 C.
PTN3460I provides high flexibility to optimally fit under different platform environments. It
supports three configuration options: multi-level configuration pins, DP AUX interface, and
I2C-bus interface.
PTN3460I can be powered by either 3.3 V supply only or dual supplies (3.3 V/1.8 V) and
is available in the HVQFN56 7 mm  7 mm package with 0.4 mm pitch.
2. Features and benefits
2.1 Device features
 Embedded microcontroller and on-chip Non-Volatile Memory (NVM) allow for flexibility
in firmware updates
 LVDS panel power-up (/down) sequencing control
 Firmware controlled panel power-up (/down) sequence timing parameters
 No external timing reference needed
 EDID ROM emulation to support panels with no EDID ROM. Emulation ON/OFF is set
via configuration pin CFG4 (see Table 14 for more details)
 Supports EDID structure v1.3
 On-chip EDID emulation up to seven different EDID data structures
PTN3460I
NXP Semiconductors
eDP to LVDS bridge for industrial and embedded applications
 eDP complying PWM signal generation or PWM signal pass through from eDP source
2.2 DisplayPort receiver features
 Compliant to DP v1.2a and v1.1a
 Compliant to eDP v1.2 and v1.1
 Supports Main Link operation with one or two lanes (select through configuration pin
CFG3, see Table 4 for more details)
 Supports Main Link rate: Reduced Bit Rate (1.62 Gbit/s) and High Bit Rate (2.7 Gbit/s)
 Supports 1 Mbit/s AUX channel
 Supports Native AUX and I2C-over-AUX transactions
 Supports down spreading to minimize EMI
 Integrated 50  termination resistors provide impedance matching on both Main Link
lanes and AUX channel
 High performance Auto Receive Equalization enabling optimal channel compensation,
device placement flexibility and power saving at CPU/GPU
 Supports eDP authentication options: Alternate Scrambler Seed Reset (ASSR) and
Alternate Framing
 Supports Full Link training
 Supports DisplayPort symbol error rate measurements
 Supports PCB routing flexibility by programming for:
 AUX P/N swapping
 DP Main Link P/N swapping
2.3 LVDS transmitter features









Compatible with ANSI/TIA/EIA-644-A-2001 standard
Supports RGB data packing as per JEIDA and VESA data formats
Supports pixel clock frequency from 6 MHz to 112 MHz
Supports single LVDS bus operation up to 112 mega pixels per second
Supports dual LVDS bus operation up to 224 mega pixels per second
Supports color depth options: 18 bpp, 24 bpp
Programmable center spreading of pixel clock frequency to minimize EMI
Supports 1920  1200 at 60 Hz resolution in dual LVDS bus mode
Programmable LVDS signal swing to pre-compensate for channel attenuation or allow
for power saving
 Supports PCB routing flexibility by programming for:
 LVDS bus swapping
 Channel swapping
 Differential signal pair swapping
 Supports Data Enable polarity programming
 DDC control for EDID ROM access; I2C-bus interface up to 400 kbit/s
2.4 Control and system features
 Device programmability
 Multi-level configuration pins enabling wider choice
PTN3460I
Product data sheet
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Rev. 2 — 19 December 2014
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PTN3460I
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eDP to LVDS bridge for industrial and embedded applications
 I2C-bus slave interface supporting Standard-mode (100 kbit/s) and
Fast-mode (400 kbit/s)
 Power management
 Low-power state: DP AUX command-based Low-power mode (SET POWER)
 Deep power-saving state via a dedicated pin
2.5 General
 Power supply: with on-chip regulator
 3.3 V  10 % (integrated regulator switched on)
 3.3 V  10 %, 1.8 V  5 % (integrated regulator switched off)
 ESD: 8 kV HBM, 1 kV CDM
 Operating temperature range: 40 C to +85 C
 HVQFN56 package 7 mm  7 mm, 0.4 mm pitch; exposed center pad for thermal relief
and electrical ground
3. Applications






Industrial PC design
Printer display
Automotive dashboard display
AIO platforms
Notebook platforms
Netbooks/net tops
4. System context diagram
Figure 1 illustrates the PTN3460I usage.
notebook or AIO platform
CPU/GPU/
CHIP SET
eDP
PTN3460I
DP to LVDS
BRIDGE
LVDS
LVDS PANEL
cable
MOTHERBOARD
aaa-009841
Fig 1.
PTN3460I
Product data sheet
PTN3460I context diagram
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PTN3460I
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eDP to LVDS bridge for industrial and embedded applications
5. Ordering information
Table 1.
Ordering information
Type number
Topside mark
PTN3460IBS/Fx[1][2]
PTN3460IBS[3]
Package
Name
Description
Version
HVQFN56
plastic thermal enhanced very thin quad flat package;
no leads; 56 terminals; body 7  7  0.85 mm[4];
0.4 mm pitch
SOT949-2
[1]
PTN3460IBS/Fx is firmware -specific, where the ‘x’ indicates the firmware version.
[2]
Notes on firmware and marking:
a) Firmware versions are not necessarily backwards compatible.
b) Box/reel labels will indicate the firmware version via the orderable part number (e.g., labeling will indicate PTN3460IBS/F1 for
firmware version 1).
[3]
Topside marking is limited to PTN3460IBS and will not indicate the firmware version.
[4]
Maximum package height is 1 mm.
5.1 Ordering options
Table 2.
Ordering options
Type number
Orderable
part number
PTN3460IBS/Fx[1] PTN3460IBS/FxZ
Package
Packing method
Minimum
order
quantity
Temperature
HVQFN56
Reel 7” Q2/T3 *standard
mark SMD dry pack
500
Tamb = 40 C to +85 C
Reel 13” Q2/T3 *standard
mark SMD dry pack
2000
Tamb = 40 C to +85 C
PTN3460IBS/Fx[1] PTN3460IBS/FxMP HVQFN56
[1]
PTN3460IBS/Fx uses specific firmware version (‘x’ = 1, 2, 3, etc., and changes according to firmware version).
PTN3460I
Product data sheet
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Rev. 2 — 19 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x
PTN3460I
DIFF CDR,
RCV S2P
10b/8b
DP1_P,
DP1_N
DE-SCRAM
Vbias
INTERFACE DE-SKEWING
R[7:0]
10b/8b
DIFF CDR,
RCV S2P
G[7:0]
MAIN
STREAM
B[7:0]
TIME
CONV.
TIMING RECOVERY
LVDS
DIGITAL
SUBSYSTEM
LVDS
PHY
SUBSYSTEM
H, V
sync
I2C-BUS
CONTOL
INTERFACE
RCV
MANCHESTER
CODEC
AUX
CONTROL
BKLTEN
PWMO
EDID
EMULATION
DDC_SCL
DDC
INTERFACE
DDC_SDA
DRV
Vbias
HPDRX
aaa-009842
CFG1
Block diagram of PTN3460I
CFG3
CFG2
DEV_CFG
CFG4
MS_SDA
MS_SCL
PTN3460I
5 of 38
© NXP Semiconductors N.V. 2014. All rights reserved.
PD_N RST_N
TESTMODE
Fig 2.
LVS[A:D]O_P,
LVS[A:D]O_N
PVCCEN
SYSTEM
CONTROLLER
EPS_N
LVSCKE_P,
LVSCKE_N
LVSCKO_P,
LVSCKO_N
NONVOLATILE
MEMORY
DPCD
REGISTERS
Vbias
AUX_P,
AUX_N
LVS[A:D]E_P,
LVS[A:D]E_N
ISOCHRONOUS LINK
eDP to LVDS bridge for industrial and embedded applications
Rev. 2 — 19 December 2014
All information provided in this document is subject to legal disclaimers.
DP0_P,
DP0_N
RX PHY DIGITAL
DE-SCRAM
RX PHY
ANALOG
SUBSYSTEM
NXP Semiconductors
6. Block diagram
PTN3460I
Product data sheet
supply
PTN3460I
NXP Semiconductors
eDP to LVDS bridge for industrial and embedded applications
7. Pinning information
43 LVSDO_P
44 LVSDO_N
45 VDD(1V8)
46 LVSCKO_P
47 LVSCKO_N
48 LVSCO_P
49 LVSCO_N
50 VDD(3V3)
51 LVSBO_P
52 LVSBO_N
53 LVSAO_P
54 LVSAO_N
terminal 1
index area
55 n.c.
56 EPS_N
7.1 Pinning
AUX_N
1
42 LVSAE_N
AUX_P
2
41 LVSAE_P
GND
3
40 LVSBE_N
DP0_P
4
39 LVSBE_P
DP0_N
5
38 VDD(3V3)
VDD(1V8)
6
37 LVSCE_N
DP1_P
7
DP1_N
8
35 LVSCKE_N
RST_N
9
34 LVSCKE_P
36 LVSCE_P
PTN3460I
PD_N 10
33 PVCCEN
HPDRX 11
32 LVSDE_N
DEV_CFG 12
31 LVSDE_P
(1)
PWMO 28
CFG4 27
BKLTEN 26
MS_SCL 25
MS_SDA 24
CFG3 23
CFG2 22
CFG1 21
TESTMODE 20
VDD(1V8) 19
GNDREG 18
GNDREG 17
29 DDC_SCL
n.c. 16
30 DDC_SDA
VDD(3V3) 14
n.c. 15
VDD(3V3) 13
aaa-009843
Transparent top view
(1) Center pad is connected to PCB ground plane for electrical grounding and thermal relief.
Fig 3.
Pin configuration for HVQFN56
Refer to Section 13 “Package outline” for package and pin dimensions.
PTN3460I
Product data sheet
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Rev. 2 — 19 December 2014
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PTN3460I
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eDP to LVDS bridge for industrial and embedded applications
7.2 Pin description
Table 3.
Pin description
Symbol
Pin
Type
Description
DisplayPort interface signals
DP0_P
4
self-biasing
differential input
Differential signal from DP source. DP0_P makes a differential pair with DP0_N.
The input to this pin must be AC-coupled externally.
DP0_N
5
self-biasing
differential input
Differential signal from DP source. DP0_N makes a differential pair with DP0_P.
The input to this pin must be AC-coupled externally.
DP1_P
7
self-biasing
differential input
Differential signal from DP source. DP1_P makes a differential pair with DP1_N.
The input to this pin must be AC-coupled externally.
DP1_N
8
self-biasing
differential input
Differential signal from DP source. DP1_N makes a differential pair with DP1_P.
The input to this pin must be AC-coupled externally.
AUX_P
2
self-biasing
differential I/O
Differential signal towards DP source. AUX_P makes a differential pair with
AUX_N. The pin must be AC-coupled externally.
AUX_N
1
self-biasing
differential I/O
Differential signal towards DP source. AUX_N makes a differential pair with
AUX_P. The pin must be AC-coupled externally.
HPDRX
11
single-ended
3.3 V CMOS
output
Hot Plug Detect signal to DP source.
LVDS interface signals
LVSAE_P
41
LVDS output
Even bus, Channel A differential signal to LVDS receiver. LVSAE_P makes a
differential pair with LVSAE_N.
LVSAE_N
42
LVDS output
Even bus, Channel A differential signal to LVDS receiver. LVSAE_N makes a
differential pair with LVSAE_P.
LVSBE_P
39
LVDS output
Even bus, Channel B differential signal to LVDS receiver. LVSBE_P makes a
differential pair with LVSBE_N.
LVSBE_N
40
LVDS output
Even bus, Channel B differential signal to LVDS receiver. LVSBE_N makes a
differential pair with LVSBE_P.
LVSCE_P
36
LVDS output
Even bus, Channel C differential signal to LVDS receiver. LVSCE_P makes a
differential pair with LVSCE_N.
LVSCE_N
37
LVDS output
Even bus, Channel C differential signal to LVDS receiver. LVSCE_N makes a
differential pair with LVSCE_P.
LVSCKE_P
34
LVDS clock
output
Even bus, clock differential signal to LVDS receiver. LVSCKE_P makes a
differential pair with LVSCKE_N.
LVSCKE_N
35
LVDS clock
output
Even bus, clock differential signal to LVDS receiver. LVSCKE_N makes a
differential pair with LVSCKE_P.
LVSDE_P
31
LVDS output
Even bus, Channel D differential signal to LVDS receiver. LVSDE_P makes a
differential pair with LVSDE_N.
LVSDE_N
32
LVDS output
Even bus, Channel D differential signal to LVDS receiver. LVSDE_N makes a
differential pair with LVSDE_P.
LVSAO_P
53
LVDS output
Odd bus, Channel A differential signal to LVDS receiver. LVSAO_P makes a
differential pair with LVSAO_N.
LVSAO_N
54
LVDS output
Odd bus, Channel A differential signal to LVDS receiver. LVSAO_N makes a
differential pair with LVSAO_P.
LVSBO_P
51
LVDS output
Odd bus, Channel B differential signal to LVDS receiver. LVSBO_P makes a
differential pair with LVSBO_N.
LVSBO_N
52
LVDS output
Odd bus, Channel B differential signal to LVDS receiver. LVSBO_N makes a
differential pair with LVSBO_P.
PTN3460I
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Rev. 2 — 19 December 2014
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eDP to LVDS bridge for industrial and embedded applications
Table 3.
Pin description …continued
Symbol
Pin
Type
Description
LVSCO_P
48
LVDS output
Odd bus, Channel C differential signal to LVDS receiver. LVSCO_P makes a
differential pair with LVSCO_N.
LVSCO_N
49
LVDS output
Odd bus, Channel C differential signal to LVDS receiver. LVSCO_N makes a
differential pair with LVSCO_P.
LVSCKO_P
46
LVDS clock
output
Odd bus, clock differential signal to LVDS receiver. LVSCKO_P makes a
differential pair with LVSCKO_N.
LVSCKO_N
47
LVDS clock
output
Odd bus, clock differential signal to LVDS receiver. LVSCKO_N makes a
differential pair with LVSCKO_P.
LVSDO_P
43
LVDS output
Odd bus, Channel D differential signal to LVDS receiver. LVSDO_P makes a
differential pair with LVSDO_N.
LVSDO_N
44
LVDS output
Odd bus, Channel D differential signal to LVDS receiver. LVSDO_N makes a
differential pair with LVSDO_P.
DDC_SDA
30
open-drain
DDC data I/O
DDC data signal connection to display panel. Pulled-up by external termination
resistor (5 V tolerant).
DDC_SCL
29
open-drain
DDC clock I/O
DDC clock signal connection to display panel. Pulled-up by external termination
resistor (5 V tolerant).
Panel and backlight interface signals
PVCCEN
33
CMOS output
Panel power (VCC) enable output.
PWMO
28
CMOS output
PWM output signal to display panel.
BKLTEN
26
CMOS output
Backlight enable output.
Control interface signals
PD_N
10
CMOS input
Chip power-down input (active LOW). If PD_N is LOW, then the device is in
Deep power-down completely, even if supply rail is ON; for the device to be able
to operate, the PD_N pin must be HIGH.
RST_N
9
CMOS input
Chip reset pin (active LOW); internally pulled-up. The pin is meant to reset the
device and all its internal states/logic; all internal registers are taken to default
value after RST_N is applied and made HIGH.
If RST_N is LOW, the device stays in reset condition and for the device to be
able to operate, RST_N must be HIGH.
CMOS I/O
I2C-bus address/mode selection pin.
TESTMODE 20
CMOS input
If TESTMODE is left open or pulled HIGH, CFG[4:1] operate as JTAG pins. If
TESTMODE is pulled LOW, these pins serve as configuration pins.
CFG1
input
Behavior defined by TESTMODE pin.
DEV_CFG
12
21
If TESTMODE is left open or pulled HIGH, this pin functions as JTAG TEST
CLOCK input. If TESTMODE is pulled LOW, this pin acts as configuration input.
CFG2
22
input
Behavior defined by TESTMODE pin.
If TESTMODE is left open or pulled HIGH, this pin functions as JTAG MODE
SELECT input. If TESTMODE is pulled LOW, this pin acts as configuration
input.
CFG3
23
input
Behavior defined by TESTMODE pin.
If TESTMODE is left open or pulled HIGH, this pin functions as JTAG TEST
DATA INPUT. If TESTMODE is pulled LOW, this pin acts as configuration input.
CFG4
27
I/O
Behavior defined by TESTMODE pin value.
If TESTMODE is left open or pulled HIGH, this pin functions as JTAG TEST
DATA OUTPUT. If TESTMODE is pulled LOW, this pin acts as configuration
input.
PTN3460I
Product data sheet
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Rev. 2 — 19 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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PTN3460I
NXP Semiconductors
eDP to LVDS bridge for industrial and embedded applications
Table 3.
Pin description …continued
Symbol
Pin
Type
Description
MS_SDA
24
open-drain (I2C)
data input/output
I2C-bus data signal connection to I2C-bus master or slave. Pulled up by external
resistor.
MS_SCL
25
I2C-bus clock signal connection to I2C-bus master or slave. Pulled up by
open-drain (I2C)
clock input/output external resistor.
n.c.
55
-
not connected; reserved.
EPS_N
56
input
Can be left open or pulled HIGH for 3.3 V supply only option relying on internal
regulator for 1.8 V generation.
Should be pulled down to GND for dual supply (3.3 V/1.8 V) option.
Supply, ground and decoupling
VDD(3V3)
13, 14, power
38, 50
3.3 V supply input.
VDD(1V8)
6, 45
power
1.8 V supply input.
VDD(1V8)
19
power
1.8 V regulator supply output.
n.c.
15, 16
power
Not connected.
GND
3
power
Ground.
GNDREG
17, 18
power
Ground for regulator.
GND
center
pad
power
The center pad must be connected to motherboard GND plane for both
electrical ground and thermal relief.
8. Functional description
PTN3460I is an (Embedded) DisplayPort to LVDS bridge IC that processes the incoming
DisplayPort (DP) stream, performs DP to LVDS protocol conversion and transmits
processed stream in LVDS format. Refer to Figure 2 “Block diagram of PTN3460I”.
The PTN3460I consists of:
• DisplayPort receiver
• LVDS transmitter
• System control and operation
The following sections describe individual sub-systems and their capabilities in more
detail.
8.1 DisplayPort receiver
PTN3460I implements a DisplayPort receiver consisting of up to 2-lane Main Link and
AUX channel.
PTN3460I implements a high-performance Auto Receive Equalizer and Clock Data
Recovery (CDR) algorithm, with which it identifies and selects an optimal operational
setting for given channel environment. Given that the device is targeted primarily for
embedded Display connectivity, both Display Authentication and Copy Protection
Method 3a (Alternate Scrambler Seed Reset) and Method 3b (Enhanced Framing) are
supported, as per eDP 1.2.
The PTN3460I DPCD registers can be accessed by DP source through AUX channel. It
supports both Native AUX transactions and I2C-over-AUX transactions.
PTN3460I
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Rev. 2 — 19 December 2014
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PTN3460I
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eDP to LVDS bridge for industrial and embedded applications
Native AUX transactions are used to access PTN3460I DisplayPort Configuration Data
(DPCD) registers (for example, to facilitate Link training, check error conditions) and
I2C-over-AUX transactions are used to perform any required access to DDC bus (for
example, EDID reads).
Given that the HPDRX pin is internally connected to GND through an integrated pull-down
resistor (> 100 k), the DP source will see HPDRX pin as LOW indicating that the
DisplayPort receiver is not ready when the device is not powered. This helps avoid raising
false events to the source. After power-up, PTN3460I continues to drive HPDRX pin LOW
until completion of internal initialization. After this, PTN3460I generates HPD signal to
notify DP source and take corrective action(s).
8.1.1 DP Link
PTN3460I is capable of operating either in DP 2-lane or 1-lane mode.
DP 1-lane or 2-lane mode is selected through configuration pin CFG3. See Table 4 for
more details.
Table 4.
CFG3 configuration options
Configuration input setting
DP lane selection
LOW
2-lane DP configuration
HIGH
1-lane DP configuration
8.1.2 DPCD registers
DPCD registers are described in VESA DisplayPort v1.1a/1.2a specifications in detail and
PTN3460I supports DPCD version 1.2.
PTN3460I configuration registers can be accessed through DP AUX channel from the
GPU/CPU, if required. They are defined under vendor-specific region starting at base
address 0x00510h. So any configuration register can be accessed at DPCD address
obtained by adding the register offset and base address.
PTN3460I supports down spreading on DP link and this is reflected in DPCD register
MAX_DOWNSPREAD at address 0003h. Further, the DP source could control
down spreading and inform PTN3460I via DOWNSPREAD_CTRL register at DPCD
register 00107h.
The key aspect is that the system designer must take care that the Input video payload fits
well within both DP link bandwidth and LVDS bandwidth (for a given pixel frequency,
SSC depths) when clock spreading is enabled. Also, another aspect for the system
designer is to ensure LVDS (panel) TCONs are capable of handling SSC modulated LVDS
signaling.
PTN3460I
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Rev. 2 — 19 December 2014
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PTN3460I
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eDP to LVDS bridge for industrial and embedded applications
8.2 LVDS transmitter
The LVDS interface can operate either in Single or Dual LVDS Bus mode at pixel clock
frequencies over the range of 6 MHz to 112 MHz and color depths of 18 bpp or 24 bpp.
Each LVDS bus consists of 3/4 differential data pairs and one clock pair. PTN3460I can
packetize RGB video data, HSYNC, VSYNC, DE either in VESA or JEIDA format. To
enable system EMI reduction, the device can be programmed for center spreading of
LVDS channel clock outputs.
The LVDS interface can be flexibly configured using multi-level configuration pins (CFG1,
CFG2) or via register interface. The configuration pins and the corresponding definitions
are described in Table 5 and Table 6. Nevertheless, as the configuration pins are
designed for general purpose, their definitions can be modified and they can be used for
any other purposes. However, this can be achieved through firmware upgrade only.
Table 5.
Configuration input setting
Number of LVDS links
LOW
single LVDS bus
HIGH
dual LVDS bus
Table 6.
PTN3460I
Product data sheet
CFG1 configuration options
CFG2 configuration options
3-level configuration input setting
Data format
Number of bits per pixel (bpp)
LOW
VESA
24 bpp
OPEN
JEIDA
24 bpp
HIGH
JEIDA or VESA
18 bpp
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Rev. 2 — 19 December 2014
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PTN3460I
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eDP to LVDS bridge for industrial and embedded applications
The VESA and JEIDA data format definitions are described in Table 7 to Table Table 13.
Table 7.
LVDS single bus, 18 bpp, VESA or JEIDA data packing
Channel
Bit position
6
5
4
3
2
1
0
LVDS odd differential channel A
bit 0
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
LVDS odd differential channel B
bit 1
bit 0
bit 5
bit 4
bit 3
bit 2
bit 1
LVDS odd differential channel C
DE
VSYNC
HSYNC
bit 5
bit 4
bit 3
bit 2
Table 8.
LVDS single bus, 24 bpp, VESA data packing
Channel
Bit position
6
5
4
3
2
1
0
LVDS odd differential channel A
bit 0
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
LVDS odd differential channel B
bit 1
bit 0
bit 5
bit 4
bit 3
bit 2
bit 1
bit 4
bit 3
bit 2
bit 6
bit 7
bit 6
LVDS odd differential channel C
DE
VSYNC
HSYNC
bit 5
LVDS odd differential channel D
don’t care
bit 7
bit 6
bit 7
Table 9.
LVDS dual bus, 18 bpp, VESA data packing
Channel
Bit position
6
5
4
3
2
1
0
LVDS odd differential channel A
bit 0
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
LVDS odd differential channel B
bit 1
bit 0
bit 5
bit 4
bit 3
bit 2
bit 1
LVDS odd differential channel C
DE
VSYNC
HSYNC
bit 5
bit 4
bit 3
bit 2
LVDS even differential channel A
bit 0
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
LVDS even differential channel B
bit 1
bit 0
bit 5
bit 4
bit 3
bit 2
bit 1
LVDS even differential channel C
DE
VSYNC
HSYNC
bit 5
bit 4
bit 3
bit 2
Table 10.
LVDS dual bus, 24 bpp, VESA data packing
Channel
Bit position
6
5
4
3
2
1
0
LVDS odd differential channel A
bit 0
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
LVDS odd differential channel B
bit 1
bit 0
bit 5
bit 4
bit 3
bit 2
bit 1
bit 4
bit 3
bit 2
LVDS odd differential channel C
DE
VSYNC
HSYNC
bit 5
LVDS odd differential channel D
don’t care
bit 7
bit 6
bit 7
bit 6
bit 7
bit 6
LVDS even differential channel A
bit 0
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
LVDS even differential channel B
bit 1
bit 0
bit 5
bit 4
bit 3
bit 2
bit 1
bit 4
bit 3
bit 2
bit 6
bit 7
bit 6
LVDS even differential channel C
DE
VSYNC
HSYNC
bit 5
LVDS even differential channel D
don’t care
bit 7
bit 6
bit 7
PTN3460I
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PTN3460I
NXP Semiconductors
eDP to LVDS bridge for industrial and embedded applications
Table 11.
LVDS single bus, 24 bpp, JEIDA data packing
Channel
Bit position
6
5
4
3
2
1
0
LVDS odd differential channel A
bit 2
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
LVDS odd differential channel B
bit 3
bit 2
bit 7
bit 6
bit 5
bit 4
bit 3
LVDS odd differential channel C
DE
VSYNC
HSYNC
bit 7
bit 6
bit 5
bit 4
LVDS odd differential channel D
don’t care
bit 1
bit 0
bit 1
bit 0
bit 1
bit 0
Table 12.
LVDS dual bus, 18 bpp, JEIDA data packing
Channel
Bit position
6
5
4
3
2
1
0
LVDS odd differential channel A
bit 0
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
LVDS odd differential channel B
bit 1
bit 0
bit 5
bit 4
bit 3
bit 2
bit 1
LVDS odd differential channel C
DE
VSYNC
HSYNC
bit 5
bit 4
bit 3
bit 2
LVDS even differential channel A
bit 0
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
LVDS even differential channel B
bit 1
bit 0
bit 5
bit 4
bit 3
bit 2
bit 1
LVDS even differential channel C
DE
VSYNC
HSYNC
bit 5
bit 4
bit 3
bit 2
Table 13.
LVDS dual bus, 24 bpp, JEIDA data packing
Channel
Bit position
6
5
4
3
2
1
0
LVDS odd differential channel A
bit 2
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
LVDS odd differential channel B
bit 3
bit 2
bit 7
bit 6
bit 5
bit 4
bit 3
LVDS odd differential channel C
DE
VSYNC
HSYNC
bit 7
bit 6
bit 5
bit 4
LVDS odd differential channel D
don’t care
bit 1
bit 0
bit 1
bit 0
bit 1
bit 0
LVDS even differential channel A
bit 2
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
LVDS even differential channel B
bit 3
bit 2
bit 7
bit 6
bit 5
bit 4
bit 3
LVDS even differential channel C
DE
VSYNC
HSYNC
bit 7
bit 6
bit 5
bit 4
LVDS even differential channel D
don’t care
bit 1
bit 0
bit 1
bit 0
bit 1
bit 0
PTN3460I delivers great flexibility by supporting more programmable options via I2C-bus
or AUX interface. Please refer to Section 8.3.11 for more details.
PTN3460I
Product data sheet
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PTN3460I
NXP Semiconductors
eDP to LVDS bridge for industrial and embedded applications
8.3 System control and operation
With its combination of embedded microcontroller, non-volatile memory, DPCD AUX and
I2C-bus interfaces, PTN3460I delivers significant value for customer applications by
providing higher degree of control and programmability.
By default, all user controllable registers can be accessed through DPCD AUX interface.
This interface is always enabled. This AUX interface delivers seamless access of
PTN3460I registers to system/platform (GPU) firmware driver. Nevertheless, use of
I2C-bus interface for configuring PTN3460I is left to the choice of system integrator.
DEV_CFG (pin 12) sets up I2C-bus configuration mode:
• Pull-down resistor to GND — PTN3460I operates as I2C-bus slave, low address
(0x40h)
• Open — PTN3460I operates as I2C-bus slave, high address (0xC0h)
• Pull-up resistor to VDD(3V3) — PTN3460I operates as I2C-bus master capable of
reading from external EEPROM
Remark: PTN3460I I2C pins are not failsafe and cannot be connected to the SMBus if the
SMBus has active communications during VDD33 supply switch ON. In the application
there MUST be no MS_I2C traffic during supply rise-up.
8.3.1 Reset and power-on initialization
The device has a built-in reset circuitry that generates internal reset signal after power-on.
All the internal registers and state machines are initialized and the registers take default
values. In addition, PTN3460I has a dedicated control pin RST_N. This serves the same
purpose as power-on reset, but without power cycling of the device/platform.
PTN3460I starts up in a default condition after power-on or after RST_N is toggled from
LOW to HIGH. The configuration pins are sampled at power-on, or external reset, or when
returning from Deep Sleep.
PTN3460I has a built-in reset circuitry that generates internal reset signal after power-on.
All the internal registers and state machines are synchronously initialized and the
registers take default values. Though PTN3460I is designed NOT to need the RST_N pin,
RST_N is still provided. This serves the same purpose as power-on reset, but without
power cycling of the device/platform.
It is good practice to provide for RST_N control if EPS_N is LOW (external 1.8 V supply is
used). In case RST_N is used, it must be released after all supplies are within operating
conditions.
PTN3460I starts up in a default condition after power-on or after RST_N is toggled from
LOW to HIGH. The configuration pins are sampled at power-on and when there is change
of state (for example, from Power saving state to Active state).
Device start-up time from power-on and RST_N = HIGH is 90 ms max.
Remark: Driving RST_N HIGH is not possible and forbidden during power-up, because
the ESD diodes will clamp the signal to the VDDIO+0.6 V. RST_N pin should be left at
Tri-state level during power-up.
PTN3460I
Product data sheet
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Rev. 2 — 19 December 2014
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14 of 38
PTN3460I
NXP Semiconductors
eDP to LVDS bridge for industrial and embedded applications
1.7 V
VDD(1V8)
< 2.5 μs
on-chip
reset_n
td(rstn_i2chz)
< 20 μs
I2C pins
tstartup
< 90 ms
HPD
normal operation
aaa-014260
Fig 4.
Start-up behavior with RST_N and PD_N unconnected
8.3.2 Power-down for Ultra Power Save
PTN3460I goes into Deep power-saving when both PD_N and RST_N are LOW. This will
trigger a power-down sequence.
PD_N and RST_N can be controlled by GPIO pins of system microcontroller. To leave
Deep power-saving state, the system needs to drive PD_N back to HIGH, then issue a
RST_N pulse for at least 10 s. If PD_N pin is open, the device will not enter Deep
power-saving state. Once the device is in Deep power-saving condition, the HPDRX pin
will go LOW automatically and this can be used by the system to remove the 3.3 V supply,
if required.
PTN3460I will not respect the Panel power-down sequence if PD_N is asserted LOW
while video is being streamed to the display; the system is not supposed to toggle PD_N
and RST_N pins asynchronously while the LVDS output is streaming video to the display
panel, but instead follow the panel powering sequence as described in Section 8.3.5.
The time between PD_N going HIGH and HPD raised HIGH by PTN3460I is also 90 ms
max.
PTN3460I
Product data sheet
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Rev. 2 — 19 December 2014
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15 of 38
PTN3460I
NXP Semiconductors
eDP to LVDS bridge for industrial and embedded applications
1.7 V
> 2.5 μs
VDD(1V8)
normal
operation
PD_N
power saving
mode
> 10 μs
td(rstn_i2chz)
RST_N
< 20 μs
I2C pins
tpwrsave
tstartup
< 90 ms
HPD
tstartup
< 90 ms
< 90 ms
normal
operation
aaa-014261
Fig 5.
Start-up behavior with RST_N and PD_N sequence when used
8.3.3 Use GPIOs to control PD_N and RST_N from system side
One example to control PD_N and RST_N pulses from system side is shown below:
•
•
•
•
PTN3460I
Product data sheet
Assert PD_N (make it LOW)
Assert RST_N (make it LOW)
De-assert PD_N (make it HIGH)
De-assert RST_N (make it HIGH)
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Rev. 2 — 19 December 2014
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PTN3460I
NXP Semiconductors
eDP to LVDS bridge for industrial and embedded applications
8.3.4 LVDS panel control
PTN3460I implements eDPv1.2 specific DPCD registers that concern panel power,
backlight and PWM controls and the DP source can issue AUX commands to initiate
panel power-up/down sequence as required. Also, PTN3460I supports LVDS panel
control pins — backlight enable, panel power enable and PWM — that can be set via AUX
commands.
• PVCCEN pin — the signal output is set based on SET_POWER DPCD register
00600h and SET_POWER_CAPABLE bit of
EDP_GENERAL_CAPABILITY_REGISTER_1 DPCD register 00701h and detection
and handling of video data stream by PTN3460I
• BKLTEN pin — the signal output is set based on
BACKLIGHT_PIN_ENABLE_CAPABLE bit of
EDP_GENERAL_CAPABILITY_REGISTER_1 DPCD register 00701h and
BACKLIGHT_ENABLE bit of EDP_DISPLAY_CONTROL_REGISTER DPCD register
00720h
• PWMO pin — the PWM signal generated by PTN3460I based on controls set in
DPCD registers. In addition, PTN3460I can pass through PWM signal from eDP
source as well.
All the panel control enable and signal outputs from PTN3460I are aligned with panel
power-on sequence timing including LVDS video output generation. It is important to note
that the Panel power must be delivered by the system platform and it should be gated by
PVCCEN signal.
PTN3460I
Product data sheet
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PTN3460I
NXP Semiconductors
eDP to LVDS bridge for industrial and embedded applications
8.3.5 Panel power sequencing
Figure 6 illustrates an example of panel power-up/power-down sequence for PTN3460I.
Depending on the source behavior and PTN3460I firmware version, the powering
sequence/timing could have some slight differences.
T12 > 500 ms
VDD(3V3)
LCDVCC
black video
from PTN3460I
T2 < 50 ms
PVCCEN
LVDS interface
T5 < 50 ms
video from source
SINK_STATUS
HPDRX
eDP AUX channel
eDP Main Link
display backlight
AUX channel operational
Link Training
idle
valid video data
disabled
enabled
T3 > 200 ms
to 1000 ms
video or IDLE stream
from DP source
T4 > 200 ms
aaa-009844
T2: Time interval between panel power enable signal (PVCCEN) going HIGH and video data/clock driven on LVDS interface.
T3: Time interval between valid video data/clock on LVDS interface and backlight enable signal (BKLTEN) going HIGH.
T4: Time interval between backlight enable signal (BKLTEN) made LOW and stopping of video data/clock on LVDS interface.
T5: Time interval between stopping of video data/clock on LVDS interface and panel power enable signal (PVCCEN) made
LOW.
T12: Time interval for which PVCCEN is held LOW before it can be made HIGH.
Fig 6.
Panel power-up/power-down sequence example
When working with eDP capable DP sources, PTN3460I supports the following (for
specific sequence, refer to Figure 6):
• After power-on/startup, HPDRX is asserted HIGH, DP source will start AUX
communication for initialization, perform Link Training and starts the video data
stream. Once presence of video data is detected, PTN3460I will assert PVCCEN to
HIGH, synchronize to video stream, output LVDS data and assert rise the Sink_status
lock as indicated in DPCD register (0x00205h). PTN3460I will wait for Backlight
enabling delay (T3) to avoid visual artifacts and program the BKLTEN HIGH.
• While transitioning out of Active state by receiving DPCD 0x600 to set PTN3460I in
D3 mode, PTN3460I will disable BKLTEN prior to cutting off Video streaming to avoid
visible artifacts following specific panel specifications. PTN3460I will assert PVCCEN
to LOW after T5 delay as long as either if the video stream is stopped or video
synchronization is lost. This is to avoid driving the LVDS panel with illegal stream for
long periods of time. It is good practice for sources to keep video data or at least
DP-idle stream active during T4 + T5.
• When PTN3460I is in Low-power state (DisplayPort D3 power state), the LVDS
differential I/Os are weakly pulled down to 0 V. In this state, PVCCEN and BKLTEN
are pulled LOW.
• When PD_N is LOW, which sets PTN3460I in Deep power-saving state, the BKLTEN
pin is set to LOW. LVDS differential I/Os are pulled LOW via the weak pull-downs.
PTN3460I
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Rev. 2 — 19 December 2014
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PTN3460I
NXP Semiconductors
eDP to LVDS bridge for industrial and embedded applications
8.3.6 Termination resistors
The device provides integrated and calibrated 50  termination resistors on both
DisplayPort Main Link lanes and AUX channel.
8.3.7 Reference clock input
PTN3460I does not require an external clock. It relies fully on the clock derived internally
from incoming DP stream or on-chip clock generator.
8.3.8 Power supply
PTN3460I can be flexibly supplied with either 3.3 V supply only or dual supplies
(3.3 V/1.8 V). When supplied with 3.3 V supply only, the integrated regulator is used to
generate 1.8 V for internal circuit operation. In this case, the EPS_N pin must be pulled
HIGH or left open. For optimal power consumption, dual supply option (3.3 V and 1.8 V) is
recommended.
VDD(3V3)
3.0 V
tstartup(VDD1V8)
< 30 μs
VDD(1V8)
1.7 V
aaa-014262
Fig 7.
Internal regulator start-up
• EPS_N pin not connected
• VDD(1V8) total decoupling Cdecap < 8 F total
The 8 F is 4.7 F + 100 nF on pin 19 + 100 nF on pin 45 + 2.2 F + 100 nF on pin 6 +
10 %
8.3.9 Power-on reset
Figure 8 shows a possible curve of the regulated VDD(1v8) voltage with dips at t2 to t3
and t4 to t5. The on-chip reset_n (active LOW) starts active at t0. At t1, the voltage gets
higher than the Vtrip(H) level and if this condition is maintained for a period longer than
Thigh, a delay element will add another Tporp before the on-chip reset_n is de-asserted. If
the voltage drops below Vtrip(L) for a period longer than Tlow, the reset_n is re-asserted.
If the supply dip is shorter (eg. t4 to t5) the internal reset is not asserted. This means that
voltage drops less than Tlow must be avoided in the system.
PTN3460I
Product data sheet
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Rev. 2 — 19 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
19 of 38
PTN3460I
NXP Semiconductors
eDP to LVDS bridge for industrial and embedded applications
VDD(1V8)
Vtrip(H)
Vtrip(L)
supplies
t0
t1
Thigh
t2
Tporp
t3
Tlow
Thigh
t4
t5
[time]
Tporp
on-chip
reset_n
[time]
aaa-014263
Fig 8.
Timing diagram of on-chip power-on reset generator
8.3.10 Power management
In tune with the system application needs, PTN3460I implements aggressive techniques
to support system power management and conservation. The device can exist in one of
the three different states as described below:
• Active state when the device is fully operational.
• Low-power state when DP source issues AUX SET_POWER command on DPCD
register 00600h. In this state, AUX and HPD circuits are operational but the main
DP Link and LVDS Bus are put to high-impedance condition. The device will transition
back to Active state when the DP source sets the corresponding DPCD register bits to
‘DisplayPort D0/Normal Operation mode’. The I2C-bus interface will not be
operational in this state.
• Deep power-saving state: In this state PTN3460I is put to ultra low-power condition.
This is effected when PD_N is LOW. To get back to Active state, PD_N must be made
HIGH. The external interfaces (like I2C, AUX, DP, LVDS, configuration pins) will not be
operational.
8.3.11 Register interface — control and programmability
PTN3460I has a register interface that can be accessed by CPU/GPU or System
Controller to choose settings suitably for the System application needs. The registers can
be read/written either via DP AUX or I2C-bus interface. It is left to system integrator choice
to use an interface to configure PTN3460I.
PTN3460I provides greater level of configurability of certain parameters (e.g., LVDS
output swing, spreading depth, etc.) via registers beyond what is available through pins.
The register settings override the pin values. All registers must be configured during
power-on initialization after HPDRX is HIGH. The registers and bit definitions are
described in “I2C-bus utility and programming guide for firmware and EDID update”
PTN3460I
Product data sheet
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Rev. 2 — 19 December 2014
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20 of 38
PTN3460I
NXP Semiconductors
eDP to LVDS bridge for industrial and embedded applications
8.3.12 EDID handling
The DP source issues EDID reads using I2C-over-AUX transactions and PTN3460I, in
turn, reads from the panel EDID ROM and passes back to the source. To support
seamless functioning of panels without EDID ROM, the PTN3460I can be programmed to
emulate EDID ROM and delivers internally stored EDID information to the source. Given
that EDID is specific to panels, PTN3460I enables system integrator to program EDID
information into embedded memory through DP AUX and I2C-bus interfaces. The
supported EDID ROM emulation size is 896 bytes (seven EDID data structures, each of
128 bytes).
EDID ROM emulation bit is programmed in the configuration table inside the flash
memory. It can also be configured through pin setting. FW will read in the pin settings and
overwrite the configuration table settings. CFG4 pin is used to turn EDID emulation bit
ON/OFF.
Table 14.
CFG4 configuration options
Configuration input setting
pull-down
pull-up
[1]
resistor[1]
resistor[1]
to GND
to VDD(3V3)
Emulation bit on/off selection
Emulation ON, EDID is read from internal flash
Emulation OFF, EDID is read from DDC bus
Pull-up/down resistor value in the range of 1 k to 10 k.
9. Application design-in information
Figure 9 illustrates PTN3460I usage in a system context. The eDP inputs are connected
to DP source port on CPU/GPU and the LVDS outputs are connected to LVDS panel
TCON.
PTN3460I
Product data sheet
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Rev. 2 — 19 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
21 of 38
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
NXP Semiconductors
PTN3460I
1
(optional)
HPD pull-down
is integrated into
R1
silicon (400 kΩ)
100 kΩ
DP_HPD
C15 1
2 0.1 μF
DP_L1n
DP_LANE1P
C16 1
2 0.1 μF
DP_L1p
DP_LANE0N
C17 1
2 0.1 μF
DP_L0n
DP_LANE0P
C18 1
2 0.1 μF
DP_L0p
AUXP
C19 1
2 0.1 μF
DP_AUXP
AUXN
MS_SCL
MS_SDA
C20 1
2 0.1 μF
DP_AUXN
Application diagram
1V8_REG
C13
4.7 μF
1
1
LVSCE_N
LVSCE_P
LVSCKE_N
LVSCKE_P
PVCCEN
LVSDE_N
LVSDE_P
DDC_SDA
DDC_SCL
LVSDO_N
LVSDO_P
LVSAE_N
LVSAE_P
LVSBE_N
LVSBE_P
LVSCE_N
LVSCE_P
LVSCKE_N
LVSCKE_P
PVCCEN
LVSDE_N
LVSDE_P
DDC_SDA
DDC_SCL
BKLTEN
PWMO
option
DEV_CFG 1 R2 2
10 kΩ
open: I2C-bus slave,
high address (0C0h)
LOW: I2C-bus slave (040h)
+3V3
R3
EPS_N
1
PD_N
10 kΩ
1 R4 2
C12
0.1 μF
2
LVSDO_N
LVSDO_P
56
55
54
53
52
51
50
49
48
47
46
45
44
43
LVSAE_N
LVSAE_P
LVSBE_N
LVSBE_P
option
2
DP_LANE1N
42
41
40
39
38
37
36
35
34
33
32
31
30
29
C4
0.1 μF
2
configuration
options
CFG1
CFG2
CFG3
CFG4
10 kΩ
TESTMODE 1 R5 2
10 kΩ
aaa-009845
PTN3460I
22 of 38
© NXP Semiconductors N.V. 2014. All rights reserved.
Fig 9.
optional
2
eDP port or
PCH port D
DP_HPD
LVSCO_N
LVSCO_P
LVSCKO_N
LVSCKO_P
2
C14
1 μF
(25 V)
GND
1
C11
0.01 μF
center pad
2
1
1
C9
1 μF
(25 V)
C10
0.01 μF
2
C8
0.47 μF
+3V3_REG
1
2
2
2
1
1 L3
FB
TESTMODE
CFG1
CFG2
CFG3
MS_SDA
MS_SCL
BKLTEN
CFG4
PWMO
+3V3
PTN3460I
1
PD_N
DP_HPD
DEV_CFG
2
DP_L1p
DP_L1n
LVSAE_N
LVSAE_P
LVSBE_N
LVSBE_P
VDD(3V3)
LVSCE_N
LVSCE_P
LVSCKE_N
LVSCKE_P
PVCCEN
LVSDE_N
LVSDE_P
DDC_SDA
DDC_SCL
n.c.
n.c.
GNDREG
GNDREG
VDD(1V8)
TESTMODE
CFG1
CFG2
CFG3
MS_SDA
MS_SCL
BKLTEN
CFG4
PWMO
DP_L0p
DP_L0n
AUX_N
AUX_P
GND
DP0_P
DP0_N
VDD(1V8)
DP1_P
DP1_N
RST_N
PD_N
HPDRX
DEV_CFG
VDD(3V3)
VDD(3V3)
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
2
2
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
C7
DP_AUXp
0.01 μF
C3
0.1 μF
LVSCO_N
LVSCO_P
LVSCKO_N
LVSCKO_P
eDP to LVDS bridge for industrial and embedded applications
Rev. 2 — 19 December 2014
All information provided in this document is subject to legal disclaimers.
C6
2.2 μF
1
DP_AUXn
C5
0.1 μF
1
2
EPS_N
n.c.
LVSAO_N
LVSAO_P
LVSBO_N
LVSBO_P
VDD(3V3)
LVSCO_N
LVSCO_P
LVSCKO_N
LVSCKO_P
VDD(1V8)
LVSDO_N
LVSDO_P
U1
1V8_DP
1
1 L2
FB
C2
0.1 μF
2
1V8_REG
1
1
+3V3_IO
EPS_N
1V8_REG
2
C1
2.2 μF
LVSAO_N
LVSAO_P
LVSBO_N
LVBSO_P
+3V3_IO
1 L1
FB
LVSAO_N
LVSAO_P
LVSBO_N
LVBSO_P
2
+3.3 V
2
Product data sheet
LVDS panel
and backlight
inverter
PTN3460I
NXP Semiconductors
eDP to LVDS bridge for industrial and embedded applications
10. Limiting values
Table 15. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD
supply voltage
VI
input voltage
Tstg
storage temperature
VESD
electrostatic discharge
voltage
Conditions
Min
Max
Unit
[1]
0.3
+4.6
V
3.3 V CMOS inputs
[1]
0.3
VDD + 0.5 V
65
+150
C
HBM
[2]
-
8000
V
CDM
[3]
-
1000
V
[1]
All voltage values, except differential voltages, are with respect to network ground terminal.
[2]
Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model
– Component level; Electrostatic Discharge Association, Rome, NY, USA.
[3]
Charged-Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing,
Charged-Device Model – Component level; Electrostatic Discharge Association, Rome, NY, USA.
11. Recommended operating conditions
Table 16. Operating conditions
Over operating free-air temperature range, unless otherwise noted.
Symbol
Parameter
Min
Typ
Max
Unit
VDD(3V3)
supply voltage (3.3 V)
3.0
3.3
3.6
V
VDD(1V8)
supply voltage (1.8 V)
1.7
1.8
1.9
V
VI
input voltage
3.3 V CMOS inputs
0
3.3
3.6
V
open-drain I/O with
respect to ground
(e.g., DDC_SCL,
DDC_SDA, MS_SDA,
MS_SCL)
0
5
5.5
V
operating in free air
40
-
+85
C
Tamb
PTN3460I
Product data sheet
Conditions
ambient temperature
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12. Characteristics
12.1 Device characteristics
Table 17. Device characteristics
Over operating free-air temperature range, unless otherwise noted.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tstartup
start-up time
device start-up time from power-on and
RST_N = HIGH; supply voltage within
operating range to specified operating
characteristics
-
-
90
ms
tw(rst)
reset pulse width
device is supplied with valid supply voltage
10
-
-
s
td(rst)
reset delay time[1]
device is supplied with valid supply voltage
-
-
90
ms
td(pwrsave-act)
delay time from
power-save to active
time between PD_N going HIGH and HPD
raised HIGH by PTN3460I; RST_N is HIGH.
-
-
90
ms
Device is supplied with valid supply voltage.
[1]
Time for device to be ready after rising edge of RST_N.
12.2 Power consumption
Table 18. Power consumption
At operating free-air temperature of 25 C and under nominal supply value (unless otherwise noted).
Symbol
Pcons
[1]
Parameter
power
consumption
Conditions
Single supply mode
EPS_N = HIGH
or open
Dual supply mode
EPS_N = LOW
Unit
Min
Typ
Max
Min
Typ
Max
Active mode;
1440  900 at 60 Hz;
24 bits per pixel; dual LVDS bus
[1]
-
430
-
-
290
-
mW
Active mode;
1600  900 at 60 Hz;
24 bits per pixel; dual LVDS bus
[1]
-
448
-
-
305
-
mW
Active mode;
1920  1200 at 60 Hz;
24-bits per pixel; dual LVDS bus
[1]
-
570
-
-
380
-
mW
D3 mode/Power-saving mode;
when PTN3460I is set to
Power-saving mode via
‘SET_POWER’ AUX command by
eDP source; AUX and HPDRX
circuitry are only kept active
-
27
-
-
15
-
mW
Deep power-saving/Shutdown mode;
when PD_N is LOW and the device is
supplied with valid supply voltage
-
5
-
-
2
-
mW
For Active mode power consumption, LVDS output swing of 300 mV is considered.
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eDP to LVDS bridge for industrial and embedded applications
12.3 DisplayPort receiver characteristics
Table 19. DisplayPort receiver main channel characteristics
Over operating free-air temperature range (unless otherwise noted).
Symbol
UI
Parameter
Conditions
unit interval
fDOWN_SPREAD
link clock down spreading
CRX
AC coupling capacitor
VRX_DIFFp-p
differential input peak-to-peak
voltage
Min
Typ
Max
Unit
high bit rate
(2.7 Gbit/s per lane)
[1]
-
370
-
ps
reduced bit rate
(1.62 Gbit/s per lane)
[1]
-
617
-
ps
[2]
0
-
0.5
%
75
-
200
nF
at receiver package pins
high bit rate
(2.7 Gbit/s per lane)
[3]
120
-
-
mV
reduced bit rate
(1.62 Gbit/s per lane)
[3]
40
-
-
mV
RX DC common mode voltage
[4]
0
-
2.0
V
RX short-circuit current limit
[5]
-
-
50
mA
fRX_TRACKING_BW
jitter tracking bandwidth
[6]
Geq(max)
maximum equalization gain
VRX_DC_CM
IRX_SHORT
at 1.35 GHz
20
-
-
MHz
-
15
-
dB
[1]
Range is nominal 350 ppm. DisplayPort channel RX does not require local crystal for channel clock generation.
[2]
Up to 0.5 % down spreading is supported. Modulation frequency range of 30 kHz to 33 kHz is supported.
[3]
Informative; refer to Figure 10 for definition of differential voltage.
[4]
Common-mode voltage is equal to Vbias_RX voltage.
[5]
Total drive current of the input bias circuit when it is shorted to its ground.
[6]
Minimum CDR tracking bandwidth at the receiver when the input is repetition of D10.2 symbols without scrambling.
VD+
VCM
VDIFF_PRE
VDIFF
VD−
002aaf363
pre-emphasis = 20Log(VDIFF_PRE / VDIFF)
Fig 10. Definition of pre-emphasis and differential voltage
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eDP to LVDS bridge for industrial and embedded applications
12.4 DisplayPort AUX characteristics
Table 20.
DisplayPort AUX characteristics
Symbol
UI
tjit(cc)
VAUX_DIFFp-p
Parameter
Conditions
Min
Typ
Max
Unit
unit interval
[1]
0.4
0.5
0.6
s
cycle-to-cycle jitter time
transmitting device
[2]
-
-
0.04
UI
receiving device
[3]
-
-
0.05
UI
transmitting device
[4]
0.39
-
1.38
V
receiving device
[4]
0.32
-
1.36
V

AUX differential peak-to-peak voltage
RAUX_TERM(DC) AUX CH termination DC resistance
VAUX_DC_CM
informative
-
100
-
[5]
0
-
2.0
V
[6]
-
-
0.3
V
AUX short-circuit current limit
[7]
-
-
90
mA
AUX AC coupling capacitor
[8]
75
-
200
nF
AUX DC common-mode voltage
VAUX_TURN_CM AUX turnaround common-mode voltage
IAUX_SHORT
CAUX
[1]
Results in the bit rate of 1 Mbit/s including the overhead of Manchester II coding.
[2]
Maximum allowable UI variation within a single transaction at connector pins of a transmitting device. Equal to 24 ns maximum.
The transmitting device is a source device for a request transaction and a sink device for a reply transaction.
[3]
Maximum allowable UI variation within a single transaction at connector pins of a receiving device. Equal to 30 ns maximum.
The transmitting device is a source device for a request transaction and a sink device for a reply transaction.
[4]
VAUX_DIFFp-p = 2  VAUX_P  VAUX_N.
[5]
Common-mode voltage is equal to Vbias_TX (or Vbias_RX) voltage.
[6]
Steady-state common-mode voltage shift between transmit and receive modes of operation.
[7]
Total drive current of the transmitter when it is shorted to its ground.
[8]
The AUX channel AC-coupling capacitor placed both on the DisplayPort source and sink devices.
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eDP to LVDS bridge for industrial and embedded applications
12.5 LVDS interface characteristics
Table 21.
LVDS interface characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Vo(dif)(p-p)
peak-to-peak differential
output voltage
RL = 100 ;
CFG4 pin is open and LVDS interface
control 2 register in default value
250
300
350
mV
Vo(dif)
differential output voltage
variation
RL = 100 ;
change in differential output voltage
between complementary output states
-
-
50
mV
Vcm
common-mode voltage
RL = 100 
1.125
1.2
1.375
V
IOS
output short-circuit current
RL = 100 
-
-
24
mA
IOZ
OFF-state output current
output 3-state circuit current;
RL = 100 ; LVDS outputs are 3-stated;
receiver biasing at 1.2 V
-
-
20
A
tr
rise time
RL = 100 ; from 20 % to 80 %
-
-
390
ps
tf
fall time
RL = 100 ; from 80 % to 20 %
-
-
390
ps
tsk
skew time
intra-pair skew between differential
pairs
-
-
50
ps
inter-pair skew between 2 adjacent
LVDS channels
-
-
200
ps
minimum modulation depth
-
0
-
%
maximum modulation depth
-
2.5
-
%
30
-
100
kHz
m
modulation index
for center spreading
modulation frequency
fmod
center spreading
12.6 Control inputs and outputs
Table 22.
Control input and output characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Signal output pins — PVCCEN, BKLTEN, HPDRX, PWMO
VOH
HIGH-level output voltage
IOH = 2 mA
2.4
-
-
V
VOL
LOW-level output voltage
IOL = 2 mA
-
-
0.4
V
Control input pins — PD_N, TESTMODE, DEV_CFG, CFG[4:1]
VIH
HIGH-level input voltage
0.7VDD(3V3)
-
-
V
VIL
LOW-level input voltage
-
-
0.3VDD(3V3)
V
Control input pin — EPS_N
VIH
HIGH-level input voltage
0.7VDD(3V3)
-
-
V
VIL
LOW-level input voltage
-
-
0.2VDD(3V3)
V
DDC_SDA, DDC_SCL, MS_SDA,
MS_SCL[1]
VIH
HIGH-level input voltage
0.7VDD(3V3)
-
5.25
V
VIL
LOW-level input voltage
-
-
0.3VDD(3V3)
V
IOL
LOW-level output current
3.0
-
-
mA
[1]
static output; VOL = 0.4 V
For DDC_SCL, DDC_SDA, MS_SCL, MS_SDA characteristics, please refer to UM10204, “I2C-bus specification and user manual”
(Ref. 6).
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12.7 RST_N
Table 23. RST_N characteristics
Over operating free-air temperature range, unless otherwise noted.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
Input characteristics
VIH
HIGH-level input voltage
0.7  VDD(3V3) -
-
VIL
LOW-level input voltage
-
-
0.3  VDD(3V3) V
25
55
90
Ipu(RST_N) pull-up current on
pin RST_N
VI = 0 V
A
12.8 On-chip power-on reset
Table 24.
On-chip power-on reset characteristics
Symbol
Parameter
Min
Typ
Max
Unit
Thigh
time VDD(1V8) has to be above Vtrip(H) before
reset_n will be ‘1’
-
-
2
s
Tlow
time VDD(1V8) has to be below Vtrip(L) before
reset_n will be ‘0’
-
-
11
s
Tporp
minimal time reset_n will be ‘1’ after VDD(1V8)
> Vtrip(H)
0.2
0.32
0.5
s
Vtrip(H)
HIGH trip level
1.0
1.2
1.6
V
Vtrip(L)
LOW trip level
0.95
1.1
1.4
V
s
Td(rstn_i2chz)
delay time for I2C pins (SCL or SDA) to get
into Hi impedance state from the rising edge
of RST_N or internal reset_n
-
-
20[1]
Tstartup
time delay from RST_N or internal reset_n
signal and rising edge of HPD
-
-
90[2]
ms
Tpwrsave
time delay from falling edge of PD_N and
actual HPD falling edge while entering power
saving mode
-
-
90[3]
s
Tw(rst)
minimum requirement for external RST_N
reset pulse width
10
-
-
s
Tstartup(vdd1v8)
internal 1.8 V regulator delay from VDD(3V3)
within specification to VDD(1V8) within
specification
-
-
30[4]
s
[1]
This is based on simulations. In all cases seen in measurement this delay is actually much shorter.
[2]
This is a firmware deadline and the typical value can change with a FW update. The max timing has to be respected and checked at any
FW update.
[3]
This delay is also defined by firmware. The FW polls for DP_N pin state at periods close to 50 ms and this makes the response fluctuate.
[4]
Based on worst-case measurements starting the regulator after VDD(3V3) is 3.0 V. In practical case the regulator starts at much lower
supply level and this value can be considered 0 if input supply has rise time > 1 ms.
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eDP to LVDS bridge for industrial and embedded applications
13. Package outline
HVQFN56: plastic thermal enhanced very thin quad flat package; no leads;
56 terminals; body 7 x 7 x 0.85 mm
D
B
SOT949-2
A
A1
A
A3
terminal 1
index area
E
detail X
e1
C
v
w
b
L
15
28
C A B
A
y
y1 C
29
14
e
e2
Eh 1/2 e
1
terminal 1
index area
42
56
43
e
X
1/2 e
Dh
0
5 mm
scale
Dimensions
Unit
mm
A(1)
A1
max 1.00 0.05
nom 0.85 0.02
min 0.80 0.00
A3
b
D
Dh
E
Eh
e
e1
e2
L
v
0.2
0.30
0.21
0.18
7.1
7.0
6.9
4.85
4.70
4.55
7.1
7.0
6.9
4.05
3.90
3.75
0.4
5.2
5.2
0.5
0.4
0.3
0.1
w
y
0.05 0.05
y1
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
Outline
version
SOT949-2
References
IEC
JEDEC
JEITA
sot949-2_po
European
projection
Issue date
11-09-06
11-09-16
MO-220
Fig 11. Package outline SOT949-2 (HVQFN56)
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eDP to LVDS bridge for industrial and embedded applications
14. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
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eDP to LVDS bridge for industrial and embedded applications
14.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 12) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 25 and 26
Table 25.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
 350
< 2.5
235
220
 2.5
220
220
Table 26.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 12.
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eDP to LVDS bridge for industrial and embedded applications
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 12. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
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15. Soldering: PCB footprint
Footprint information for reflow soldering of HVQFN56 (SOT949-2) package
SOT949-2
Hx
Gx
D
0.125
P
0.125
C
SPx
nSPy nSPx
SPy
Hy
SPx
tot
Gy
SLy By
Ay
Y
SPx tot
SLx
X
0.24
Bx
0.19
Ax
0.85 0.9
occupied area
solder paste deposit
solder land
solder land plus solder paste
0.25
0.5
detail Y
Dimensions in mm
P
Ax
Ay
Bx
By
SLx
SLy
SPx
SPy SPx tot SPy tot
0.4
8
8
6.2
6.2
4.7
4.7
0.7
0.7
Issue date
detail X
Recommended stencil thickness: 0.1 mm
3
3
C
D
nSPx
nSPy
Gx
Gy
Hx
Hy
0.9
0.24
3
3
7.3
7.3
8.25
8.25
14-07-09
14-07-22
sot949-2_fr
Fig 13. SOT949-2 PCB footprint
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16. Abbreviations
Table 27.
PTN3460I
Product data sheet
Abbreviations
Acronym
Description
AIO
All In One
AUX
Auxiliary channel
BIOS
Basic Input/Output System
bpp
bits per pixel
CDM
Charged-Device Model
CDR
Clock Data Recovery
CPU
Central Processing Unit
DDC
Data Display Channel
DP
DisplayPort
DPCD
DisplayPort Configuration Data
EDID
Extended Display Identification Data
eDP
embedded DisplayPort
EMI
ElectroMagnetic Interference
ESD
ElectroStatic Discharge
GPU
Graphics Processor Unit
HBM
Human Body Model
HBR
High Bit Rate (2.7 Gbit/s) of DisplayPort specification
HPD
Hot Plug Detect signal of DisplayPort or LVDS interface
I/O
Input/Output
I2C-bus
Inter-Integrated Circuit bus
IC
Integrated Circuit
LVDS
Low-Voltage Differential Signaling
NVM
Non-Volatile Memory
PCB
Printed-Circuit Board
POR
Power-On Reset
PWM
Pulse Width Modulation (or Modulator)
RBR
Reduced Bit Rate (1.62 Gbit/s) of DisplayPort specification
RGB
Red/Green/Blue
ROM
Read-Only Memory
Rx
Receive
SSC
Spread Spectrum Clock
TCON
Timing CONtroller
Tx
Transmit
UI
Unit Interval
VESA
Video Electronics Standards Association
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
34 of 38
PTN3460I
NXP Semiconductors
eDP to LVDS bridge for industrial and embedded applications
17. References
[1]
VESA DisplayPort standard — version 1, revision 1a; January 11, 2008
[2]
VESA DisplayPort standard — version 1, revision 2a; March 2012
[3]
VESA embedded DisplayPort standard — version 1.2; May 5, 2010
[4]
VESA embedded DisplayPort standard — version 1.1, October 23, 2009
[5]
ANSI/TIA/EIA-644-A-2001, Electrical characteristics of Low Voltage Differential
Signaling (LVDS) Interface Circuits — approved: January 30, 2001
[6]
UM10204, I2C-bus specification and user manual — NXP Semiconductors
18. Revision history
Table 28.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PTN3460I v.2
20141219
Product data sheet
-
PTN3460IBS v.1
Modifications:
PTN3460IBS v.1
PTN3460I
Product data sheet
•
•
•
Changed document name from “PTN3460IBS” to “PTN3460I”.
Table 24 “On-chip power-on reset characteristics”: Updated typ and max values for Tporp.
Updated Figure 4 “Start-up behavior with RST_N and PD_N unconnected” and Figure 5
“Start-up behavior with RST_N and PD_N sequence when used”
20140910
Product data sheet
-
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 December 2014
-
© NXP Semiconductors N.V. 2014. All rights reserved.
35 of 38
PTN3460I
NXP Semiconductors
eDP to LVDS bridge for industrial and embedded applications
19. Legal information
19.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
19.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PTN3460I
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
36 of 38
PTN3460I
NXP Semiconductors
eDP to LVDS bridge for industrial and embedded applications
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
20. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PTN3460I
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
37 of 38
PTN3460I
NXP Semiconductors
eDP to LVDS bridge for industrial and embedded applications
21. Contents
1
2
2.1
2.2
2.3
2.4
2.5
3
4
5
5.1
6
7
7.1
7.2
8
8.1
8.1.1
8.1.2
8.2
8.3
8.3.1
8.3.2
8.3.3
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Device features. . . . . . . . . . . . . . . . . . . . . . . . . 1
DisplayPort receiver features . . . . . . . . . . . . . . 2
LVDS transmitter features. . . . . . . . . . . . . . . . . 2
Control and system features. . . . . . . . . . . . . . . 2
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
System context diagram . . . . . . . . . . . . . . . . . . 3
Ordering information . . . . . . . . . . . . . . . . . . . . . 4
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pinning information . . . . . . . . . . . . . . . . . . . . . . 6
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7
Functional description . . . . . . . . . . . . . . . . . . . 9
DisplayPort receiver . . . . . . . . . . . . . . . . . . . . . 9
DP Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DPCD registers. . . . . . . . . . . . . . . . . . . . . . . . 10
LVDS transmitter. . . . . . . . . . . . . . . . . . . . . . . 11
System control and operation . . . . . . . . . . . . . 14
Reset and power-on initialization . . . . . . . . . . 14
Power-down for Ultra Power Save . . . . . . . . . 15
Use GPIOs to control PD_N and RST_N from
system side. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8.3.4
LVDS panel control . . . . . . . . . . . . . . . . . . . . . 17
8.3.5
Panel power sequencing . . . . . . . . . . . . . . . . 18
8.3.6
Termination resistors . . . . . . . . . . . . . . . . . . . 19
8.3.7
Reference clock input . . . . . . . . . . . . . . . . . . . 19
8.3.8
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . 19
8.3.9
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 19
8.3.10
Power management . . . . . . . . . . . . . . . . . . . . 20
8.3.11
Register interface — control and
programmability . . . . . . . . . . . . . . . . . . . . . . . 20
8.3.12
EDID handling . . . . . . . . . . . . . . . . . . . . . . . . 21
9
Application design-in information . . . . . . . . . 21
10
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 23
11
Recommended operating conditions. . . . . . . 23
12
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 24
12.1
Device characteristics. . . . . . . . . . . . . . . . . . . 24
12.2
Power consumption . . . . . . . . . . . . . . . . . . . . 24
12.3
DisplayPort receiver characteristics . . . . . . . . 25
12.4
DisplayPort AUX characteristics . . . . . . . . . . . 26
12.5
LVDS interface characteristics . . . . . . . . . . . . 27
12.6
Control inputs and outputs . . . . . . . . . . . . . . . 27
12.7
RST_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
12.8
13
14
14.1
14.2
14.3
14.4
15
16
17
18
19
19.1
19.2
19.3
19.4
20
21
On-chip power-on reset . . . . . . . . . . . . . . . . .
Package outline. . . . . . . . . . . . . . . . . . . . . . . .
Soldering of SMD packages . . . . . . . . . . . . . .
Introduction to soldering. . . . . . . . . . . . . . . . .
Wave and reflow soldering. . . . . . . . . . . . . . .
Wave soldering . . . . . . . . . . . . . . . . . . . . . . .
Reflow soldering . . . . . . . . . . . . . . . . . . . . . .
Soldering: PCB footprint . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
References. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
29
30
30
30
30
31
33
34
35
35
36
36
36
36
37
37
38
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 19 December 2014
Document identifier: PTN3460I
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