Data Sheet

PTN3381D
Enhanced performance HDMI/DVI level shifter with voltage
regulator, dongle detection and supporting 3 Gbit/s operation
Rev. 2 — 26 July 2012
Product data sheet
1. General description
The PTN3381D is a high-speed level shifter device which converts four lanes of low-swing
AC-coupled differential input signals to DVI v1.0 and HDMI v1.4b compliant open-drain
current-steering differential output signals, up to 3 Gbit/s to support 36-bit deep color, 3D
and 3 Gbit/s modes. Each of these channels provides a level-shifting differential buffer to
translate from low-swing AC-coupled differential signaling on the source side, to
TMDS-type DC-coupled differential current-mode signaling terminated into 50  to 3.3 V
on the sink side. Additionally, the PTN3381D provides a single-ended active buffer for
voltage translation of the HPD signal from 5 V on the sink side to 3.3 V on the source side
and provides a channel with active buffering and level shifting of the DDC channel
(consisting of a clock and a data line) between 3.3 V source-side and 5 V sink-side. The
DDC channel is implemented using active I2C-bus buffer technology providing capacitive
isolation, redriving and level shifting as well as disablement (isolation between source and
sink) of the clock and data lines.
To provide the highest level of integration in external adapter (or: dongle) applications,
PTN3381D includes an on-board 5 V DC regulator. Its output is designed to provide the
required 5 V power supply to the DVI or HDMI connector, thereby eliminating the need for
a separate external regulator. The on-board regulator needs only two external capacitors
to operate, and its output is active whenever a valid 3.3 V is applied to the PTN3381D VDD
pins.
The low-swing AC-coupled differential input signals to the PTN3381D typically come from
a display source with multi-mode I/O, which supports multiple display standards, for
example, DisplayPort, HDMI and DVI. While the input differential signals are configured to
carry DVI or HDMI coded data, they do not comply with the electrical requirements of the
DVI v1.0 or HDMI v1.3a specification. By using PTN3381D, chip set vendors are able to
implement such reconfigurable I/Os on multi-mode display source devices, allowing the
support of multiple display standards while keeping the number of chip set I/O pins low.
See Figure 1.
The PTN3381D main high-speed differential lanes feature low-swing self-biasing
differential inputs which are compliant to the electrical specifications of DisplayPort
Standard v1.2 and/or PCI Express Standard v1.1, and open-drain current-steering
differential outputs compliant to DVI v1.0 and HDMI v1.4b electrical specifications. The
I2C-bus channel actively buffers as well as level-translates the DDC signals for optimal
capacitive isolation. Its I2C-bus control block also provides for optional software HDMI
dongle detect by issuing a predetermined code sequence upon a read command to an
I2C-bus specified address. The PTN3381D also supports power-saving modes in order to
minimize current consumption when no display is active or connected.
PTN3381D
NXP Semiconductors
Fully integrated HDMI/DVI level shifter supporting 3 Gbit/s operation
The PTN3381D is a fully featured HDMI as well as DVI level shifter. It is functionally
equivalent to PTN3361D but provides an onboard 5 V regulator. The PTN3381D
supersedes PTN3381B, and provides a better high speed performance with a
programmable equalizer.
PTN3381D is powered from a single 3.3 V power supply consuming a small amount of
power (230 mW typical with no load at 5 V regulator) and is offered in a 48-terminal
HVQFN48 package.
MULTI-MODE DISPLAY SOURCE
OE_N
reconfigurable I/Os
PTN3381D
PHY ELECTRICAL
TMDS
coded
data
output buffer
TX
FF
OUT_D4+
OUT_D4−
AC-coupled
differential pair
TMDS data
IN_D4+
DATA LANE
IN_D4−
TX
TMDS
coded
data
output buffer
TX
FF
AC-coupled
differential pair
TMDS data
OUT_D3+
OUT_D3−
IN_D3+
DATA LANE
IN_D3−
TX
output buffer
TX
FF
AC-coupled
differential pair
TMDS data
DATA LANE
OUT_D2+
OUT_D2−
IN_D2+
DVI/HDMI CONNECTOR
TMDS
coded
data
IN_D2−
TX
TMDS
clock
pattern
output buffer
TX
FF
OUT_D1+
OUT_D1−
AC-coupled
differential pair
clock
CLOCK LANE
IN_D1+
IN_D1−
TX
0 V to 3.3 V
quinary input
HPD_SOURCE
HPD_SINK
0 V to 5 V
EQ5
3.3 V
DDC_EN
(0 V to 3.3 V)
3.3 V
DDET
3.3 V
5V
SCL_SOURCE
SCL_SINK
3.3 V
5V
DDC I/O
(I2C-bus)
CONFIGURATION
SDA_SOURCE
SDA_SINK
V5OUT
5 VDC out
002aaf310
Remark: TMDS clock and data lanes can be assigned arbitrarily and interchangeably to D[4:1].
Fig 1.
Typical application system diagram
PTN3381D
Product data sheet
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Rev. 2 — 26 July 2012
© NXP B.V. 2012. All rights reserved.
2 of 30
PTN3381D
NXP Semiconductors
Fully integrated HDMI/DVI level shifter supporting 3 Gbit/s operation
2. Features and benefits
2.1 High-speed TMDS level shifting
 Converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and
HDMI v1.4b compliant open-drain current-steering differential output signals
 TMDS level shifting operation up to 3 Gbit/s per lane (300 MHz character clock)
supporting 36-bit deep color, 3D and 3 Gbit/s modes
 Programmable equalizer
 Integrated 50  termination resistors for self-biasing differential inputs
 Back-current safe outputs to disallow current when device power is off and monitor is
on
 Disable feature to turn off TMDS inputs and outputs and to enter low-power state
2.2 DDC level shifting




Integrated DDC buffering and level shifting (3.3 V source to 5 V sink side)
Rise time accelerator on sink-side DDC ports
100 kHz I2C-bus clock frequency
Back-power safe sink-side terminals to disallow backdrive current when power is off or
when DDC is not enabled
2.3 HDMI dongle detect support
 Incorporates I2C slave ROM
 Responds to DDC read to address 81h with predetermined byte sequence
 Feature enabled by pin DDET (must be enabled for correct operation in accordance
with DisplayPort interoperability guideline)
2.4 HPD level shifting
 HPD non-inverting level shift from 0 V on the sink side to 0 V on the source side, or
from 5 V on the sink side to 3.3 V on the source side
 Integrated 200 k pull-down resistor on HPD sink input guarantees ‘input LOW’ when
no display is plugged in
 Back-power safe design on HPD_SINK to disallow backdrive current when power is off
2.5 5 V DC voltage regulator
 Generates 5 V for the DVI/HDMI connector from the 3.3 V DP_PWR pin supplied by
the DisplayPort connector
 Supports up to 75 mA of load current with an accuracy of 300 mV
 Only two external capacitors required
 Eliminates need for an external 5 V regulator in dongle applications
 Back drive protection on 5 V output
 Short-circuit protection
 Overcurrent protection
PTN3381D
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 26 July 2012
© NXP B.V. 2012. All rights reserved.
3 of 30
PTN3381D
NXP Semiconductors
Fully integrated HDMI/DVI level shifter supporting 3 Gbit/s operation
2.6 General





Power supply 2.85 V to 3.6 V
ESD resilience to 6 kV HBM, 1 kV CDM
Power-saving modes (using output enable)
Back-current-safe design on all sink-side main link, DDC and HPD terminals
Transparent operation: no re-timing or software configuration required
3. Applications
 DisplayPort to HDMI adapters supporting 36-bit deep color, 3D and 3 Gbit/s modes
 DisplayPort to DVI adapters required to drive long cables
4. Ordering information
Table 1.
Ordering information
Type number
PTN3381DBS
PTN3381D
Product data sheet
Package
Name
Description
Version
HVQFN48
plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; SOT619-1
body 7  7  0.85 mm
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Rev. 2 — 26 July 2012
© NXP B.V. 2012. All rights reserved.
4 of 30
PTN3381D
NXP Semiconductors
Fully integrated HDMI/DVI level shifter supporting 3 Gbit/s operation
5. Functional diagram
OE_N
PTN3381D
input bias
enable
50 Ω
OUT_D4+
OUT_D4−
50 Ω
IN_D4+
IN_D4−
EQ
enable
input bias
enable
50 Ω
OUT_D3+
OUT_D3−
50 Ω
IN_D3+
IN_D3−
EQ
enable
input bias
enable
50 Ω
OUT_D2+
OUT_D2−
50 Ω
IN_D2+
IN_D2−
EQ
enable
input bias
enable
50 Ω
IN_D1+
IN_D1−
OUT_D1+
OUT_D1−
50 Ω
EQ
enable
EQ5
HPD level shifter
HPD_SOURCE
(0 V to 3.3 V)
HPD_SINK
(0 V to 5 V)
200 kΩ
DDC_EN (0 V to 3.3 V)
SCL_SOURCE
SDA_SOURCE
I2C-BUS
SLAVE
ROM
SCL_SINK
DDC BUFFER
AND
LEVEL SHIFTER
SDA_SINK
DDET
CP
V5OUT
DC REGULATOR
Creg(ext)
Co(reg)
CN
002aaf311
Fig 2.
PTN3381D
Product data sheet
Functional diagram of PTN3381D
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Rev. 2 — 26 July 2012
© NXP B.V. 2012. All rights reserved.
5 of 30
PTN3381D
NXP Semiconductors
Fully integrated HDMI/DVI level shifter supporting 3 Gbit/s operation
6. Pinning information
37 GND
38 IN_D1−
39 IN_D1+
40 VDD
41 IN_D2−
42 IN_D2+
43 GND
44 IN_D3−
45 IN_D3+
46 VDD
terminal 1
index area
47 IN_D4−
48 IN_D4+
6.1 Pinning
GND
1
36 CP
VDD
2
35 CN
EQ5
3
34 V5OUT
DDET
4
33 VDD
GND
5
32 DDC_EN
REXT
6
HPD_SOURCE
7
SDA_SOURCE
8
29 SDA_SINK
SCL_SOURCE
9
28 SCL_SINK
31 GND
PTN3381DBS
30 HPD_SINK
GND 10
27 GND
VDD 11
26 VDD
GND 24
OUT_D1− 23
OUT_D1+ 22
VDD 21
OUT_D2− 20
OUT_D2+ 19
GND 18
OUT_D3− 17
OUT_D3+ 16
VDD 15
OUT_D4− 14
25 OE_N
OUT_D4+ 13
GND 12
002aaf312
Transparent top view
HVQFN48 package supply ground is connected to both GND pins and exposed center pad. GND
pins and the exposed center pad must be connected to supply ground for proper device operation.
For enhanced thermal, electrical, and board level performance, the exposed pad needs to be
soldered to the board using a corresponding thermal pad on the board and for proper heat
conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad
region.
Fig 3.
Pin configuration for HVQFN48
6.2 Pin description
Table 2.
Pin description
Symbol
Pin
Type
Description
OE_N, IN_Dx and OUT_Dx signals
OE_N
25
3.3 V low-voltage
CMOS single-ended
input
Output Enable and power saving function for high-speed differential
level shifter path.
When OE_N = HIGH:
IN_Dx termination = high-impedance
OUT_Dx outputs = high-impedance; zero output current
When OE_N = LOW:
IN_Dx termination = 50 
OUT_Dx outputs = active
IN_D4+
PTN3381D
Product data sheet
48
Self-biasing
differential input
Low-swing differential input from source. IN_D4+ makes a
differential pair with IN_D4. The input to this pin must be AC
coupled externally.
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PTN3381D
NXP Semiconductors
Fully integrated HDMI/DVI level shifter supporting 3 Gbit/s operation
Table 2.
Pin description …continued
Symbol
Pin
Type
Description
IN_D4
47
Self-biasing
differential input
Low-swing differential input from source. IN_D4 makes a
differential pair with IN_D4+. The input to this pin must be AC
coupled externally.
IN_D3+
45
Self-biasing
differential input
Low-swing differential input from source. IN_D3+ makes a
differential pair with IN_D3. The input to this pin must be AC
coupled externally.
IN_D3
44
Self-biasing
differential input
Low-swing differential input from source. IN_D3 makes a
differential pair with IN_D3+. The input to this pin must be AC
coupled externally.
IN_D2+
42
Self-biasing
differential input
Low-swing differential input from source. IN_D2+ makes a
differential pair with IN_D2. The input to this pin must be AC
coupled externally.
IN_D2
41
Self-biasing
differential input
Low-swing differential input from source. IN_D2 makes a
differential pair with IN_D2+. The input to this pin must be AC
coupled externally.
IN_D1+
39
Self-biasing
differential input
Low-swing differential input from source. IN_D1+ makes a
differential pair with IN_D1. The input to this pin must be AC
coupled externally.
IN_D1
38
Self-biasing
differential input
Low-swing differential input from source. IN_D1 makes a
differential pair with IN_D1+. The input to this pin must be AC
coupled externally.
OUT_D4+
13
TMDS differential
output
HDMI compliant TMDS output. OUT_D4+ makes a differential pair
with OUT_D4. OUT_D4+ is in phase with IN_D4+.
OUT_D4
14
TMDS differential
output
HDMI compliant TMDS output. OUT_D4 makes a differential pair
with OUT_D4+. OUT_D4 is in phase with IN_D4.
OUT_D3+
16
TMDS differential
output
HDMI compliant TMDS output. OUT_D3+ makes a differential pair
with OUT_D3. OUT_D3+ is in phase with IN_D3+.
OUT_D3
17
TMDS differential
output
HDMI compliant TMDS output. OUT_D3 makes a differential pair
with OUT_D3+. OUT_D3 is in phase with IN_D3.
OUT_D2+
19
TMDS differential
output
HDMI compliant TMDS output. OUT_D2+ makes a differential pair
with OUT_D2. OUT_D2+ is in phase with IN_D2+.
OUT_D2
20
TMDS differential
output
HDMI compliant TMDS output. OUT_D2 makes a differential pair
with OUT_D2+. OUT_D2 is in phase with IN_D2.
OUT_D1+
22
TMDS differential
output
HDMI compliant TMDS output. OUT_D1+ makes a differential pair
with OUT_D1. OUT_D1+ is in phase with IN_D1+.
OUT_D1
23
TMDS differential
output
HDMI compliant TMDS output. OUT_D1 makes a differential pair
with OUT_D1+. OUT_D1 is in phase with IN_D1.
HPD and DDC signals
HPD_SINK
30
5 V CMOS
single-ended input
0 V to 5 V (nominal) input signal. This signal comes from the DVI or
HDMI sink. A HIGH value indicates that the sink is connected; a
LOW value indicates that the sink is disconnected. HPD_SINK is
pulled down by an integrated 200 k pull-down resistor.
HPD_SOURCE
7
3.3 V CMOS
single-ended output
0 V to 3.3 V (nominal) output signal. This is level-shifted version of
the HPD_SINK signal.
SCL_SOURCE
9
single-ended 3.3 V
open-drain DDC I/O
3.3 V source-side DDC clock I/O. Pulled up by external termination
to 3.3 V. 5 V tolerant I/O.
SDA_SOURCE
8
single-ended 3.3 V
open-drain DDC I/O
3.3 V source-side DDC data I/O. Pulled up by external termination
to 3.3 V. 5 V tolerant I/O.
PTN3381D
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 26 July 2012
© NXP B.V. 2012. All rights reserved.
7 of 30
PTN3381D
NXP Semiconductors
Fully integrated HDMI/DVI level shifter supporting 3 Gbit/s operation
Table 2.
Pin description …continued
Symbol
Pin
Type
Description
SCL_SINK
28
single-ended 5 V
open-drain DDC I/O
5 V sink-side DDC clock I/O. Pulled up by external termination to
5 V. Provides rise time acceleration for LOW-to-HIGH transitions.
SDA_SINK
29
single-ended 5 V
open-drain DDC I/O
5 V sink-side DDC data I/O. Pulled up by external termination to
5 V. Provides rise time acceleration for LOW-to-HIGH transitions.
DDC_EN
32
3.3 V CMOS input
Enables the DDC buffer and level shifter.
When DDC_EN = LOW, buffer/level shifter is disabled.
When DDC_EN = HIGH, buffer and level shifter are enabled.
Supply and ground
VDD
2, 11, 15,
21, 26, 33,
40, 46
DC supply
GND[1]
1, 5, 10, 12, ground
18, 24, 27,
31, 37, 43
Supply voltage (2.85 V to 3.6 V).
Supply ground. All GND pins must be connected to ground for
proper operation.
Feature control signals
REXT
6
analog I/O
Current sense port used to provide an accurate current reference
for the differential outputs OUT_Dx. For best output voltage swing
accuracy, use of a 10 k resistor (1 % tolerance) from this terminal
to GND is recommended. May also be tied to either VDD or GND
directly (0 ). See Section 7.2 for details.
DDET
4
3.3 V input
Dongle detect enable input. When HIGH, the dongle detect function
via I2C is active. When LOW, the dongle detect function will not
respond to an I2C-bus command. Must be tied to GND or VDD either
directly or via a resistor. Note that this pin may not be left
open-circuit. When used in an HDMI dongle, this pin must be tied
HIGH for correct operation in accordance with DisplayPort
interoperability guidelines. When used in a DVI dongle, this pin
must be tied LOW.
EQ5
3
3.3 V low-voltage
CMOS quinary input
Equalizer setting input pin. This pin can be board-strapped to one of
five decode values: short to GND, resistor to GND, open-circuit,
resistor to VDD, short to VDD. See Table 4 for truth table.
Voltage regulator terminals
CP
36
analog high-voltage
Positive terminal for the voltage regulator external capacitor.[2]
CN
35
analog high-voltage
Negative terminal for the voltage regulator external capacitor.[2]
V5OUT
34
power output
5 V regulated output from the integrated voltage regulator.[2]
[1]
HVQFN48 package supply ground is connected to both GND pins and exposed center pad. GND pins and the exposed center pad must
be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed
pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the
board, thermal vias need to be incorporated in the PCB in the thermal pad region.
[2]
A ceramic capacitor with ESR < 100 m is recommended and should be placed close to the pin(s).
PTN3381D
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 26 July 2012
© NXP B.V. 2012. All rights reserved.
8 of 30
PTN3381D
NXP Semiconductors
Fully integrated HDMI/DVI level shifter supporting 3 Gbit/s operation
7. Functional description
Refer to Figure 2 “Functional diagram of PTN3381D”.
The PTN3381D level shifts four lanes of low-swing AC-coupled differential input signals to
DVI and HDMI compliant open-drain current-steering differential output signals, up to
3 Gbit/s per lane to support 36-bit deep color, 3D and 3 Gbit/s modes. It has integrated
50  termination resistors for AC-coupled differential input signals. An enable signal
OE_N can be used to turn off the TMDS inputs and outputs, thereby minimizing power
consumption. The TMDS outputs are back-power safe to disallow current flow from a
powered sink while the PTN3381D is unpowered.
The PTN3381D’s DDC channel provides active level shifting and buffering, allowing 3.3 V
source-side termination and 5 V sink-side termination. The sink-side DDC ports are
equipped with a rise time accelerator enabling drive of long cables or high bus
capacitance. This enables the system designer to isolate bus capacitance to meet HDMI
DDC specification. Furthermore, the DDC channel is augmented with an I2C-bus slave
ROM device that provides optional HDMI dongle detect response, which can be enabled
by dongle detect signal DDET. The PTN3381D offers back-power safe sink-side I/Os to
disallow backdrive current from the DDC clock and data lines when power is off or when
DDC is not enabled. An enable signal DCC_EN enables the DDC level shifter block.
Remark: When used in an HDMI dongle, the DDET function must be enabled for correct
operation in accordance with DisplayPort interoperability guidelines. When used in a DVI
dongle, the DDET function must be disabled.
The PTN3381D also provides voltage translation for the Hot Plug Detect (HPD) signal
from 0 V to 5 V on the sink side to 0 V to 3.3 V on the source side.
PTN3381D includes an onboard 5 VDC regulator, designed to provide the required 5 V
power supply to the DVI or HDMI connector, thereby eliminating the need for a separate
external regulator. The onboard regulator needs only two external capacitors to operate,
and its output is active whenever a valid 3.3 V is applied to the PTN3381D VDD pins. The
back drive protection on 5 V output prevents back-drive current from 5 V output to the
input supply. The short-circuit protection limits current flowing through the supply, and the
overcurrent protection prevents overload conditions at the charge pump output.
The PTN3381D does not re-time any data. It contains no state machines except for the
DDC/I2C-bus block. No inputs or outputs of the device are latched or clocked. Because
the PTN3381D acts as a transparent level shifter, no reset is required.
PTN3381D
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 26 July 2012
© NXP B.V. 2012. All rights reserved.
9 of 30
PTN3381D
NXP Semiconductors
Fully integrated HDMI/DVI level shifter supporting 3 Gbit/s operation
7.1 Enable and disable features
PTN3381D offers different ways to enable or disable functionality, using the Output
Enable (OE_N), and DDC Enable (DDC_EN) inputs. Whenever the PTN3381D is
disabled, the device will be in standby mode and power consumption will be minimal;
otherwise the PTN3381D will be in active mode and power consumption will be nominal.
These two inputs each affect the operation of PTN3381D differently: OE_N controls the
TMDS channels, DDC_EN affects only the DDC channel, and HPD_SINK does not affect
either of the channels. The following sections and truth table describe their detailed
operation.
7.1.1 Hot plug detect
The HPD channel of PTN3381D functions as a level-shifting buffer to pass the HPD logic
signal from the display sink device (via input HPD_SINK) on to the display source device
(via output HPD_SOURCE).
The output logic state of HPD_SOURCE output always follows the logic state of input
HPD_SINK, regardless of whether the device is in active or standby mode.
7.1.2 Output Enable function (OE_N)
When input OE_N is asserted (active LOW), the IN_Dx and OUT_Dx signals are fully
functional. Input termination resistors are enabled and the internal bias circuits are turned
on.
When OE_N is de-asserted (inactive HIGH), the OUT_Dx outputs are in a
high-impedance state and drive zero output current. The IN_Dx input buffers are disabled
and IN_Dx termination is disabled. Power consumption is minimized.
Remark: Note that OE_N signal level has no influence on the HPD_SINK input,
HPD_SOURCE output, or the SCL and SDA level shifters. A transition from HIGH to LOW
at OE_N may disable the DDC channel for up to 20 s.
7.1.3 DDC channel enable function (DDC_EN)
The DDC_EN pin is active HIGH and can be used to isolate a badly behaved slave. When
DDC_EN is LOW, the DDC channel is turned off. The DDC_EN input should never
change state during an I2C-bus operation. Note that disabling DDC_EN during a bus
operation may hang the bus, while enabling DDC_EN during bus traffic would corrupt the
I2C-bus operation. Hence, DDC_EN should only be toggled while the bus is idle. (See
I2C-bus specification).
PTN3381D
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 26 July 2012
© NXP B.V. 2012. All rights reserved.
10 of 30
PTN3381D
NXP Semiconductors
Fully integrated HDMI/DVI level shifter supporting 3 Gbit/s operation
7.1.4 Enable/disable truth table
Table 3.
HPD_SINK, OE_N and DDC_EN enabling truth table
Inputs
Channels
HPD_SINK OE_N
Mode
OUT_Dx[3]
DDC_EN IN_Dx
DDC[4]
HPD_SOURCE[5]
[1]
[2]
LOW
LOW
LOW
50  termination enabled
to VRX(bias)
high-impedance
LOW
Active; DDC
disabled
LOW
LOW
HIGH
50  termination enabled
to VRX(bias)
SDA_SINK
connected to
SDA_SOURCE
and SCL_SINK
connected to
SCL_SOURCE
LOW
Active; DDC
enabled
LOW
HIGH
LOW
high-impedance
high-impedance;
zero output current
high-impedance
LOW
Standby
LOW
HIGH
HIGH
high-impedance
high-impedance;
zero output current
SDA_SINK
connected to
SDA_SOURCE
and SCL_SINK
connected to
SCL_SOURCE
LOW
Standby;
DDC
enabled
HIGH
LOW
LOW
50  termination enabled
to VRX(bias)
high-impedance
HIGH
Active; DDC
disabled
HIGH
LOW
HIGH
50  termination enabled
to VRX(bias)
SDA_SINK
connected to
SDA_SOURCE
and SCL_SINK
connected to
SCL_SOURCE
HIGH
Active; DDC
enabled
HIGH
HIGH
LOW
high-impedance
high-impedance;
zero output current
high-impedance
HIGH
Standby
HIGH
HIGH
HIGH
high-impedance
high-impedance;
zero output current
SDA_SINK
connected to
SDA_SOURCE
and SCL_SINK
connected to
SCL_SOURCE
HIGH
Standby;
DDC
enabled
[1]
A HIGH level on input OE_N disables only the TMDS channels.
[2]
A LOW level on input DDC_EN disables only the DDC channel.
[3]
OUT_Dx channels ‘enabled’ means outputs OUT_Dx toggling in accordance with IN_Dx differential input voltage switching.
[4]
DDC channel ‘enabled’ means SDA_SINK is connected to SDA_SOURCE and SCL_SINK is connected to SCL_SOURCE.
[5]
The HPD_SOURCE output logic state always follows the HPD_SINK input logic state.
PTN3381D
Product data sheet
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Fully integrated HDMI/DVI level shifter supporting 3 Gbit/s operation
7.2 Analog current reference
The REXT pin (pin 6) is an analog current sense port used to provide an accurate current
reference for the differential outputs OUT_Dx. For best output voltage swing accuracy,
use of a 10 k resistor (1 % tolerance) connected between this terminal and GND is
recommended.
If an external 10 k  1 % resistor is not used, this pin can be connected to GND or VDD
directly (0 ) to use the internal resistor. In any of these cases, the output will function
normally but at reduced accuracy over voltage and temperature of the following
parameters: output levels (VOL), differential output voltage swing, and rise and fall time
accuracy.
7.3 Equalizer
The PTN3381D supports 5 level equalization setting by the quinary input pin EQ5.
Table 4.
Equalizer settings
Inputs
Quinary notation
Equalizer mode
short to GND
05
0 dB
10 k resistor to GND
15
2 dB
open-circuit
25
3.5 dB
10 k resistor to VDD
35
9 dB
short to VDD
45
7 dB
EQ5
7.4 Backdrive current protection
The PTN3381D is designed for backdrive prevention on all sink-side TMDS outputs,
sink-side DDC I/Os and the HPD_SINK input. This supports user scenarios where the
display is connected and powered, but the PTN3381D is unpowered. In these cases, the
PTN3381D will sink no more than a negligible amount of leakage current, and will block
the display (sink) termination network from driving the power supply of the PTN3381D or
that of the inactive DVI or HDMI source.
7.5 Active DDC buffer with rise time accelerator
The PTN3381D DDC channel, besides providing 3.3 V to 5 V level shifting, includes
active buffering and rise time acceleration which allows up to 18 meters bus extension for
reliable DDC applications. While retaining all the operating modes and features of the
I2C-bus system during the level shifts, it permits extension of the I2C-bus by providing
bidirectional buffering for both the data (SDA) and the clock (SCL) line as well as the
rise time accelerator on the sink-side port (SCL_SINK and SDA_SINK) enabling the bus
to drive a load up to 1400 pF or distance of 18 m on the sink-side port, and 400 pF on the
source-side port (SCL_SOURCE and SCA_SOURCE). Using the PTN3381D for DVI or
HDMI level shifting enables the system designer to isolate bus capacitance to meet HDMI
DDC specification. The SDA and SCL pins are overvoltage tolerant and are
high-impedance when the PTN3381D is unpowered or when DDC_EN is LOW.
PTN3381D
Product data sheet
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Fully integrated HDMI/DVI level shifter supporting 3 Gbit/s operation
PTN3381D has rise time accelerators on the sink-side port (SCL_SINK and SDA_SINK)
only. During positive bus transitions on the sink-side port, a current source is switched on
to quickly slew the SCL_SINK and SDA_SINK lines HIGH once the 5 V DDC bus VIL
threshold level of around 1.5 V is exceeded, and turns off as the 5 V DDC bus VIH
threshold voltage of approximately 3.5 V is approached.
7.6 I2C-bus based HDMI dongle detection
The PTN3381D includes an on-board I2C-bus slave ROM which provides a means to
detect the presence of an HDMI dongle by the system through the DDC channel,
accessible via ports SDA_SOURCE and SCL_SOURCE. This allows system vendors to
detect HDMI dongle presence through the already available DDC/I2C-bus port using a
predetermined bus sequence. Please see Section 8 for more information.
For the I2C-bus HDMI Dongle Detect function to be active, input pin DDET (dongle detect)
should be tied HIGH. When DDET is LOW, the PTN3381D will not respond to an I2C-bus
command. When used in an HDMI dongle, the DDET function must be enabled for
correct operation in accordance with DisplayPort interoperability guidelines. When used in
a DVI dongle, the DDET function must be disabled.
The HDMI dongle detection is accomplished by accessing the PTN3381D on-board
I2C-bus slave ROM using a simple sequential I2C-bus Read operation as described
below.
7.6.1 Slave address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
1
0
0
0
0
0
0
R/W
slave address
002aad340
R = 1; W = 0
Fig 4.
PTN3381D
Product data sheet
PTN3381D slave address
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7.6.2 Read operation
The slave device address of PTN3381D is 80h. PTN3381D will respond to a Read
command to slave address 81h (PTN3381D will respond with an ACK to a Write
command to address 80h). Following the Read command, the PTN3381D will respond
with the contents of its internal ROM, as a sequence of 16 bytes, for as long as the master
continues to issue clock edges with an acknowledge after each byte. The 16-byte
sequence represents the ‘DP-HDMI ADAPTOR<EOT>’ symbol converted to ASCII and is
documented in Table 5.
The PTN3381D auto-increments its internal ROM address pointer (0h through Fh) as long
as it continues to receive clock edges from the master with an acknowledge after each
byte. If the master continues to issue clock edges past the 16th byte, the PTN3381D will
respond with a data byte of FFh. If the master does not acknowledge a received byte, the
PTN3381D internal address pointer will be reset to 0 and a new Read sequence should
be started by the master. Access to the 16-byte is by sequential read only as described
above; there is no random-access possible to any specific byte in the ROM.
Table 5.
DisplayPort - HDMI Adaptor Detection ROM content
Internal pointer
offset (hex)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Data (hex)
44
50
2D
48
44
4D
49
20
41
44
41
50
54
4F
52
04
Table 6.
HDMI dongle detect transaction sequence outline
Phase I2C transaction
Transmitting
Bit
7
1
START
master
2
Write command
master
3
Acknowledge
slave
4
Word address offset
master
5
Acknowledge
slave
6
STOP
7
START
8
Read command
master
9
Acknowledge
slave
Slave
optional
-
mandatory
master
optional
-
master
mandatory
-
mandatory
-
-
mandatory
Read data
slave
13
:
:
:
:
:
40
Read data
slave
41
Not Acknowledge
42
STOP
0
Master
-
12
0
R/W
-
slave
0
1
optional
master
0
2
-
Read data
0
3
mandatory
Acknowledge
0
4
-
11
0
5
optional
10
1
6
Status
word address offset data byte
1
0
0
0
0
0
data byte at offset 0
data byte at offset 1
0
1
-
mandatory
mandatory
-
-
mandatory
-
-
-
-
-
mandatory
master
mandatory
-
master
mandatory
-
data byte at offset 15
Remark: If the slave does not acknowledge the above transaction sequence, the entire
sequence should be retried by the source.
PTN3381D
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Fully integrated HDMI/DVI level shifter supporting 3 Gbit/s operation
7.7 Characteristics of the I2C-bus
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a Serial DAta line (SDA) and a Serial Clock Line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
7.7.1 Bit transfer
One data bit is transferred during each clock phase. The data on the SDA line must
remain stable during the HIGH period of the clock pulse as changes in the data line at this
time will be interpreted as control signals (see Figure 5).
SDA
SCL
data line
stable;
data valid
Fig 5.
change
of data
allowed
mba607
Bit transfer
7.7.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P). See Figure 6.
SDA
SCL
S
P
START condition
STOP condition
mba608
Fig 6.
Definition of START and STOP conditions.
7.7.3 System configuration
An I2C-bus device generating a message is a ‘transmitter’, a device receiving is the
‘receiver’. The device that controls the message is the ‘master’ and the devices which are
controlled by the master are the ‘slaves’. See Figure 7.
PTN3381D
Product data sheet
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Fully integrated HDMI/DVI level shifter supporting 3 Gbit/s operation
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
002aaa381
Fig 7.
System configuration
7.7.4 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also, a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse, set-up and hold
times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating as
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from master
1
2
S
START
condition
Fig 8.
PTN3381D
Product data sheet
8
9
clock pulse for
acknowledgement
002aaa987
Acknowledgement on the I2C-bus
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8. Application design-in information
8.1 Dongle or cable adaptor detect discovery mechanism
The PTN3381D supports the source-side dongle detect discovery mechanism described
in VESA DisplayPort Interoperability Guideline Version 1.1a.
When a source-side cable adaptor is plugged into a multi-mode source device that
supports multiple standards such as DisplayPort, DVI and HDMI, a discovery mechanism
is needed for the multi-mode source to configure itself for outputting DisplayPort, DVI or
HDMI compliant signals through the dongle or cable adaptor. The discovery mechanism
ensures that a multi-mode source device only sends either DVI or HDMI signals when a
valid DVI or HDMI cable adaptor is present.
The VESA Interoperability Guideline recommends that a multi-mode source to power up
with both DDC and AUX CH disabled. After initialization, the source device can use a
variety of mechanisms to decide whether a dongle or cable adaptor is present by
detecting pin 13 on the DisplayPort connector. Depending on the voltage level detected at
pin 13, the source configures itself either:
• as a DVI or HDMI source (see below paragraph for detection between DVI and
HDMI), and enables DDC, while keeping AUX CH disabled, or
• as a DisplayPort source and enables AUX CH, while keeping DDC disabled.
The monitoring of the voltage level on pin 13 by a multi-mode source device is optional. A
multi-mode source may also, for example, attempt an AUX CH read transaction and, if the
transaction fails, a DDC transaction to discover the presence/absence of a cable adaptor.
Furthermore, a source that supports both DVI and HDMI can discover whether a DVI or
HDMI dongle or cable adaptor is present by using a variety of discovery procedures. One
possible method is to check the voltage level of pin 14 of the DisplayPort connector.
Pin 14 also carries CEC signal used for HDMI. Please note that other HDMI devices on
the CEC line may be momentarily pulling down pin 14 as a part of CEC protocol.
The VESA Interoperability Guideline recommends that a multi-mode source should
distinguish a source-side HDMI cable adaptor from a DVI cable adaptor by checking the
DDC buffer ID as described in Section 7.6 “I2C-bus based HDMI dongle detection”. While
it is optional for a multi-mode source to use the I2C-bus based HDMI dongle detection
mechanism, it is mandatory for HDMI dongle or cable adaptor to respond to the I2C-bus
read command described in Section 7.7. The PTN3381D provides an integrated I2C-bus
slave ROM to support this mandatory HDMI dongle detect mechanism for HDMI dongles.
For a DisplayPort-to-HDMI source-side dongle or cable adaptor, DDET must be tied HIGH
to enable the I2C-based HDMI dongle detection response function of PTN3381D. For a
DisplayPort-to-DVI sink-side dongle or cable adaptor, DDET must be tied LOW to disable
the function.
PTN3381D
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PTN3381D
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Fully integrated HDMI/DVI level shifter supporting 3 Gbit/s operation
9. Limiting values
Table 7.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD
supply voltage
VI
input voltage
Conditions
RL
load resistance
Tstg
storage temperature
VESD
electrostatic discharge
voltage
Min
Max
Unit
0.3
+4.6
V
3.3 V CMOS inputs
0.3
VDD + 0.5
V
5.0 V CMOS inputs
0.3
6.0
V
5 V regulator output
66
-

65
+150
C
HBM
[1]
-
6000
V
CDM
[2]
-
1000
V
[1]
Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model Component level; Electrostatic Discharge Association, Rome, NY, USA.
[2]
Charged Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing, Charged Device
Model - Component level; Electrostatic Discharge Association, Rome, NY, USA.
10. Recommended operating conditions
Table 8.
Recommended operating conditions
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD
supply voltage
2.85
3.3
3.6
V
VI
input voltage
3.3 V CMOS inputs
0
-
3.6
V
VI(AV)
average input
voltage
IN_Dn+, IN_Dn inputs
[1]
0
-
5.5
V
-
0
-
V
Rref(ext)
external reference
resistance
connected between pin
REXT (pin 6) and GND
[2]
-
10 ± 1 %
-
k
Co(reg)
regulator output
capacitance
external capacitor on
pin V5OUT
[3]
-
1
-
F
Creg(ext)
external regulator
capacitance
from pin CP to pin CN
[3]
-
330
-
nF
Tamb
ambient temperature operating in free air
40
-
+85
C
5.0 V CMOS inputs
PTN3381D
Product data sheet
[1]
Input signals to these pins must be AC-coupled.
[2]
Operation without external reference resistor is possible but will result in reduced output voltage swing
accuracy. For details, see Section 7.2.
[3]
A ceramic capacitor with ESR < 100 m is recommended and should be placed close to the pin(s).
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Fully integrated HDMI/DVI level shifter supporting 3 Gbit/s operation
10.1 Current consumption
Table 9.
Current consumption
Symbol
Parameter
Conditions
IDD
supply current
OE_N = 0; Active mode
Min
Typ
Max
Unit
no load
-
70
100
mA
with 75 mA load
-
200
300
mA
-
-
7
mA
OE_N = 1 and DDC_EN = 0;
Standby mode; no load
11. Characteristics
11.1 Differential inputs
Table 10.
Differential input characteristics for IN_Dx signals
Symbol
Parameter
Min
Typ
Max
Unit
UI
unit interval[1]
Conditions
[2]
333
-
4000
ps
VRX_DIFFp-p
differential input peak-to-peak voltage
[3]
0.175
-
1.200
V
tRX_EYE
receiver eye time
minimum eye width at
IN_Dx input pair
0.8
-
-
UI
Vi(cm)M(AC)
peak common-mode input voltage (AC)
includes all frequencies
above 30 kHz
-
-
100
mV
ZRX_DC
DC input impedance
40
50
60

VRX(bias)
bias receiver voltage
ZI(se)
single-ended input impedance
inputs in
high-impedance state
[4]
[5]
1.0
1.2
1.4
V
100
-
-
k
[1]
UI (unit interval) = tbit (bit time).
[2]
UI is determined by the display mode. Nominal bit rate ranges from 250 Mbit/s to 2.5 Gbit/s per lane. Nominal UI at 2.5 Gbit/s = 400 ps.
360 ps = 400 ps  10 %.
[3]
VRX_DIFFp-p = 2  VRX_D+  VRX_D. Applies to IN_Dx signals.
[4]
Vi(cm)M(AC) = VRX_D+ + VRX_D / 2  VRX(cm).
VRX(cm) = DC (avg) of VRX_D+ + VRX_D / 2.
[5]
Differential inputs will switch to a high-impedance state when OE_N is HIGH.
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PTN3381D
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Fully integrated HDMI/DVI level shifter supporting 3 Gbit/s operation
11.2 Differential outputs
The level shifter’s differential outputs are designed to meet HDMI version 1.4b and
DVI version 1.0 specifications.
Table 11.
Symbol
Differential output characteristics for OUT_Dx signals
Parameter
Conditions
Min
Typ
VTT  0.01 VTT
Max
Unit
VOH(se)
single-ended HIGH-level
output voltage
[1]
VOL(se)
single-ended LOW-level
output voltage
[2]
VTT  0.60 VTT  0.50 VTT  0.40 V
VO(se)
single-ended output
voltage variation
logic 1 and logic 0 state applied
respectively to differential inputs
IN_Dn; Rref(ext) connected;
see Table 8
[3]
400
500
600
mV
IOZ
OFF-state output current
single-ended
-
-
10
A
tr
rise time
20 % to 80 %
75
-
240
ps
tf
fall time
80 % to 20 %
skew time
tsk
tjit(add)
added jitter time
VTT + 0.01 V
75
-
240
ps
intra-pair
[4]
-
-
10
ps
inter-pair
[5]
-
-
250
ps
jitter contribution by IC,
PRBS7 pattern
[6]
-
10
-
ps
[1]
VTT is the DC termination voltage in the HDMI or DVI sink. VTT is nominally 3.3 V.
[2]
The open-drain output pulls down from VTT.
[3]
Swing down from TMDS termination voltage (3.3 V  10 %).
[4]
This differential skew budget is in addition to the skew presented between IN_Dn+ and IN_Dn paired input pins.
[5]
This lane-to-lane skew budget is in addition to skew between differential input pairs.
[6]
Jitter budget for differential signals as they pass through the level shifter.
11.3 HPD_SINK input, HPD_SOURCE output
Table 12.
HPD characteristics
Symbol
Parameter
Conditions
VIH
HIGH-level input voltage
HPD_SINK
Min
Typ
Max
Unit
2.0
5.0
5.3
V
VIL
LOW-level input voltage
HPD_SINK
0
-
0.8
V
ILI
input leakage current
HPD_SINK
-
-
15
A
[1]
VOH
HIGH-level output voltage
HPD_SOURCE
2.5
-
VDD
V
VOL
LOW-level output voltage
HPD_SOURCE
0
-
0.2
V
tPD
propagation delay
from HPD_SINK to HPD_SOURCE;
50 % to 50 %
[2]
-
-
200
ns
tt
transition time
HPD_SOURCE rise/fall; 10 % to 90 %
[3]
1
-
20
ns
Rpd
pull-down resistance
HPD_SINK input pull-down resistor
[4]
100
200
300
k
[1]
Low-speed input changes state on cable plug/unplug.
[2]
Time from HPD_SINK changing state to HPD_SOURCE changing state. Includes HPD_SOURCE rise/fall time.
[3]
Time required to transition from VOH to VOL or from VOL to VOH.
[4]
Guarantees HPD_SINK is LOW when no display is plugged in.
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11.4 OE_N, DDC_EN and DDET inputs
Table 13.
OE_N, DDC_EN and DDET input characteristics
Symbol
Parameter
VIH
HIGH-level input voltage
VIL
LOW-level input voltage
input leakage current
ILI
[1]
Conditions
[1]
OE_N pin
Min
Typ
2.0
-
-
Max
Unit
V
-
0.8
V
-
10
A
Measured with input at VIH maximum and VIL minimum.
11.5 DDC characteristics
Table 14.
Symbol
DDC characteristics
Parameter
Conditions
Min
Typ
Max
Unit
Input and output SCL_SOURCE and SDA_SOURCE, VCC1 = 2.85 V to 3.6 V[1]
VIH
HIGH-level input voltage
0.7VCC1
-
3.6
V
VIL
LOW-level input voltage
0.5
-
+0.4
V
ILI
input leakage current
VI = 3.6 V
-
-
10
A
IIL
LOW-level input current
VI = 0.2 V
-
-
10
A
VOL
LOW-level output voltage
IOL = 100 A or 6 mA
0.47
0.52
0.6
V
VOLVIL
difference between LOW-level output
and LOW-level input voltage
guaranteed by design to
prevent contention
-
70
-
mV
Cio
input/output capacitance
VI = 3 V or 0 V; VDD = 3.3 V
-
6
7
pF
VI = 3 V or 0 V; VDD = 0 V
-
6
7
pF
Input and output SDA_SINK and SCL_SINK, VCC2 = 4.5 V to 5.5
V[2]
VIH
HIGH-level input voltage
0.7VCC2
-
5.5
V
VIL
LOW-level input voltage
0.5
-
+1
V
ILI
input leakage current
VI = 5.5 V
-
-
10
A
IIL
LOW-level input current
VI = 0.2 V
-
-
10
A
VOL
LOW-level output voltage
IOL = 6 mA
-
0.1
0.2
V
Cio
input/output capacitance
VI = 3 V or 0 V; VDD = 3.3 V
-
-
7
pF
VI = 3 V or 0 V; VDD = 0 V
-
6
7
pF
VCC2 = 4.5 V;
slew rate = 1.25 V/s
-
4
-
mA
Itrt(pu)
transient boosted pull-up current
[1]
VCC1 is the pull-up voltage for DDC source.
[2]
VCC2 is the pull-up voltage for DDC sink.
PTN3381D
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11.6 5 V DC regulator characteristics
Table 15.
5 V DC regulator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VO
output voltage
5 V regulator output
4.7
5
5.3
V
Iload
load current
5 V regulator output
VDD = 3.0 V to 3.6 V
-
-
75
mA
VDD = 2.85 V
-
-
60
mA
100
150
200
mA
-
-
10
A
IO(sc)
short-circuit output current
Ibckdrv
backdrive current
5 V regulator output
Vo(ripple)(p-p)
peak-to-peak ripple output voltage
Co(reg) = 1 F

efficiency
Iload > 10 mA
[1]
[1]
-
250
400
mV
70
75
80
%
Recommend low ESR ceramic output capacitor of 2 F to reduce the output ripple.
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12. Package outline
HVQFN48: plastic thermal enhanced very thin quad flat package; no leads;
48 terminals; body 7 x 7 x 0.85 mm
A
B
D
SOT619-1
terminal 1
index area
A
E
A1
c
detail X
C
e1
e
1/2
e
24
y
y1 C
v M C A B
w M C
b
13
L
25
12
e
e2
Eh
1/2
1
e
36
terminal 1
index area
48
37
Dh
X
0
2.5
scale
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A(1)
max.
A1
b
1
0.05
0.00
0.30
0.18
5 mm
c
D (1)
Dh
E (1)
Eh
0.2
7.1
6.9
5.25
4.95
7.1
6.9
5.25
4.95
e
e1
5.5
0.5
e2
L
v
5.5
0.5
0.3
0.1
w
0.05
y
y1
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
Fig 9.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT619-1
---
MO-220
---
EUROPEAN
PROJECTION
ISSUE DATE
01-08-08
02-10-18
Package outline SOT619-1 (HVQFN48)
PTN3381D
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13. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
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13.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 10) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 16 and 17
Table 16.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
 350
< 2.5
235
220
 2.5
220
220
Table 17.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 10.
PTN3381D
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maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 10. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
14. Abbreviations
Table 18.
PTN3381D
Product data sheet
Abbreviations
Acronym
Description
ASCII
American Standard Code for Information Interchange
CDM
Charged-Device Model
CEC
Consumer Electronics Control
CMOS
Complementary Metal-Oxide Semiconductor
DDC
Data Display Channel
DVI
Digital Visual Interface
ESD
ElectroStatic Discharge
ESR
Equivalent Series Resistance
HBM
Human Body Model
HDMI
High-Definition Multimedia Interface
HPD
Hot Plug Detect
I2C-bus
Inter-IC bus
I/O
Input/Output
PCB
Printed-Circuit Board
ROM
Read Only Memory
TMDS
Transition Minimized Differential Signaling
VESA
Video Electronic Standards Association
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15. Revision history
Table 19.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PTN3381D v.2
20120726
Product data sheet
-
PTN3381D v.1
Modifications:
•
Descriptive title of this data sheet modified from “supporting deep color mode” to “supporting
3 Gbit/s operation”
•
Section 1 “General description”:
– first paragraph, first sentence: changed from “HDMI v1.3a” to “HDMI v1.4b”
– first paragraph, first sentence: changed from “up to 2.5 Gbit/s per lane to support 36-bit deep
color mode” to “up to 3 Gbit/s to support 36-bit deep color, 3D and 3 Gbit/s modes”
– first paragraph, second sentence: changed from “Each of these lanes” to “Each of these
channels”
– fourth paragraph, first sentence: changed from “DisplayPort Standard v1.1” to “DisplayPort
Standard v1.2”
– fourth paragraph, first sentence: changed from “HDMI v1.3a” to “HDMI v1.4b”
•
•
Figure 1 “Typical application system diagram” updated (deleted “PCIe” in five places)
Section 2.1 “High-speed TMDS level shifting”:
– first bullet: changed from “HDMI v1.3a” to “HDMI v1.4b”
– second bullet: changed from “up to 2.5 Gbit/s” to “up to 3 Gbit/s”
– second bullet: changed from “250 MHz character clock” to “300 MHz character clock”
– second bullet: changed from “36-bit deep color mode” to “36-bit deep color, 3D and 3 Gbit/s
modes”
•
Section 3 “Applications”: first bullet changed from “36-bit deep color mode” to “36-bit deep color,
3D and 3 Gbit/s modes”
•
Table 2 “Pin description”: Description of pins IN_Dn+, IN_Dn changed from “Low-swing
differential input from display source with PCI Express electrical signalling” to “Low-swing
differential input from source”
•
Section 7 “Functional description”:
– second paragraph, first sentence changed from “up to 2.5 Gbit/s per lane to support 36-bit
deep color mode” to “up to 3 Gbit/s per lane to support 36-bit deep color, 3D and 3 Gbit/s
modes”
– third paragraph, third sentence changed from “HDMI DDC version 1.3a distance specification”
to “HDMI DDC specification”
– Section 7.5 “Active DDC buffer with rise time accelerator”, first paragraph, third sentence
changed from “HDMI DDC version 1.3a distance specification” to “HDMI DDC specification”
PTN3381D v.1
PTN3381D
Product data sheet
•
Section 8.1 “Dongle or cable adaptor detect discovery mechanism”, first paragraph: changed from
“Version 1.1” to “Version 1.1a”
•
Table 10 “Differential input characteristics for IN_Dx signals”: UI Min value changed from “360 ps”
to “333 ps”
•
Section 11.2 “Differential outputs”, first paragraph changed from “HDMI version 1.3” to “HDMI
version 1.4b”
20120323
Product data sheet
-
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Rev. 2 — 26 July 2012
-
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16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PTN3381D
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 26 July 2012
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28 of 30
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Fully integrated HDMI/DVI level shifter supporting 3 Gbit/s operation
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
16.4 Licenses
Purchase of NXP ICs with HDMI technology
Use of an NXP IC with HDMI technology in equipment that complies with
the HDMI standard requires a license from HDMI Licensing LLC, 1060 E.
Arques Avenue Suite 100, Sunnyvale CA 94085, USA, e-mail:
[email protected]
16.5 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PTN3381D
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© NXP B.V. 2012. All rights reserved.
29 of 30
PTN3381D
NXP Semiconductors
Fully integrated HDMI/DVI level shifter supporting 3 Gbit/s operation
18. Contents
1
2
2.1
2.2
2.3
2.4
2.5
2.6
3
4
5
6
6.1
6.2
7
7.1
7.1.1
7.1.2
7.1.3
7.1.4
7.2
7.3
7.4
7.5
7.6
7.6.1
7.6.2
7.7
7.7.1
7.7.2
7.7.3
7.7.4
8
8.1
9
10
10.1
11
11.1
11.2
11.3
11.4
11.5
11.6
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 3
High-speed TMDS level shifting . . . . . . . . . . . . 3
DDC level shifting . . . . . . . . . . . . . . . . . . . . . . . 3
HDMI dongle detect support . . . . . . . . . . . . . . . 3
HPD level shifting . . . . . . . . . . . . . . . . . . . . . . . 3
5 V DC voltage regulator . . . . . . . . . . . . . . . . . 3
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Ordering information . . . . . . . . . . . . . . . . . . . . . 4
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 5
Pinning information . . . . . . . . . . . . . . . . . . . . . . 6
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional description . . . . . . . . . . . . . . . . . . . 9
Enable and disable features . . . . . . . . . . . . . . 10
Hot plug detect . . . . . . . . . . . . . . . . . . . . . . . 10
Output Enable function (OE_N) . . . . . . . . . . . 10
DDC channel enable function (DDC_EN). . . . 10
Enable/disable truth table . . . . . . . . . . . . . . . . 11
Analog current reference . . . . . . . . . . . . . . . . 12
Equalizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Backdrive current protection . . . . . . . . . . . . . . 12
Active DDC buffer with rise time accelerator . 12
I2C-bus based HDMI dongle detection . . . . . . 13
Slave address . . . . . . . . . . . . . . . . . . . . . . . . . 13
Read operation . . . . . . . . . . . . . . . . . . . . . . . . 14
Characteristics of the I2C-bus. . . . . . . . . . . . . 15
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
START and STOP conditions . . . . . . . . . . . . . 15
System configuration . . . . . . . . . . . . . . . . . . . 15
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 16
Application design-in information . . . . . . . . . 17
Dongle or cable adaptor detect discovery
mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 18
Recommended operating conditions. . . . . . . 18
Current consumption . . . . . . . . . . . . . . . . . . . 19
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 19
Differential inputs . . . . . . . . . . . . . . . . . . . . . . 19
Differential outputs . . . . . . . . . . . . . . . . . . . . . 20
HPD_SINK input, HPD_SOURCE output . . . . 20
OE_N, DDC_EN and DDET inputs. . . . . . . . . 21
DDC characteristics . . . . . . . . . . . . . . . . . . . . 21
5 V DC regulator characteristics . . . . . . . . . . . 22
12
13
13.1
13.2
13.3
13.4
14
15
16
16.1
16.2
16.3
16.4
16.5
17
18
Package outline. . . . . . . . . . . . . . . . . . . . . . . .
Soldering of SMD packages . . . . . . . . . . . . . .
Introduction to soldering. . . . . . . . . . . . . . . . .
Wave and reflow soldering. . . . . . . . . . . . . . .
Wave soldering . . . . . . . . . . . . . . . . . . . . . . .
Reflow soldering . . . . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
24
24
24
24
25
26
27
28
28
28
28
29
29
29
30
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 26 July 2012
Document identifier: PTN3381D
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