CBTL06DP212 High-performance DisplayPort Gen2 2 : 1 multiplexer Rev. 2 — 3 November 2011 Product data sheet 1. General description CBTL06DP212 is a high performance multi-channel Generation 2 multiplexer meant for DisplayPort (DP) v1.2, v1.1a or Embedded DisplayPort applications operating at data rate of 1.62 Gbit/s, 2.7 Gbit/s or 5.4 Gbit/s. It is designed using NXP proprietary high-bandwidth pass-gate technology and it can be used for 1 : 2 switching or 2 : 1 multiplexing of four high-speed differential AC-coupled DP channels. Further, it is capable of switching/multiplexing of Hot Plug Detect (HPD) signal as well as Auxiliary (AUX) and Display Data Channel (DDC) signals. In order to support GPUs/CPUs that have dedicated AUX and DDC I/Os, CBTL06DP212 provides an additional level of multiplexing of AUX and DDC signals delivering true flexibility and choice. A typical application of CBTL06DP212 is on motherboards where one of two GPU DisplayPort sources needs to be selected to connect to a DisplayPort sink device or connector. A controller chip selects which path to use by setting a select signal HIGH or LOW. Due to the bidirectional nature of the signal paths, CBTL06DP212 can also be used in the reverse topology, e.g., to connect one display source device to one of two display sink devices or connectors. 2. Features and benefits 1 : 2 switching or 2 : 1 multiplexing of DisplayPort (v1.2 - 5.4 Gbit/s) signals 4 high-speed differential channels with 2 : 1 multiplexing/switching for DisplayPort main link signals 1 channel with 4 : 1 multiplexing/switching for AUX or DDC signals 1 channel with 2 : 1 multiplexing/switching for HPD signal High-bandwidth: 5 GHz at 3 dB Low insertion loss: 0.5 dB at 100 MHz 3 dB at 5 GHz Low crosstalk: 35 dB at 3 GHz Low off-state isolation: 30 dB at 3 GHz Low return loss: 8 dB at 3 GHz Very low intra-pair skew (5 ps typical) Very low inter-pair skew (< 80 ps) Switch/multiplexer position select CMOS input DDC and AUX ports tolerant to being pulled to +5 V via 2.2 k resistor Supports HDMI/DVI incorrect dongle connection Single 3.3 V power supply Operation current of 2 mA typical CBTL06DP212 NXP Semiconductors High-performance DisplayPort Gen2 2 : 1 multiplexer ESD 8 kV HBM, 1 kV CDM ESD 2 kV HBM, 500 V CDM for control pins Available in 5 mm 5 mm, 0.5 mm ball pitch TFBGA48 package 3. Applications Motherboard applications requiring DisplayPort and PCI Express switching/multiplexing Docking stations Notebook computers Chip sets requiring flexible allocation of PCI Express or DisplayPort I/O pins to board connectors 4. Ordering information Table 1. Ordering information Type number CBTL06DP212EE [1] Solder process Package Pb-free (SnAgCu solder compound) Name Description Version TFBGA48 plastic thin fine-pitch ball grid array package; 48 balls; body 5 5 0.8 mm[1] SOT918-1 Total height including solder balls after printed circuit board mounting = 1.15 mm maximum. 5. Marking Table 2. Package marking Line Marking Description A 6D212[1] basic type number B xxxxxxx diffusion lot number C ZPGyyww manufacturing code: Z = diffusion site P = assembly site G = lead-free yy = year code ww = week code [1] CBTL06DP212 Product data sheet Industrial temperature range. All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 November 2011 © NXP B.V. 2011. All rights reserved. 2 of 18 CBTL06DP212 NXP Semiconductors High-performance DisplayPort Gen2 2 : 1 multiplexer 6. Functional diagram VDD CBTL06DP212 IN1_n+ IN1_n− IN2_n+ IN2_n− 4 0 4 1 AUX1+ AUX1− 00 AUX2+ AUX2− 10 DDC_CLK1 DDC_DAT1 01 DDC_CLK2 DDC_DAT2 11 HPD_1 OUT_n+ OUT_n− 4 AUX+ or SCL AUX− or SDA AUX+ AUX− 0 HPDIN HPD_2 1 GPU_SEL DDC_AUX_SEL TST0 GND Fig 1. CBTL06DP212 Product data sheet 002aaf878 Functional diagram All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 November 2011 © NXP B.V. 2011. All rights reserved. 3 of 18 CBTL06DP212 NXP Semiconductors High-performance DisplayPort Gen2 2 : 1 multiplexer 7. Pinning information 7.1 Pinning ball A1 index area CBTL06DP212EE 1 2 3 4 5 6 7 8 9 A B C D E F G H J 002aaf879 Transparent top view Fig 2. Pin configuration for TFBGA48 1 2 A GPU_SEL VDD B OUT_0− OUT_0+ C 3 GND 4 5 6 IN1_0− IN1_1− IN1_2− IN1_0+ IN1_1+ IN1_2+ 7 TST0 8 9 IN1_3+ IN1_3− IN2_0+ IN2_0− DDC_AUX _SEL GND D OUT_1− OUT_1+ IN2_1+ IN2_1− E OUT_2− OUT_2+ IN2_2+ IN2_2− F OUT_3− OUT_3+ IN2_3+ IN2_3− GND GND G H AUX− AUX+ J HPDIN HPD_1 HPD_2 GND DDC_CLK2 AUX2+ VDD DDC_DAT2 AUX2− GND DDC_CLK1 AUX1+ DDC_DAT1 AUX1− 002aaf943 Transparent top view Fig 3. CBTL06DP212 Product data sheet Ball mapping All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 November 2011 © NXP B.V. 2011. All rights reserved. 4 of 18 CBTL06DP212 NXP Semiconductors High-performance DisplayPort Gen2 2 : 1 multiplexer 7.2 Pin description Table 3. Pin description Symbol Ball Type Description GPU_SEL A1 3.3 V CMOS single-ended input Selects between two multiplexer/switch paths. When HIGH, path 2 left-side is connected to its corresponding right-side I/O. When LOW, path 1 left-side is connected to its corresponding right-side I/O. DDC_AUX_SEL C2 3.3 V CMOS single-ended input Selects between DDC and AUX paths. When HIGH, the CLK and DAT I/Os are connected to their respective DDCOUT terminals. When LOW, the AUX+ and AUX I/Os are connected to their respective DDCOUT terminals. TST0 B7 3.3 V CMOS single-ended input Test pin for NXP use only. Should be tied to VDD in normal operation. IN1_0+ B4 differential I/O IN1_0 A4 differential I/O Four high-speed differential pairs for DisplayPort or PCI Express signals, path 1, left-side. IN1_1+ B5 differential I/O IN1_1 A5 differential I/O IN1_2+ B6 differential I/O IN1_2 A6 differential I/O IN1_3+ A8 differential I/O IN1_3 A9 differential I/O IN2_0+ B8 differential I/O IN2_0 B9 differential I/O IN2_1+ D8 differential I/O IN2_1 D9 differential I/O IN2_2+ E8 differential I/O IN2_2 E9 differential I/O IN2_3+ F8 differential I/O IN2_3 F9 differential I/O OUT_0+ B2 differential I/O OUT_0 B1 differential I/O OUT_1+ D2 differential I/O OUT_1 D1 differential I/O OUT_2+ E2 differential I/O OUT_2 E1 differential I/O OUT_3+ F2 differential I/O OUT_3 F1 differential I/O AUX1+ H9 differential I/O AUX1 J9 differential I/O AUX2+ H6 differential I/O AUX2 J6 differential I/O DDC_CLK1 H8 differential I/O DDC_DAT1 J8 differential I/O CBTL06DP212 Product data sheet Four high-speed differential pairs for DisplayPort or PCI Express signals, path 2, left-side. Four high-speed differential pairs for DisplayPort or PCI Express signals, right-side. High-speed differential pair for AUX signals, path 1, left-side. High-speed differential pair for AUX signals, path 2, left-side. Pair of single-ended terminals for DDC clock and data signals, path 1, left-side. All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 November 2011 © NXP B.V. 2011. All rights reserved. 5 of 18 CBTL06DP212 NXP Semiconductors High-performance DisplayPort Gen2 2 : 1 multiplexer Table 3. Pin description …continued Symbol Ball Type Description DDC_CLK2 H5 differential I/O DDC_DAT2 J5 differential I/O Pair of single-ended terminals for DDC clock and data signals, path 2, left-side. AUX+ H2 differential I/O AUX H1 differential I/O High-speed differential pair for AUX or single-ended DDC signals, right-side. HPD_1 J2 single-ended I/O Single ended channel for the HPD signal, path 1, left-side. HPD_2 H3 single-ended I/O Single ended channel for the HPD signal, path 2, left-side. HPDIN J1 single-ended I/O Single ended channel for the HPD signal, right-side. VDD A2, J4 power supply 3.3 V power supply. GND B3, C8, ground G2, G8, H4, H7 Ground. 8. Functional description Refer to Figure 1 “Functional diagram”. The CBTL06DP212 uses a 3.3 V power supply. All main signal paths are implemented using high-bandwidth pass-gate technology and are bidirectional. No clock or reset signal is needed for the multiplexer to function. The switch position for the main channels is selected using the select signal GPU_SEL. Additionally, the signal DDC_AUX_SEL selects between AUX and DDC positions for the DDC / AUX channel. The detailed operation is described in Section 8.1. 8.1 Multiplexer/switch select functions The internal multiplexer switch position is controlled by two logic inputs GPU_SEL and DDC_AUX_SEL as described below. Table 4. GPU_SEL IN1_n IN2_n 0 active; connected to OUT_n high-impedance 1 high-impedance active; connected to OUT_n Table 5. CBTL06DP212 Product data sheet Multiplexer/switch select control for INn and OUTn channels Multiplexer/switch select control for HPD channel GPU_SEL HPD_1 HPD_2 0 active; connected to HPDIN high-impedance 1 high-impedance active; connected to HPDIN All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 November 2011 © NXP B.V. 2011. All rights reserved. 6 of 18 CBTL06DP212 NXP Semiconductors High-performance DisplayPort Gen2 2 : 1 multiplexer Table 6. Multiplexer/switch select control for DDC and AUX channels DDC_AUX_SEL GPU_SEL AUX1 AUX2 DDC_CLK1, DDC_DAT1 DDC_CLK2, DDC_DAT2 0 0 active; connected to AUX high-impedance high-impedance high-impedance 0 1 high-impedance active; connected to AUX high-impedance high-impedance 1 0 high-impedance high-impedance active; connected to AUX high-impedance 1 1 high-impedance high-impedance high-impedance active; connected to AUX 9. Limiting values Table 7. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD supply voltage Tcase case temperature VESD Conditions Min Max Unit 0.3 +5 V 40 +85 C [1] - 8000 V [1] - 2000 V CDM [2] - 1000 V CDM; CMOS inputs [2] 500 V electrostatic discharge HBM voltage HBM; CMOS inputs [1] Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model Component level; Electrostatic Discharge Association, Rome, NY, USA. [2] Charged Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing, Charged Device Model - Component level; Electrostatic Discharge Association, Rome, NY, USA. 10. Recommended operating conditions Table 8. Symbol Parameter VDD supply voltage VI input voltage Tamb CBTL06DP212 Product data sheet Recommended operating conditions Conditions Typ Max Unit 3.0 3.3 3.6 V 0.3 - VDD + 0.3 V HPD inputs [1] 0.3 - VDD + 0.3 V DDC/AUX inputs [2] 0.3 - VDD + 0.3 V other inputs 0.3 - +2.6 V operating in free air 40 - +85 C CMOS inputs ambient temperature Min [1] HPD input is tolerant to 5 V input, provided a 1 k series resistor between the voltage source and the pin is placed in series. See Section 12.1 “Special considerations”. [2] DDC/AUX inputs are tolerant to 5 V input, provided a 2.2 k series resistor between the voltage source and the pin is placed in series. See Section 12.1 “Special considerations”. All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 November 2011 © NXP B.V. 2011. All rights reserved. 7 of 18 CBTL06DP212 NXP Semiconductors High-performance DisplayPort Gen2 2 : 1 multiplexer 11. Characteristics 11.1 General characteristics Table 9. General characteristics Symbol Parameter Conditions Min Typ Max Unit IDD supply current VDD = 3.3 V - 2 3 mA Pcons power consumption VDD = 3.3 V - - 10 mW tstartup start-up time supply voltage valid to channel specified operating characteristics - - 10 s trcfg reconfiguration time GPU_SEL or DDC_AUX_SEL state change to channel specified operating characteristics - - 1 s 11.2 DisplayPort channel characteristics Table 10. DisplayPort channel characteristics Symbol Parameter Min Typ Max Unit VI input voltage 0.3 - +2.6 V VIC common-mode input voltage 0 - 2.0 V VID differential input voltage - - +1.2 V Ron ON-state resistance VDD = 3.3 V; VI = 2 V; II = 20 mA - 6.5 - DDIL differential insertion loss channel is ON; f 100 MHz - 0.5 - dB channel is ON; f = 3.0 GHz - 2.5 - dB channel is OFF; f 3.0 GHz - 30 - dB f = 100 MHz - 25 - dB f = 3.0 GHz - 8 - dB - 65 - dB DDRL differential return loss DDNEXT differential near-end crosstalk Conditions peak-to-peak adjacent channels are ON f = 100 MHz f = 3.0 GHz - 35 - dB B bandwidth 3.0 dB intercept - 5 - GHz tPD propagation delay from left-side port to right-side port or vice versa - 80 - ps tsk(dif) differential skew time intra-pair - 5 - ps tsk skew time inter-pair - - 80 ps CBTL06DP212 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 November 2011 © NXP B.V. 2011. All rights reserved. 8 of 18 CBTL06DP212 NXP Semiconductors High-performance DisplayPort Gen2 2 : 1 multiplexer 11.3 AUX and DDC ports Table 11. AUX and DDC port characteristics Symbol Parameter VI input voltage VO output voltage VIC VID tPD [1] Conditions Min Typ Max Unit 0.3 - VDD + 0.3 V no load - - VDD V common-mode input voltage AUX 0 - 2.0 V differential input voltage AUX - - +1.4 V propagation delay from left-side port to right-side port or vice versa - 80 - ps Max Unit [1] Time from DDC/AUX input changing state to AUX output changing state. Includes DDC/AUX rise/fall time. 11.4 HPDIN input, HPD_x outputs Table 12. HPD input and output characteristics Symbol Parameter VI input voltage VO output voltage propagation delay tPD [1] Conditions Min 0.3 - VDD + 0.3 V no load - - VDD V - 80 - ps from HPDIN to HPD_x or vice versa [1] Typ Time from HPDIN changing state to HPD_x changing state. Includes HPD rise/fall time. 11.5 GPU_SEL and DDC_AUX_SEL inputs Table 13. GPU_SEL and DDC_AUX_SEL input characteristics Symbol Parameter VIH HIGH-level input voltage VIL LOW-level input voltage ILI input leakage current CBTL06DP212 Product data sheet Conditions VDD = 3.6 V; 0.3 V VI 3.9 V All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 November 2011 Min Typ Max Unit 2.0 - - V - - 0.8 V - - 10 A © NXP B.V. 2011. All rights reserved. 9 of 18 CBTL06DP212 NXP Semiconductors High-performance DisplayPort Gen2 2 : 1 multiplexer 12. Application information CBTL06DP212 IN1_n+ IN1_n− IN2_n+ OUT_n+ OUT_n− 2:1 MUX IN2_n− GND 100 kΩ AUX1− GND 100 kΩ 100 kΩ VDD AUX2+ AUX+ AUX− AUX2− +3.3 V 100 kΩ 4:1 MUX 2 kΩ VDD DP CONNECTOR GPU1_DP++ SOURCE AUX1+ DDC_CLK1 DDC_DAT1 DDC_CLK2 DDC_DAT2 HPD_1 HPD_2 HPDIN 2:1 MUX DDC_AUX_SEL GPU2_DP++ SOURCE GPU_SEL Fig 4. 002aaf944 Application diagram 12.1 Special considerations Certain cable or dongle misplug scenarios make it possible for a 5 V input condition to occur on pins AUX+ and AUX, as well as HPDIN. When AUX+ and AUX are connected through a minimum of 2.2 k each, the CBTL06DP212 will sink current but will not be damaged. Similarly, HPDIN may be connected to 5 V via at least a 1 k resistor. (Correct functional operation to specification is not expected in these scenarios.) The latter also prevents the HPDIN input from loading down the system HPD signal when power to the CBTL06DP212 is off. CBTL06DP212 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 November 2011 © NXP B.V. 2011. All rights reserved. 10 of 18 CBTL06DP212 NXP Semiconductors High-performance DisplayPort Gen2 2 : 1 multiplexer 13. Package outline TFBGA48: plastic thin fine-pitch ball grid array package; 48 balls; body 5 x 5 x 0.8 mm B D SOT918-1 A ball A1 index area E A2 A A1 detail X e1 ∅v ∅w b e M M C C A B C y1 C y J H G F E e2 e D C B A ball A1 index area 1 2 3 4 5 6 7 8 9 X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 A2 b D E e e1 e2 v w y y1 mm 1.15 0.25 0.15 0.90 0.75 0.35 0.25 5.1 4.9 5.1 4.9 0.5 4 4 0.15 0.05 0.08 0.1 REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT918-1 --- MO-195 --- Fig 5. EUROPEAN PROJECTION ISSUE DATE 05-09-21 05-10-13 Package outline TFBGA48 (SOT918-1) CBTL06DP212 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 November 2011 © NXP B.V. 2011. All rights reserved. 11 of 18 CBTL06DP212 NXP Semiconductors High-performance DisplayPort Gen2 2 : 1 multiplexer 14. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 14.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 14.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities CBTL06DP212 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 November 2011 © NXP B.V. 2011. All rights reserved. 12 of 18 CBTL06DP212 NXP Semiconductors High-performance DisplayPort Gen2 2 : 1 multiplexer 14.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 6) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 14 and 15 Table 14. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 < 2.5 235 220 2.5 220 220 Table 15. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 6. CBTL06DP212 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 November 2011 © NXP B.V. 2011. All rights reserved. 13 of 18 CBTL06DP212 NXP Semiconductors High-performance DisplayPort Gen2 2 : 1 multiplexer maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 6. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 15. Abbreviations Table 16. CBTL06DP212 Product data sheet Abbreviations Acronym Description AUX Auxiliary channel (in DisplayPort definition) CDM Charged-Device Model CMOS Complementary Metal-Oxide Semiconductor CPU Central Processing Unit DP DisplayPort DVI Digital Video Interface ESD ElectroStatic Discharge GPU Graphics Processor Unit HBM Human Body Model HDMI High-Definition Multimedia Interface I/O Input/Output PCI Peripheral Component Interconnect All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 November 2011 © NXP B.V. 2011. All rights reserved. 14 of 18 CBTL06DP212 NXP Semiconductors High-performance DisplayPort Gen2 2 : 1 multiplexer 16. Revision history Table 17. Revision history Document ID Release date Data sheet status Change notice Supersedes CBTL06DP212 v.2 20111103 Product data sheet - CBTL06DP212 v.1 Modifications: CBTL06DP212 v.1 CBTL06DP212 Product data sheet • Table 2 “Package marking”: Line A marking corrected from “6DP212” to “6D212” 20110221 Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 November 2011 - © NXP B.V. 2011. All rights reserved. 15 of 18 CBTL06DP212 NXP Semiconductors High-performance DisplayPort Gen2 2 : 1 multiplexer 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. 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No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. CBTL06DP212 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 November 2011 © NXP B.V. 2011. All rights reserved. 16 of 18 CBTL06DP212 NXP Semiconductors High-performance DisplayPort Gen2 2 : 1 multiplexer Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 17.4 Licenses Purchase of NXP ICs with HDMI technology Use of an NXP IC with HDMI technology in equipment that complies with the HDMI standard requires a license from HDMI Licensing LLC, 1060 E. Arques Avenue Suite 100, Sunnyvale CA 94085, USA, e-mail: [email protected]. 17.5 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] CBTL06DP212 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 3 November 2011 © NXP B.V. 2011. All rights reserved. 17 of 18 CBTL06DP212 NXP Semiconductors High-performance DisplayPort Gen2 2 : 1 multiplexer 19. Contents 1 2 3 4 5 6 7 7.1 7.2 8 8.1 9 10 11 11.1 11.2 11.3 11.4 11.5 12 12.1 13 14 14.1 14.2 14.3 14.4 15 16 17 17.1 17.2 17.3 17.4 17.5 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Multiplexer/switch select functions . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Recommended operating conditions. . . . . . . . 7 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 8 General characteristics . . . . . . . . . . . . . . . . . . . 8 DisplayPort channel characteristics . . . . . . . . . 8 AUX and DDC ports . . . . . . . . . . . . . . . . . . . . . 9 HPDIN input, HPD_x outputs . . . . . . . . . . . . . . 9 GPU_SEL and DDC_AUX_SEL inputs. . . . . . . 9 Application information. . . . . . . . . . . . . . . . . . 10 Special considerations . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Soldering of SMD packages . . . . . . . . . . . . . . 12 Introduction to soldering . . . . . . . . . . . . . . . . . 12 Wave and reflow soldering . . . . . . . . . . . . . . . 12 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 12 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 3 November 2011 Document identifier: CBTL06DP212