Data Sheet

PCA9519
4-channel level translating I2C-bus/SMBus repeater
Rev. 3 — 10 January 2013
Product data sheet
1. General description
The PCA9519 is a 4-channel level translating I2C-bus/SMBus repeater that enables the
processor low voltage 2-wire serial bus to interface with standard I2C-bus or SMBus I/O.
While retaining all the operating modes and features of the I2C-bus system during the
level shifts, it also permits extension of the I2C-bus by providing bidirectional buffering for
both the data (SDA) and the clock (SCL) lines, thus enabling the I2C-bus or SMBus
maximum capacitance of 400 pF on the higher voltage side. The SDA and SCL pins are
over-voltage tolerant and are high-impedance when the PCA9519 is unpowered.
The port B drivers are compliant with SMBus I/O levels, while port A uses a current
sensing mechanism to detect the input or output LOW signal which prevents bus lock-up.
The port A uses a 1 mA current source for pull-up and a 200  pull-down driver. This
results in a LOW on port A accommodating smaller voltage swings. The output pull-down
on the port A internal buffer LOW is set for approximately 0.2 V, while the input threshold
of the internal buffer is set about 50 mV lower than that of the output voltage LOW. When
the port A I/O is driven LOW internally, the LOW is not recognized as a LOW by the input.
This prevents a lock-up condition from occurring. The output pull-down on the port B
drives a hard LOW and the input level is set at 0.3 of SMBus or I2C-bus voltage level
which enables port B to connect to any other I2C-bus device or buffer.
The PCA9519 drivers are not enabled unless VCC(A) is above 0.8 V and VCC(B) is above
2.5 V. The enable (EN) pin can also be used to turn the drivers on and off under system
control. Caution should be observed to only change the state of the EN pin when the bus
is idle.
2. Features and benefits
 4-channel (4 SCL/SDA pairs), bidirectional buffer isolates capacitance and allows
400 pF on port B of the device
 Voltage level translation from port A (1 V to VCC(B)  1.5 V) to port B (3.0 V to 5.5 V)
 Requires no external pull-up resistors on lower voltage port A
 Active HIGH repeater enable input
 Open-drain inputs/outputs
 Lock-up free operation
 Supports arbitration and clock stretching across the repeater
 Accommodates Standard-mode and Fast-mode I2C-bus devices and multiple masters
 Powered-off high-impedance I2C-bus pins
 Operating supply voltage range of 1.0 V to VCC(B)  1.5 V on port A, 3.0 V to 5.5 V on
port B
 5 V tolerant B-side SCL and SDA and enable pins
 50 ns glitch filter on B-side input
PCA9519
NXP Semiconductors
4-channel level translating I2C-bus/SMBus repeater
 0 Hz to 400 kHz clock frequency
Remark: The maximum system operating frequency may be less than 400 kHz
because of the delays added by the repeater.
 ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
 Packages offered: TSSOP20, HVQFN24
3. Ordering information
Table 1.
Ordering information
Type number
Topside
marking
Package
Name
Description
Version
PCA9519PW
PA9519
TSSOP20
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT360-1
PCA9519BS
9519
HVQFN24
plastic thermal enhanced very thin quad flat package; no leads;
24 terminals; body 4  4  0.85 mm
SOT616-1
3.1 Ordering options
Table 2.
Ordering options
Type number
Orderable
part number
Package
Packing method
Minimum
order quantity
Temperature range
PCA9519PW
PCA9519PW,118
TSSOP20
Reel pack, SMD, 13-inch
2500
Tamb = 40 C to +85 C
PCA9519BS
PCA9519BS,118
HVQFN24
Reel pack, SMD, 13-inch
6000
Tamb = 40 C to +85 C
PCA9519
Product data sheet
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Rev. 3 — 10 January 2013
© NXP B.V. 2013. All rights reserved.
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PCA9519
NXP Semiconductors
4-channel level translating I2C-bus/SMBus repeater
4. Functional diagram
VCC(A)
PCA9519
VCC(B)
VCC(A)
1 mA
A1
B1
VCC(A)
1 mA
A2
B2
VCC(A)
1 mA
A8
B8
EN
002aab643
GND
Fig 1.
Functional diagram of PCA9519
5. Pinning information
19 B1
20 n.c.
21 n.c.
1
20 VCC(B)
B1
2
19 A1
A2
1
18 B2
B2
3
18 A2
A3
2
17 B3
B3
4
17 A3
A4
3
B4
5
16 A4
A5
4
B5
6
15 A5
A6
5
14 B6
B6
7
14 A6
A7
6
13 B7
B7
8
13 A7
B8
9
12 A8
Fig 2.
Pin configuration for TSSOP20
B8 12
9
n.c.
EN 11
8
VCC(B) 10
7
15 B5
002aab641
Transparent top view
Fig 3.
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 10 January 2013
A8
11 VCC(A)
16 B4
PCA9519BS
n.c.
PCA9519PW
002aab640
Product data sheet
22 GND
EN
GND 10
PCA9519
24 A1
terminal 1
index area
23 VCC(A)
5.1 Pinning
Pin configuration for HVQFN24
© NXP B.V. 2013. All rights reserved.
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PCA9519
NXP Semiconductors
4-channel level translating I2C-bus/SMBus repeater
5.2 Pin description
Table 3.
Symbol
Product data sheet
Pin
Description
TSSOP20
HVQFN24
1
11
GND
10
22[1]
ground (0 V)
VCC(A)
11
23
port A power supply
A1
19
24
A1 port (low voltage side)[2]
A2
18
1
A2 port (low voltage side)[2]
A3
17
2
A3 port (low voltage side)[2]
A4
16
3
A4 port (low voltage side)[2]
A5
15
4
A5 port (low voltage side)[2]
A6
14
5
A6 port (low voltage side)[2]
A7
13
6
A7 port (low voltage side)[2]
A8
12
7
A8 port (low voltage side)[2]
VCC(B)
20
10
port B power supply
B8
9
12
B8 port (SMBus/I2C-bus side)[2]
B7
8
13
B7 port (SMBus/I2C-bus side)[2]
B6
7
14
B6 port (SMBus/I2C-bus side)[2]
B5
6
15
B5 port (SMBus/I2C-bus side)[2]
B4
5
16
B4 port (SMBus/I2C-bus side)[2]
B3
4
17
B3 port (SMBus/I2C-bus side)[2]
B2
3
18
B2 port (SMBus/I2C-bus side)[2]
B1
2
19
B1 port (SMBus/I2C-bus side)[2]
n.c.
-
8, 9, 20, 21
EN
PCA9519
Pin description
enable input (active HIGH)
[1]
HVQFN24 package die supply ground is connected to both the GND pin and the exposed center pad. The
GND pin must be connected to supply ground for proper device operation. For enhanced thermal,
electrical, and board-level performance, the exposed pad needs to be soldered to the board using a
corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias
need to be incorporated in the PCB in the thermal pad region.
[2]
Port A and port B can be used for either SCL or SDA.
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Rev. 3 — 10 January 2013
© NXP B.V. 2013. All rights reserved.
4 of 21
PCA9519
NXP Semiconductors
4-channel level translating I2C-bus/SMBus repeater
6. Functional description
Refer to Figure 1 “Functional diagram of PCA9519”.
The PCA9519 enables I2C-bus or SMBus translation down to VCC(A) as low as 1.0 V
without degradation of system performance. The PCA9519 contains 8 bidirectional
open-drain buffers specifically designed to support up-translation/down-translation
between the low voltage and 3.3 V SMBus or 5 V I2C-bus. Port B I/Os are over-voltage
tolerant to 5.5 V even when the device is unpowered.
The PCA9519 includes a power-up circuit that keeps the output drivers turned off until
VCC(B) is above 2.5 V and the VCC(A) is above 0.8 V. VCC(B) and VCC(A) can be applied in
any sequence at power-up. After power-up and with the EN pin HIGH, a LOW level on the
port A (below approximately 0.15 V) turns the corresponding port B driver (either SDA or
SCL) on and drives the port B down to about 0 V. When port A rises above approximately
0.15 V, the port B pull-down driver is turned off and the external pull-up resistor pulls the
pin HIGH. When the port B falls first and goes below 0.3VCC(B), the port A driver is turned
on and the port A pulls down to 0.2 V (typical). The port B pull-down is not enabled unless
the port A voltage goes below VILc. If the port A low voltage goes below VILc, the port B
pull-down driver is enabled until the port A rises above approximately 0.15 V (VILc), then
the port B, if not externally driven LOW, will continue to rise being pulled up by the
external pull-up resistor.
Remark: Ground offset between the PCA9519 ground and the ground of devices on
port A of the PCA9519 must be avoided.
The reason for this cautionary remark is that a CMOS/NMOS open-drain capable of
sinking 3 mA of current at 0.4 V will have an output resistance of 133  or less (R = E / I).
Such a driver will share enough current with the port A output pull-down of the PCA9519
to be seen as a LOW as long as the ground offset is zero. If the ground offset is greater
than 0 V, then the driver resistance must be less. Since VILc can be as low as 90 mV at
cold temperatures and the low end of the current distribution, the maximum ground offset
should not exceed 50 mV.
Bus repeaters that use an output offset are not interoperable with port A of the PCA9519
as their output LOW levels will not be recognized by the PCA9519 as a LOW. If the
PCA9519 is placed in an application where the VIL of the port A of the PCA9519 does not
go below its VILc it will pull the port B LOW initially when the port A input transitions LOW
but port B will return HIGH, so it will not reproduce the port A input on port B. Such
applications should be avoided.
Port B is interoperable with all I2C-bus slaves, masters, and repeaters and includes the
50 ns glitch filter.
6.1 Enable
The EN pin is active HIGH and allows the user to select when the repeater is active. This
can be used to isolate a badly behaved slave on power-up until after the system power-up
reset. It should never change state during an I2C-bus operation because disabling during
a bus operation will hang the bus and enabling part way through a bus cycle could
confuse the I2C-bus parts being enabled.
PCA9519
Product data sheet
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Rev. 3 — 10 January 2013
© NXP B.V. 2013. All rights reserved.
5 of 21
PCA9519
NXP Semiconductors
4-channel level translating I2C-bus/SMBus repeater
The enable pin should only change state when the bus and the repeater port are in an idle
state to prevent system failures.
6.2 I2C-bus systems
As with the standard I2C-bus system, pull-up resistors are required to provide the logic
HIGH levels on the buffered bus (standard open-collector configuration of the I2C-bus).
The size of these pull-up resistors depends on the system. Each of the port A I/Os has an
internal pull-up current source and does not require the external pull-up resistor. The
port B is designed to work with Standard mode and Fast mode I2C-bus devices in addition
to SMBus devices. Standard mode I2C-bus devices only specify 3 mA output drive; this
limits the termination current to 3 mA in a generic I2C-bus system where Standard mode
devices and multiple masters are possible. Under certain conditions higher termination
currents can be used.
7. Application design-in information
A typical application is shown in Figure 4. In this example, the CPU is running on a 1.1 V
I2C-bus while the master is connected to a 3.3 V bus. Both buses run at 400 kHz. Master
devices can be placed on either bus.
1.1 V
3.3 V
10 kΩ
10 kΩ
VCC(A)
VCC(B)
SDA
A1
B1
SDA
SCL
A2
B2
SCL
PCA9519
1.1 V
CPU
10 kΩ
A8
MASTER
400 kHz
B8
EN
bus A
Fig 4.
bus B
002aab642
Typical application
When port B of the PCA9519 is pulled LOW by a driver on the I2C-bus, a CMOS
hysteresis detects the falling edge when it goes below 0.3VCC(B) and causes the internal
driver on port A to turn on, causing port A to pull down to about 0.2 V. When port A of the
PCA9519 falls, first a comparator detects the falling edge and causes the internal driver
on port B to turn on and pull the port B pin down to ground. In order to illustrate what
would be seen in a typical application, refer to Figure 5 and Figure 6. If the bus master in
Figure 4 were to write to the slave through the PCA9519, waveforms shown in Figure 5
would be observed on the B bus. This looks like a normal I2C-bus transmission.
On the port A bus of the PCA9519, the clock and data lines would have a positive offset
from ground equal to the VOL of the PCA9519. After the 8th clock pulse, the data line will
be pulled to the VOL of the master device, which is very close to ground in this example. At
the end of the acknowledge, the level rises only to the LOW level set by the driver in the
PCA9519 for a short delay while the port B bus rises above 0.5VCC(B), then it continues
PCA9519
Product data sheet
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Rev. 3 — 10 January 2013
© NXP B.V. 2013. All rights reserved.
6 of 21
PCA9519
NXP Semiconductors
4-channel level translating I2C-bus/SMBus repeater
HIGH. It is important to note that any arbitration or clock stretching events require that the
LOW level on the port A bus at the input of the PCA9519 (VIL) is below VILc to be
recognized by the PCA9519 and then transmitted to the port B bus.
9th clock pulse
acknowledge
SCL
SDA
002aab644
Fig 5.
Bus B SMBus/I2C-bus waveform
9th clock pulse
acknowledge
SCL
SDA
VOL of PCA9519
002aab645
VOL of master
Fig 6.
Bus A lower voltage waveform
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VCC(B)
Conditions
Min
Max
Unit
supply voltage port B
0.5
+6
V
VCC(A)
supply voltage port A
0.5
+6
V
VI/O
voltage on an input/output pin
port A
0.5
+6
V
port B; enable pin (EN)
0.5
+6
V
II/O
input/output current
-
20
mA
II
input current
-
20
mA
Ptot
total power dissipation
-
100
mW
Tstg
storage temperature
65
+150
C
Tamb
ambient temperature
Tj
junction temperature
Tsp
solder point temperature
PCA9519
Product data sheet
operating in free air
10 s max.
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 10 January 2013
40
+85
C
-
125
C
-
300
C
© NXP B.V. 2013. All rights reserved.
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PCA9519
NXP Semiconductors
4-channel level translating I2C-bus/SMBus repeater
9. Static characteristics
Table 5.
Static characteristics
GND = 0 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
Supplies
VCC(B)
supply voltage port B
3.0
-
5.5
V
VCC(A)
supply voltage port A
1.0
-
VCC(B)  1.5
V
ICC(A)
supply current port A
all port A static HIGH
1
2.1
3.6
mA
all port A static LOW
5
11.6
20
mA
all port B static HIGH
2
3.3
4.5
mA
ICC(B)
supply current port B
Input and output of port A (A1 to A8)
HIGH-level input voltage
VIH
port A
LOW-level input voltage
VIL
port A
VILc
contention LOW-level input voltage
VIK
input clamping voltage
IL = 18 mA
ILI
input leakage current
VI = VCC(A)
IIL
0.7VCC(A)
-
VCC(A)
V
[2]
0.5
-
+0.3
V
[2]
0.5
+0.15
-
V
1.5
-
0.5
V
-
-
1
A
LOW-level input current
[3]
1.5
1
0.45
mA
-
0.2
0.35
V
-
50
-
mV
-
-
10
A
-
6
7
pF
VOL
LOW-level output voltage
[4]
VOLVILc
difference between LOW-level output
port A
and LOW-level input voltage contention
[5]
ILOH
HIGH-level output leakage current
Cio
input/output capacitance
VO = 1.1 V
Input and output of port B (B1 to B8)
VIH
HIGH-level input voltage
0.7VCC(B)
-
VCC(B)
V
VIL
LOW-level input voltage
0.5
-
+0.3VCC(B)
V
VIK
input clamping voltage
IL = 18 mA
1.5
-
0.5
V
ILI
input leakage current
VI = 3.6 V
1.0
-
+1.0
A
IIL
LOW-level input current
VI = 0.2 V
-
-
10
A
VOL
LOW-level output voltage
IOL = 6 mA
-
0.1
0.2
V
ILOH
HIGH-level output leakage current
VO = 3.6 V
-
-
10
A
Cio
input/output capacitance
-
6
7
pF
VIL
LOW-level input voltage
0.5
-
+0.1VCC(A)
V
VIH
HIGH-level input voltage
IIL(EN)
LOW-level input current on pin EN
ILI
input leakage current
Ci
input capacitance
Enable
VI = 0.2 V, EN;
VCC = 3.6 V
VI = 3.0 V or 0 V
0.9VCC(A)
-
VCC(B)
V
1
-
+1
A
1
-
+1
A
-
2
3
pF
[1]
Typical values with VCC(A) = 1.1 V, VCC(B) = 5.0 V.
[2]
VIL specification is for the falling edge seen by the port A input. VILc is for the static LOW levels seen by the port A input resulting in
port B output staying LOW.
PCA9519
Product data sheet
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Rev. 3 — 10 January 2013
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PCA9519
NXP Semiconductors
4-channel level translating I2C-bus/SMBus repeater
[3]
The port A current source has a typical value of about 1 mA, but varies with both VCC(A) and VCC(B). Below VCC(A) of about 0.7 V the
port A current source current drops to 0 mA. The current source current dropping across the internal pull-down driver resistance of
about 200  defines the VOL.
[4]
As long as the chip ground is common with the input ground reference the driver resistance may be as large as 120 . However, ground
offset will rapidly decrease the maximum allowed driver resistance.
[5]
Guaranteed by design.
10. Dynamic characteristics
Table 6.
Dynamic characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCC(A) = 1.1 V; VCC(B) = 3.3 V
tPLH
LOW to HIGH propagation delay
port B to port A
[1]
69
109
216
ns
tPHL
HIGH to LOW propagation delay
port B to port A
[1]
63
86
140
ns
tTLH
LOW to HIGH output transition time
port A
[1]
14
22
96
ns
port A
[1]
5
8.1
16
ns
HIGH to LOW output transition time
tTHL
tPLH
LOW to HIGH propagation delay
port A to port B
[1]
69
91
139
ns
tPLH2
LOW to HIGH propagation delay 2
port A to port B; measured from
the 50 % of initial LOW on port A to
1.5 V rising on port B
[1]
91
153
226
ns
tPHL
HIGH to LOW propagation delay
port A to port B
[1]
73
122
183
ns
tTLH
LOW to HIGH output transition time
port B
[1][2]
-
61
-
ns
tTHL
HIGH to LOW output transition time
port B
[1]
15
24
40
ns
tsu
set-up time
EN HIGH before START condition
100
-
-
ns
th
hold time
EN HIGH after STOP condition
100
-
-
ns
VCC(A) = 1.9 V; VCC(B) = 5.0 V
LOW to HIGH propagation delay
tPLH
HIGH to LOW propagation delay
tPHL
port B to port A
[1]
69
105
216
ns
port B to port A
[1]
63
86
140
ns
tTLH
LOW to HIGH output transition time
port A
[1]
14
27
96
ns
tTHL
HIGH to LOW output transition time
port A
[1]
5
8
35
ns
tPLH
LOW to HIGH propagation delay
port A to port B
[1]
69
89
139
ns
91
131
226
ns
73
99
183
ns
-
65
-
ns
tPLH2
LOW to HIGH propagation delay 2
port A to port B; measured from
the 50 % of initial LOW on port A to
1.5 V rising on port B
[1]
tPHL
HIGH to LOW propagation delay
port A to port B
[1]
LOW to HIGH output transition time
tTLH
port B
[1][2]
[1]
tTHL
HIGH to LOW output transition time
port B
15
31
40
ns
tsu
set-up time
EN HIGH before START condition
100
-
-
ns
th
hold time
EN HIGH after STOP condition
100
-
-
ns
[1]
Load capacitance = 50 pF; load resistance on port B = 1.35 k.
[2]
Value is determined by RC time constant of bus line.
PCA9519
Product data sheet
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Rev. 3 — 10 January 2013
© NXP B.V. 2013. All rights reserved.
9 of 21
PCA9519
NXP Semiconductors
4-channel level translating I2C-bus/SMBus repeater
10.1 AC waveforms
VCC(B)
input
VCC(A)
0.5VCC(B)
0.5VCC(B)
input
0.5VCC(A)
0.5VCC(A)
0.1 V
tPHL
output
70 %
tPHL
tPLH
0.5VCC(A) 0.5VCC(A)
30 %
30 %
VCC(A)
70 %
tTHL
output
70 %
VOL
tTLH
tPLH
0.5VCC(B) 0.5VCC(B)
30 %
30 %
tTHL
Propagation delay and transition times;
port B to port A
VCC(B)
tTLH
002aab646
Fig 7.
70 %
002aab647
Fig 8.
Propagation delay and transition times;
port A to port B
input
port A
50 % of initial value
0.5VCC(B)
output
port B
tPLH2
Fig 9.
002aab648
Propagation delay from port A’s external driver switching off to the port B LOW-to-HIGH transition;
port A to port B
11. Test information
VCC(B)
VCC(B)
VCC(A)
PULSE
GENERATOR
VI
RL
VO
DUT
CL
RT
002aab649
RL = load resistor; 1.35 k on port B
CL = load capacitance includes jig and probe capacitance; 50 pF
RT = termination resistance should be equal to Zo of pulse generators
Fig 10. Test circuit for open-drain outputs
PCA9519
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 10 January 2013
© NXP B.V. 2013. All rights reserved.
10 of 21
PCA9519
NXP Semiconductors
4-channel level translating I2C-bus/SMBus repeater
12. Package outline
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
E
D
A
X
c
HE
y
v M A
Z
11
20
Q
A2
(A 3)
A1
pin 1 index
A
θ
Lp
L
1
10
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.5
0.2
8o
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT360-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-153
Fig 11. Package outline SOT360-1 (TSSOP20)
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HVQFN24: plastic thermal enhanced very thin quad flat package; no leads;
24 terminals; body 4 x 4 x 0.85 mm
A
B
D
SOT616-1
terminal 1
index area
A
A1
E
c
detail X
e1
C
1/2
e
e
12
y
y1 C
v M C A B
w M C
b
7
L
13
6
e
e2
Eh
1/2
1
e
18
terminal 1
index area
24
19
X
Dh
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
c
D (1)
Dh
E (1)
Eh
e
e1
e2
L
v
w
y
y1
mm
1
0.05
0.00
0.30
0.18
0.2
4.1
3.9
2.25
1.95
4.1
3.9
2.25
1.95
0.5
2.5
2.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT616-1
---
MO-220
---
EUROPEAN
PROJECTION
ISSUE DATE
01-08-08
02-10-22
Fig 12. Package outline SOT616-1 (HVQFN24)
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13. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
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13.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 13) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 7 and 8
Table 7.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
 350
< 2.5
235
220
 2.5
220
220
Table 8.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 13.
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temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 13. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
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14. Soldering: PCB footprints
Footprint information for reflow soldering of TSSOP20 package
SOT360-1
Hx
Gx
P2
(0.125)
Hy
Gy
(0.125)
By
Ay
C
D2 (4x)
D1
P1
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1
P2
Ay
By
C
D1
D2
Gx
Gy
Hx
Hy
0.650
0.750
7.200
4.500
1.350
0.400
0.600
6.900
5.300
7.300
7.450
sot360-1_fr
Fig 14. PCB footprint for SOT360-1 (TSSOP20); reflow soldering
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Product data sheet
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Footprint information for reflow soldering of HVQFN24 package
SOT616-1
Hx
Gx
D
P
0.025
0.025
C
(0.105)
SPx
nSPx
Hy
SPy tot
SPy
Gy
SLy
nSPy
By
Ay
SPx tot
SLx
Bx
Ax
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
solder paste deposit
solder land plus solder paste
occupied area
nSPx
nSPy
2
2
Dimensions in mm
P
Ax
Ay
Bx
By
C
D
SLx
SLy
SPx tot
SPy tot
SPx
SPy
Gx
Gy
Hx
Hy
0.500
5.000
5.000
3.200
3.200
0.900
0.240
2.100
2.100
1.200
1.200
0.450
0.450
4.300
4.300
5.250
5.250
Issue date
07-05-07
09-06-15
sot616-1_fr
Fig 15. PCB footprint for SOT616-1 (HVQFN24); reflow soldering
PCA9519
Product data sheet
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15. Abbreviations
Table 9.
Abbreviations
Acronym
Description
CDM
Charged-Device Model
CMOS
Complementary Metal-Oxide Semiconductor
CPU
Central Processing Unit
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
I/O
Input/Output
I2C-bus
Inter-Integrated Circuit Bus
NMOS
Negative-channel Metal-Oxide Semiconductor
PCB
Printed-Circuit Board
RC
Resistor Capacitor network
SMBus
System Management Bus
16. Revision history
Table 10.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCA9519 v.3
20130110
Product data sheet
-
PCA9519 v.2
Modifications:
•
•
•
•
Section 2 “Features and benefits”, 14th bullet item: deleted phrase “200 V MM per JESD22-A115”
Table 1 “Ordering information”: Type number PCA9519PW’s topside mark is corrected from
“PCA9519” to “PA9519” to reflect manufacturing.
Added Section 3.1 “Ordering options”
Added Section 14 “Soldering: PCB footprints”
PCA9519 v.2
20070813
Product data sheet
-
PCA9519 v.1
PCA9519 v.1
20060622
Objective data sheet
-
-
PCA9519
Product data sheet
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17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
17.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PCA9519
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 10 January 2013
© NXP B.V. 2013. All rights reserved.
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Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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19. Contents
1
2
3
3.1
4
5
5.1
5.2
6
6.1
6.2
7
8
9
10
10.1
11
12
13
13.1
13.2
13.3
13.4
14
15
16
17
17.1
17.2
17.3
17.4
18
19
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
I2C-bus systems . . . . . . . . . . . . . . . . . . . . . . . . 6
Application design-in information . . . . . . . . . . 6
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7
Static characteristics. . . . . . . . . . . . . . . . . . . . . 8
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . 10
Test information . . . . . . . . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
Soldering of SMD packages . . . . . . . . . . . . . . 13
Introduction to soldering . . . . . . . . . . . . . . . . . 13
Wave and reflow soldering . . . . . . . . . . . . . . . 13
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 13
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 14
Soldering: PCB footprints. . . . . . . . . . . . . . . . 16
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18
Legal information. . . . . . . . . . . . . . . . . . . . . . . 19
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Contact information. . . . . . . . . . . . . . . . . . . . . 20
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 10 January 2013
Document identifier: PCA9519