PCA9522 Fast dual bidirectional bus buffer with hot insertion logic Rev. 1 — 28 September 2011 Product data sheet 1. General description The PCA9522 is a monolithic bipolar integrated circuit for bus buffering in applications including I2C-bus, SMBus, etc. It includes hot insertion logic for detecting stop and idle conditions, making it ideal for live insertion into backplanes. The buffer extends the bus load limit by buffering both the SCL and SDA lines. The PCA9522 is a drop-in replacement for the IES5502, with only the maximum bus voltage reduced from 15 V to 10 V. Hot insertion logic allows the IC to be plugged into live backplanes without causing data corruption on the bus. The open-collector ready signal (RDY) indicates when the connection has been made. Precharging of the backplane ports minimizes disruptions to the bus during hot insertion. The enable function allows sections of the bus to be isolated. Individual parts of the system can be brought on-line successively. Bus level translation between a very wide range of bus voltages, from 1.8 V to 10 V, is supported. These features provide enormous flexibility in interfacing systems of different technologies, operating speeds and loads. The unique operation of the PCA9522 provides one of the fastest response times of such bidirectional buffers. It does this without the need for rise-time accelerators which, combined with low noise margins, may cause glitches outside of the I2C-bus specification. 2. Features and benefits Dual, bidirectional unity gain isolating buffer Hot insertion logic prevents data and clock bus corruption for live backplane applications Pre-charge minimizes data corruption on live insertion Supports I2C-bus (Standard-mode and Fast-mode), SMBus (standard and high power modes) and PMBus Open-collector ready output (RDY) Fast switching times allow operation in excess of 1 MHz Enable (EN) allows bus segments to be disconnected Low current standby mode when not enabled High-impedance ports when IC unpowered 6 mA (static) pull-down capability Low noise susceptibility Supports the connection of several buffers in series Level shift bus voltages from 1.8 V to 10 V PCA9522 NXP Semiconductors Fast dual bidirectional bus buffer with hot insertion logic 3. Applications Backplane management/interconnect Telecommunications systems including ATCA Desktop and portable computers including RAID 4. Ordering information Table 1. Ordering information Type number Topside mark Package Name Description Version PCA9522D PCA9522 SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 PCA9522DP 9522 TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1 5. Block diagram 2.7 V to 5.5 V 1.8 V to 10 V R1 1.8 V to 10 V VCC R2 undervoltage 8 R5 1.8 V to 10 V R3 R4 PCA9522 PRECHARGE enable (up to 10 V) SCL EN 1 SCLB 3 backplane side SDA 5 RDY HOT INSERT LOGIC ready 2 SCLC SCL card side Vref SDAB 6 7 SDAC SDA 4 GND 002aaf318 Fig 1. PCA9522 Product data sheet Block diagram of PCA9522 All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 September 2011 © NXP B.V. 2011. All rights reserved. 2 of 20 PCA9522 NXP Semiconductors Fast dual bidirectional bus buffer with hot insertion logic 6. Pinning information 6.1 Pinning EN 1 8 VCC SCLC 2 7 SDAC SCLB 3 6 SDAB GND 4 5 RDY PCA9522D EN 1 8 VCC SCLC 2 7 SDAC 6 SDAB 5 RDY SCLB 3 GND 4 002aaf320 002aaf319 Fig 2. PCA9522DP Pin configuration for SO8 Fig 3. Pin configuration for TSSOP8 6.2 Pin description Table 2. PCA9522 Product data sheet Pin description Symbol Pin Description EN 1 enable SCLC 2 SCL buffer, card side[1] SCLB 3 SCL buffer, backplane side[2] GND 4 supply ground RDY 5 ready SDAB 6 SDA buffer, backplane side[2] SDAC 7 SDA buffer, card side[1] VCC 8 positive supply [1] Card side is equivalent to SCL_OUT / SDA_OUT. [2] Backplane side is equivalent to SCL_IN / SDA_IN. All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 September 2011 © NXP B.V. 2011. All rights reserved. 3 of 20 PCA9522 NXP Semiconductors Fast dual bidirectional bus buffer with hot insertion logic 7. Functional description Refer to Figure 1 “Block diagram of PCA9522”. 7.1 VCC, GND — supply pins The PCA9522 can be driven from voltage supplies ranging from 2.7 V to 5.5 V. The threshold level below which the output will begin to match the input is 33 % of VCC. Hence, the operating voltage should be chosen with the required bus voltage, switching threshold, and noise margins in mind. 7.2 SCLB, SCLC, SDAB, SDAC — buffer inputs/outputs The two open-collector buffers (SCL and SDA) are identical and symmetrical. The buffers can be driven from either direction, with the same buffering response. However, the hot insertion logic is determined from the ‘backplane’ (SxxB) sides of the buffers. When the one side (e.g., SxxB) of the buffer is being driven LOW (<0.3VCC) by another device on the bus, the other side (e.g., SxxC) will be driven LOW by the IC to provide the buffered output. The ‘control’ or ‘input’ side is determined by the lowest externally driven signal. Therefore if the ‘input’ is externally pulled to VSxxB = 250 mV, and the ‘output’ is externally pulled to VSxxC = 500 mV, the buffer will pull the ‘output’ down further such that it becomes VSxxC = VSxxB + Voffset. Should the ‘output’ subsequently become lower than the ‘input’ by means of an external device pulling it LOW (VSxxC < VSxxB), control of the buffering operation will switch sides. The voltage at the ‘input’ will then become VSxxB = VSxxC + Voffset. Many bus buffers are prone to causing glitches during control transition, but the PCA9522 shows negligible glitching even under the worst operating conditions. 7.3 Enable (EN) — activate buffer operations The enable input (EN) is used to disable the buffer, for the purpose of isolating sections of the bus. The IC should only be disabled when the bus is idle, to prevent truncation of commands which may confuse other devices on the bus. Upon receiving a valid enable (EN) signal, the IC will wait to detect either a bus STOP condition, or an IDLE condition as described in the I2C-bus [Ref. 1] and SMBus [Ref. 2] specifications. This ensures that truncated transmissions are not communicated along the newly enabled bus segment. Enable may be used to progressively activate sections of the bus during system start-up. Bus sections slow to respond on power-up can be kept isolated from the main system to avoid interference and collisions. The EN pin may be pulled up higher than the VCC of the buffer, further enhancing the capability of the PCA9522 in a level shifting role. For example, a microprocessor could drive EN, SCLB and SDAB at 5 V, while the buffer VCC, SCLC and SDAC ports are at 3.3 V. Similarly, the threshold level of the EN pin allows a 1.8 V device to enable an PCA9522 with a VCC of 3.3 V. PCA9522 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 September 2011 © NXP B.V. 2011. All rights reserved. 4 of 20 PCA9522 NXP Semiconductors Fast dual bidirectional bus buffer with hot insertion logic 7.4 Ready (RDY) — buffer connected indicator The ready output (RDY) indicates that the buffer has met its enable conditions, and that communication will now occur. This is an open-collector transistor which is switched off when ready, allowing the voltage at the pin to be pulled HIGH by a pull-up resistor. 7.5 Start-up During power-up or live insertion into backplanes, the PCA9522 will start-up in an UnderVoltage LockOut (UVLO) state where any activity on the input/output ports will be ignored. This is to ensure that the PCA9522 does not try to operate when there is not enough voltage on the supply. During this time, the precharge circuit will charge all SCLB/SDAB backplane ports to typically 0.92 V. This will minimize any voltage difference between the ports and hence minimizes disruptions to the bus during hot insertion into backplanes. When the supply increases above the UVLO state the PCA9522 will then monitor the bus for either stop bit or bus idle condition. When a stop bit condition is detected and SCLC/SDAC are both idle or when all SCL/SDA ports idle for a time period of typically 95 s, then the PCA9522 will activate the input-output connection circuitry. The precharge circuitry is switched off. The voltage at the RDY pin is pulled HIGH by an external pull-up resistor to indicate the input/output connection has been made. 8. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VCC supply voltage Vn voltage on any other pin VI(EN) input voltage on pin EN IIO input/output current Ptot Min Max Unit [1] 0.3 +7 V [1] 0.3 +12 V [1] 0.3 +12 V - 20 mA total power dissipation - 300 mW Tstg storage temperature 55 +125 C Tamb ambient temperature 40 +85 C [1] PCA9522 Product data sheet Conditions SCLB, SCLC, SDAB, SDAC DC; any pin operating Voltages are specified with respect to pin 4 (GND). All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 September 2011 © NXP B.V. 2011. All rights reserved. 5 of 20 PCA9522 NXP Semiconductors Fast dual bidirectional bus buffer with hot insertion logic 9. Characteristics Table 4. Characteristics Tamb = 40 C to +85 C; voltages are specified with respect to ground (GND). Symbol Parameter Conditions Min Typ Max Unit VCC supply voltage operating 2.7 - 5.5 V ICC supply current operating; VCC = VI(EN) = 5.5 V - 9 - mA standby; VCC = 5.5 V; VI(EN) = 0 V - 520 - A Power supply Start-up circuitry Vth(UVLO) undervoltage lockout threshold voltage VCC = VI(EN) = 5.5 V - 2.2 - V Vpch precharge voltage VSxxB floating; VCC = 3.3 V; Vi(EN) > 1.2 V - 0.92 - V Ipch precharge current VSxxB floating; VCC = 3.3 V; Vi(EN) > 1.2 V - 11 - A Vth threshold voltage logic input - 0.5VCC - V logic output - 0.5VCC - V Buffer ports (SCLB, SCLC, SDAB, SDAC) Vbus bus voltage - - 10 V Vth(IL) LOW-level input threshold voltage - - 0.3VCC V Vth(IH) HIGH-level input threshold voltage 0.41VCC - - V IIL LOW-level input current drive current; Vbus < VCC - 10 20 A IO(sink) output sink current LOW-level; Vbus(out) = 0.4 V 6 - - mA Voffset offset voltage input/output; VCC = 3.3 V IOL = 4 mA; Vbus(in) = 50 mV - 165 200 mV IOL = 500 A; Vbus(in) = 50 mV - 55 100 mV IOL = 1.2 mA; Vbus(in) = 200 mV - 60 100 mV leakage current Vbus = VCC - - 5 A Ven enable voltage active 1.2 - - V Vdis disable voltage standby - - 0.7 V II input current Ven > 1.2 V 1 - 5 A IL Enable (EN) Ready (RDY) VOL(RDY) LOW-level output voltage Ipu = 3 mA on pin RDY - - 400 mV IL leakage current VOL(RDY) = VCC - - 5 A Timing characteristics[1] td delay time VCC = 5 V; Vbus = 5 V; Rpu(bus) = 1 k; CL(ext) = 120 pF; Figure 4 - 30 - ns tf fall time VCC = 5 V; Vbus = 5 V; Rpu(bus) = 1 k; CL(ext) = 120 pF; Figure 4 - 15 - ns foper operating frequency 0 400 - kHz PCA9522 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 September 2011 © NXP B.V. 2011. All rights reserved. 6 of 20 PCA9522 NXP Semiconductors Fast dual bidirectional bus buffer with hot insertion logic Table 4. Characteristics …continued Tamb = 40 C to +85 C; voltages are specified with respect to ground (GND). Symbol Parameter Conditions Min Typ Max Unit tidle idle time Vbus = VI(EN) = VCC = 3.3 V 50 95 150 s Vbus = VI(EN) = VCC = 5.5 V 50 75 120 s td(ENH-RDYoff) delay time from EN HIGH to RDY off - 95 - s td(ENL-RDYon) delay time from EN LOW to RDY on - 1.1 - s td(RDYH-I2Con) delay time from RDY HIGH to I2C on - 1 - s td(RDYL-I2Coff) delay time from RDY LOW to I2C off - 0.5 - s [1] Guaranteed by design (not subject to test), except for tidle at VCC = 3.3 V. 002aaf325 125 Voffset (mV) 100 Vbus 70 % VSxxB VCC = Vpu = 5 V VSxxB 75 VSxxC 33 % VCC 30 % VSxxB 50 SxxB td tf 25 SxxC 0 0 time 2 4 6 002aaf324 8 10 RPU (kΩ) Tamb = 25 C; Vbus(in) = 200 mV. Fig 4. Timing parameters Fig 5. Offset voltage, VO VI 002aaf326 9.6 ICC (mA) 8.8 VCC = 5.5 V 3.3 V 8.0 7.2 −50 Fig 6. 0 50 100 150 T (°C) Supply current versus temperature PCA9522 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 September 2011 © NXP B.V. 2011. All rights reserved. 7 of 20 PCA9522 NXP Semiconductors Fast dual bidirectional bus buffer with hot insertion logic 10. Application information 10.1 Design considerations Figure 7 shows a typical application for the PCA9522. The IC can level shift between various bus voltages, without the need for additional external components. Higher bus voltages and currents outside the range of the standard I2C-bus specification can be catered for, providing a longer range capability and higher noise immunity. The enable pin (EN) can be used to interface buses of different operating frequencies. When enabled, the bus frequency is limited to the maximum 100 kHz of the slave device. When disabled, the slave is isolated, and the remaining bus can be run at 400 kHz. The timing performance and current sinking capability will allow it to run well in excess of the 400 kHz maximum limit of the Fast-mode I2C-bus. 1.8 V 3.3 V R1 600 Ω VCC R2 600 Ω C1 0.01 μF R7 18 kΩ SCLC SDA SDAC R3 3.9 kΩ R4 3.9 kΩ SDAB R5 1.1 kΩ R6 1.1 kΩ SCLB VCC SCLC SCL SDAB SDAC SDA PCA9522 RDY U2 3.3 V C2 0.01 μF PCA9522 EN U1 5V 10 V VCC SCLB SCL BUS MASTER 400 kHz 10 V SLAVE 100 kHz RDY backplane or cable run VCC EN U3 U4 002aaf321 Fig 7. PCA9522 typical buffer application Figure 8 shows the PCA9522 used in a backplane application. Peripheral cards and backplanes operating at a range of voltages can be interfaced together using a minimum of components. In this example, cards are running at 1.8 V and 3.3 V, while the backplane is at 5 V. Cards operating buses between 1.8 V and 10 V can be catered for in the same system. Each card can be safely isolated from the system by disabling the PCA9522 at the interface to the backplane. The hot insertion logic on the PCA9522 protects against corrupted or truncated data transmissions on start-up of buffer operations. PCA9522 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 September 2011 © NXP B.V. 2011. All rights reserved. 8 of 20 PCA9522 NXP Semiconductors Fast dual bidirectional bus buffer with hot insertion logic backplane PERIPHERAL CARD 1 (3.3 V) R3 1.1 kΩ R4 1.1 kΩ CARD SUPPLY R7 6.8 kΩ C2 0.01 μF (3.3 V) SCLC VCC SCLB SDAC SDAB R1 1.5 kΩ VCC (5 V) R2 1.5 kΩ SCL SDA PCA9522 RDY EN GND U1 GND PERIPHERAL CARD n (1.8 V) R5 600 Ω R6 600 Ω CARD SUPPLY R8 3.6 kΩ C2 0.01 μF (3.3 V) SCLC VCC SCLB SDAC SDAB PCA9522 RDY EN GND U2 002aaf322 Fig 8. PCA9522 backplane application An ideal backplane application for the PCA9522 is the Advanced Telecom Computing Architecture (AdvancedTCA) as shown in Figure 9. The PCA9522 is well-suited to placement on ‘Field Replaceable Units’ (FRUs) used in either a conventional fully-bused arrangement (not shown) or in the low cost, high noise margin radial architecture example as shown in Figure 10. It is fully interoperable with existing systems and components. If required, Figure 10 shows a simple low-cost circuit for use at the Shelf Manager for accelerating the rise in bused systems. In each of these examples, the buffers are intended to extend total system capacitance above 400 pF, so anticipate high capacitance on each side. When loading on one side is small, adding 47 pF is suggested to avoid any waveform ripple, should it occur. PCA9522 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 September 2011 © NXP B.V. 2011. All rights reserved. 9 of 20 PCA9522 NXP Semiconductors Fast dual bidirectional bus buffer with hot insertion logic fully bused compliant plug-in (hot-insert) ShMC module (e.g., AMC) BACKPLANE enables R R VI R Rd (1) R RRA PCA9522 FET switches PCA9521 PCA9522 μP VOL = VI + 0.08 V Rd μP I2C-bus to ShMC #2 total 12 FET switches (4 / pkg.), giving 24 bus outputs R alternate implementations FRU with switching levels compliant with the I2C-bus standard PCA9521 12 × PCA9521 isolating bus buffers Rd μP required VIL = 0.3VCC (max.) = 0.99 V Vmax = 0.5 V (PICMG3.0) example of existing FRUs built to PICMG3.0 R2.0 PCA9521 enables R Rd R BUFFER WITH RTA FET switches PCA9521 ShMC1 to ShMC #2 required VIL = 0.6 V (typ.) IPMB (× 24) ShMC2 μP etc. 002aaf289 The system shown here uses FET switches, however a valid alternative is to simply use 24 PCA9521s without FET switches. Long track runs on the ShMC board and backplane can sometimes result in high frequency tuned circuits on either side of the PCA9521. If your layout is prone to forming such tuned circuits, it is perfectly acceptable to use a ‘traditional’ damping resistor (Rd) across the PCA9521. (1) RRA = Rise Rate Accelerator. Fig 9. PCA9522 used in an AdvancedTCA application in conjunction with the PCA9521 3.3 V 1 kΩ BC857BS or equivalent 47 kΩ 22 pF 1 kΩ BC857BS or equivalent 47 kΩ 1.5 kΩ 22 pF 1.5 kΩ 10 kΩ 10 kΩ SCL SDA DTC124E (or equivalent) 002aaf323 Fig 10. Discrete rise rate accelerator circuit example PCA9522 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 September 2011 © NXP B.V. 2011. All rights reserved. 10 of 20 PCA9522 NXP Semiconductors Fast dual bidirectional bus buffer with hot insertion logic 10.2 Input to output offset voltage calculation The offset voltage between the side acting as the output (Sxxx(out)) and the side acting as the input (Sxxx(in)) of the PCA9522 can be calculated using the relationship given in Equation 1: V BUS V offset = V i + 50 mV + ------------ 11 R (1) This calculation is valid for VSxxx(in) 200 mV, as below this point the saturation voltage of the open-collector output drive transistor will begin to affect the characteristic. Input and output voltages are shown in millivolts, VBUS (the supply voltage to the bus) is in volts, and R is in ohms. An example calculation for VBUS = 3.3 V, VSxxC = 200 mV, the resistance R pulling up SxxB is 2 k, then the voltage on SxxB is typically: 3.3 V SxxB = 200 mV + 50 mV + ------------ 11 = 268 mV 2000 (2) This can be compared with the offset characteristic shown in Figure 5. PCA9522 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 September 2011 © NXP B.V. 2011. All rights reserved. 11 of 20 PCA9522 NXP Semiconductors Fast dual bidirectional bus buffer with hot insertion logic 11. Package outline SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE v M A Z 5 8 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.014 0.0075 0.20 0.19 0.16 0.15 0.05 0.01 0.01 0.004 0.028 0.012 0.244 0.039 0.028 0.041 0.228 0.016 0.024 θ 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT96-1 076E03 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 11. Package outline SOT96-1 (SO8) PCA9522 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 September 2011 © NXP B.V. 2011. All rights reserved. 12 of 20 PCA9522 NXP Semiconductors Fast dual bidirectional bus buffer with hot insertion logic TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm D E SOT505-1 A X c y HE v M A Z 5 8 A2 pin 1 index (A3) A1 A θ Lp L 1 4 detail X e w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.45 0.25 0.28 0.15 3.1 2.9 3.1 2.9 0.65 5.1 4.7 0.94 0.7 0.4 0.1 0.1 0.1 0.70 0.35 6° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-04-09 03-02-18 SOT505-1 Fig 12. Package outline SOT505-1 (TSSOP8) PCA9522 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 September 2011 © NXP B.V. 2011. All rights reserved. 13 of 20 PCA9522 NXP Semiconductors Fast dual bidirectional bus buffer with hot insertion logic 12. Handling information CAUTION This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling electrostatic sensitive devices. Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or equivalent standards. 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • PCA9522 Product data sheet Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 September 2011 © NXP B.V. 2011. All rights reserved. 14 of 20 PCA9522 NXP Semiconductors Fast dual bidirectional bus buffer with hot insertion logic 13.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 13) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 5 and 6 Table 5. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 < 2.5 235 220 2.5 220 220 Table 6. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 13. PCA9522 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 September 2011 © NXP B.V. 2011. All rights reserved. 15 of 20 PCA9522 NXP Semiconductors Fast dual bidirectional bus buffer with hot insertion logic maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 13. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 14. Abbreviations Table 7. PCA9522 Product data sheet Abbreviations Acronym Description AMC Advanced Mezzanine Cards ATCA Advanced Telecommunications Computing Architecture ESD ElectroStatic Discharge FRU Field Replaceable Unit I2C-bus Inter-Integrated Circuit bus IC Integrated Circuit IPMB Intelligent Platform Management Bus PICMG PCI Industrial Computer Manufacturers Group PMBus Power Management Bus RAID Redundant Array of Independent Discs RTA Rise Time Accelerator ShMC Shelf Management Controller SMBus System Management Bus All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 September 2011 © NXP B.V. 2011. All rights reserved. 16 of 20 PCA9522 NXP Semiconductors Fast dual bidirectional bus buffer with hot insertion logic 15. References [1] UM10204, I2C-bus specification and user manual — , Rev 03, 19 June 2007; NXP B.V. www.nxp.com/documents/user_manual/UM10204.pdf [2] System Management Bus (SMBus) Specification — Version 2.0, August 3, 2000; SBS Implementers Forum. 16. Revision history Table 8. Revision history Document ID Release date Data sheet status Change notice Supersedes PCA9522 v.1 20110928 Product data sheet - - PCA9522 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 September 2011 © NXP B.V. 2011. All rights reserved. 17 of 20 PCA9522 NXP Semiconductors Fast dual bidirectional bus buffer with hot insertion logic 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. 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However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. PCA9522 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 September 2011 © NXP B.V. 2011. All rights reserved. 18 of 20 PCA9522 NXP Semiconductors Fast dual bidirectional bus buffer with hot insertion logic Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] PCA9522 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 September 2011 © NXP B.V. 2011. All rights reserved. 19 of 20 PCA9522 NXP Semiconductors Fast dual bidirectional bus buffer with hot insertion logic 19. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 8 9 10 10.1 10.2 11 12 13 13.1 13.2 13.3 13.4 14 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 VCC, GND — supply pins . . . . . . . . . . . . . . . . . 4 SCLB, SCLC, SDAB, SDAC — buffer inputs/outputs . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Enable (EN) — activate buffer operations . . . . 4 Ready (RDY) — buffer connected indicator . . . 5 Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Application information. . . . . . . . . . . . . . . . . . . 8 Design considerations . . . . . . . . . . . . . . . . . . . 8 Input to output offset voltage calculation . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Handling information. . . . . . . . . . . . . . . . . . . . 14 Soldering of SMD packages . . . . . . . . . . . . . . 14 Introduction to soldering . . . . . . . . . . . . . . . . . 14 Wave and reflow soldering . . . . . . . . . . . . . . . 14 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 15 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Contact information. . . . . . . . . . . . . . . . . . . . . 19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 28 September 2011 Document identifier: PCA9522