Data Sheet

PCA9512A; PCA9512B
Level shifting hot swappable I2C-bus and SMBus bus buffer
Rev. 6 — 1 March 2013
Product data sheet
1. General description
The PCA9512A/B is a hot swappable I2C-bus and SMBus buffer that allows I/O card
insertion into a live backplane without corruption of the data and clock buses and includes
two dedicated supply voltage pins to provide level shifting between 3.3 V and 5 V systems
while maintaining the best noise margin for each voltage level. Either pin may be powered
with supply voltages ranging from 2.7 V to 5.5 V with no constraints on which supply
voltage is higher. Control circuitry prevents the backplane from being connected to the
card until a stop bit or bus idle occurs on the backplane without bus contention on the
card. When the connection is made, the PCA9512A/B provides bidirectional buffering,
keeping the backplane and card capacitances isolated.
Both the PCA9512A and PCA9512B use identical silicon (PCN201012007F dated
13 Dec 2010), so the PCA9512B will be discontinued in the near future and is not
recommended for new designs.
The PCA9512A/B rise time accelerator circuitry allows the use of weaker DC pull-up
currents while still meeting rise time requirements. The PCA9512A/B incorporates a digital
input pin that enables and disables the rise time accelerators on all four SDAn and SCLn
pins.
During insertion, the PCA9512A/B SDAn and SCLn pins are precharged to 1 V to
minimize the current required to charge the parasitic capacitance of the chip.
The incremental offset design of the PCA9510A/11A/12A/12B/13A/14A I/O drivers allows
them to be connected to another PCA9510A/11A/12A/12B/13A/14A device in series or in
parallel and to the I2C compliant side of static offset bus buffers, but not to the static offset
side of those bus buffers.
2. Features and benefits
 Bidirectional buffer for SDA and SCL lines increases fan-out and prevents SDA and
SCL corruption during live board insertion and removal from multipoint backplane
systems
 Compatible with I2C-bus Standard mode, I2C-bus Fast mode, and SMBus standards
 Built-in V/t rise time accelerators on all SDA and SCL lines (0.6 V threshold) with
ability to disable V/t rise time accelerator through the ACC pin for lightly loaded
systems, requires the bus pull-up voltage and respective supply voltage (VCC or VCC2)
to be the same
 5 V to 3.3 V level translation with optimum noise margin
 High-impedance SDAn and SCLn pins for VCC or VCC2 = 0 V
 1 V precharge on all SDAn and SCLn pins
 Supports clock stretching and multiple master arbitration and synchronization
PCA9512A; PCA9512B
NXP Semiconductors
Level shifting hot swappable I2C-bus and SMBus bus buffer
 Operating power supply voltage range: 2.7 V to 5.5 V
 0 Hz to 400 kHz clock frequency
 ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
 Packages offered: SO8, TSSOP8 (MSOP8)
3. Applications
 cPCI, VME, AdvancedTCA cards and other multipoint backplane cards that are
required to be inserted or removed from an operating system
4. Feature selection
Table 1.
Feature selection chart
Feature
PCA9510A PCA9511A PCA9512A/B PCA9513A PCA9514A
Idle detect
yes
High-impedance SDAn, SCLn pins for VCC = 0 V
yes
yes
yes
yes
yes
yes
yes
yes
yes
Rise time accelerator circuitry on SDAn and SCLn pins -
yes
yes
yes
yes
Rise time accelerator circuitry hardware disable pin for lightly loaded systems
-
yes
-
-
Rise time accelerator threshold 0.8 V versus 0.6 V
improves noise margin
-
-
-
yes
yes
Ready open-drain output
yes
yes
-
yes
yes
Two VCC pins to support 5 V to 3.3 V level translation
with improved noise margins
-
-
yes
-
-
1 V precharge on all SDAn and SCLn pins
in only
yes
yes
-
-
-
-
yes
-
92 A current source on SCLIN and SDAIN for PICMG applications
PCA9512A_PCA9512B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 1 March 2013
© NXP B.V. 2013. All rights reserved.
2 of 27
PCA9512A; PCA9512B
NXP Semiconductors
Level shifting hot swappable I2C-bus and SMBus bus buffer
5. Ordering information
Table 2.
Ordering information
Type number
Topside
mark
Package
Name
Description
Version
PCA9512AD
PA9512A
SO8
plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
PCA9512BD
PA9512B
PCA9512ADP
9512A
TSSOP8[1]
plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1
PCA9512BDP
9512B
[1]
Also known as MSOP8.
5.1 Ordering options
Table 3.
Ordering options
Type number
Orderable
part number
Package
Packing method
Minimum
order
quantity
Temperature range
PCA9512AD
PCA9512AD,112
SO8
standard marking *
IC’s tube - DSC bulk pack
2000
Tamb = 40 C to +85 C
PCA9512AD,118
SO8
reel 13” Q1/T1
*standard mark SMD
2500
Tamb = 40 C to +85 C
PCA9512BD
PCA9512BD,118
SO8
reel 13” Q1/T1
*standard mark SMD
2500
Tamb = 40 C to +85 C
PCA9512ADP
PCA9512ADP,118
TSSOP8
reel 13” Q1/T1
*standard mark SMD
2500
Tamb = 40 C to +85 C
PCA9512BDP
PCA9512BDP,118
TSSOP8
reel 13” Q1/T1
*standard mark SMD
2500
Tamb = 40 C to +85 C
PCA9512A_PCA9512B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 1 March 2013
© NXP B.V. 2013. All rights reserved.
3 of 27
PCA9512A; PCA9512B
NXP Semiconductors
Level shifting hot swappable I2C-bus and SMBus bus buffer
6. Block diagram
PCA9512A/B
VCC2
VCC
2 mA
2 mA
SLEW RATE
DETECTOR
SLEW RATE
DETECTOR
ACC
BACKPLANE-TO-CARD
CONNECTION
SDAIN
CONNECT
SDAOUT
CONNECT
CONNECT
100 kΩ
RCH3
100 kΩ
RCH1
1 VOLT
PRECHARGE
100 kΩ
RCH2
100 kΩ
RCH4
2 mA
2 mA
SLEW RATE
DETECTOR
ACC
SLEW RATE
DETECTOR
ACC
BACKPLANE-TO-CARD
CONNECTION
SCLIN
SCLOUT
CONNECT
CONNECT
LEVEL
SHIFTER
0.5 μA
0.55VCC/
0.45VCC
0.55VCC/
0.45VCC
UVLO
STOP BIT AND
BUS IDLE
CONNECT
20 pF
UVLO
100 μs
DELAY
CONNECT
RD
S
QB
GND
0.5 pF
002aag555
Fig 1.
Block diagram of PCA9512A/B
PCA9512A_PCA9512B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 1 March 2013
© NXP B.V. 2013. All rights reserved.
4 of 27
PCA9512A; PCA9512B
NXP Semiconductors
Level shifting hot swappable I2C-bus and SMBus bus buffer
7. Pinning information
7.1 Pinning
VCC2
1
SCLOUT
2
SCLIN
3
GND
4
PCA9512AD
PCA9512BD
8
VCC
7
SDAOUT
6
SDAIN
5
ACC
VCC2
1
8
VCC
SCLOUT
2
7
SDAOUT
SCLIN
3
6
SDAIN
GND
4
5
ACC
002aab790
002aab789
Fig 2.
Pin configuration for SO8
PCA9512ADP
PCA9512BDP
Fig 3.
Pin configuration for TSSOP8
7.2 Pin description
Table 4.
Pin description
Symbol
Pin
Description
VCC2
1
Supply voltage for devices on the card I2C-bus. Connect pull-up resistors
from SDAOUT and SCLOUT to this pin.
SCLOUT
2
serial clock output to and from the SCL bus on the card
SCLIN
3
serial clock input to and from the SCL bus on the backplane
GND
4
ground supply; connect this pin to a ground plane for best results.
ACC
5
CMOS threshold digital input pin that enables and disables the rise time
accelerators on all four SDAn and SCLn pins. ACC enables all accelerators
when set to VCC2, and turns them off when set to GND.
SDAIN
6
serial data input to and from the SDA bus on the backplane
SDAOUT
7
serial data output to and from the SDA bus on the card
VCC
8
supply voltage; from the backplane, connect pull-up resistors from SDAIN
and SCLIN to this pin.
8. Functional description
Refer to Figure 1 “Block diagram of PCA9512A/B”.
Both the PCA9512A and PCA9512B use identical silicon (PCN201012007F dated
13 Dec 2010), so the PCA9512B will be discontinued in the near future and is not
recommended for new designs. Customers should continue using the PCA9512A or move
to the PCA9512A during the next refresh if they are currently using the PCA9512B.
Description of the PCA9512A operation applies equally to the PCA9512B for the
remainder of this data sheet.
8.1 Start-up
When the PCA9512A is powered up, either VCC or VCC2 may rise first, within a short time
of each other and either may be more positive or they may be equal, however the
PCA9512A will not leave the undervoltage lockout or initialization state until both VCC and
VCC2 have gone above 2.5 V. If either VCC or VCC2 drops below 2.0 V it will return to the
undervoltage lockout state.
PCA9512A_PCA9512B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 1 March 2013
© NXP B.V. 2013. All rights reserved.
5 of 27
PCA9512A; PCA9512B
NXP Semiconductors
Level shifting hot swappable I2C-bus and SMBus bus buffer
In the undervoltage lockout state the connection circuitry is disabled, the rise time
accelerators are disabled, and the precharge circuitry is also disabled. After both VCC and
VCC2 are valid, independent of which is higher, the PCA9512A/B enters the initialization
state; during this state the 1 V precharge circuitry is activated and pulls up the SDAn and
SCLn pins to 1 V through individual 100 k nominal resistors. At the end of the
initialization state the ‘Stop bit and bus idle’ detect circuit is enabled. When all the SDAn
and SCLn pins have been HIGH for the bus idle time or when all pins are HIGH and a
STOP condition is seen on the SDAIN and SCLIN pins, the connect circuitry is activated,
connecting SDAIN to SDAOUT and SCLIN to SCLOUT. The 1 V precharge circuitry is
disabled when the connection is made, unless the ACC pin is LOW; the rise time
accelerators are enabled at this time also.
8.2 Connect circuitry
Once the connection circuitry is activated, the behavior of SDAIN and SDAOUT as well as
SCLIN and SCLOUT become identical, with each acting as a bidirectional buffer that
isolates the input bus capacitance from the output bus capacitance while communicating.
If VCC  VCC2, then a level shifting function is performed between input and output. A LOW
forced on either SDAIN or SDAOUT will cause the other pin to be driven to a LOW by the
PCA9512A/B. The same is also true for the SCLn pins. Noise between 0.7VCC and VCC
on the SDAIN and SCLIN pins, and 0.7VCC2 and VCC2 on the SDAOUT and SCLOUT pins
is generally ignored because a falling edge is only recognized when it falls below 0.7VCC
for SDAIN and SCLIN (or 0.7VCC2 for SDAOUT and SCLOUT pins) with a slew rate of at
least 1.25 V/s. When a falling edge is seen on one pin, the other pin in the pair turns on a
pull-down driver that is referenced to a small voltage above the falling pin. The driver will
pull the pin down at a slew rate determined by the driver and the load. The first falling pin
may have a fast or slow slew rate; if it is faster than the pull-down slew rate, then the initial
pull-down rate will continue until it is LOW. If the first falling pin has a slow slew rate, then
the second pin will be pulled down at its initial slew rate only until it is just above the first
pin voltage then they will both continue down at the slew rate of the first.
Once both sides are LOW they will remain LOW until all the external drivers have stopped
driving LOWs. If both sides are being driven LOW to the same (or nearly the same) value
by external drivers, which is the case for clock stretching and is typically the case for
acknowledge, and one side external driver stops driving, that pin will rise and rise above
the nominal offset voltage until the internal driver catches up and pulls it back down to the
offset voltage. This bounce is worst for low capacitances and low resistances, and may
become excessive. When the last external driver stops driving a LOW, that pin will bounce
up and settle out just above the other pin as both rise together with a slew rate determined
by the internal slew rate control and the RC time constant. As long as the slew rate is at
least 1.25 V/s, when the pin voltage exceeds 0.6 V, the rise time accelerator circuits are
turned on and the pull-down driver is turned off. If the ACC pin is LOW, the rise time
accelerator circuits will be disabled, but the pull-down driver will still turn off.
8.3 Maximum number of devices in series
Each buffer adds about 0.1 V dynamic level offset at 25 C with the offset larger at higher
temperatures. Maximum offset (Voffset) is 0.150 V with a 10 k pull-up resistor. The LOW
level at the signal origination end (master) is dependent upon the load and the only
specification point is the I2C-bus specification of 3 mA will produce VOL < 0.4 V, although if
lightly loaded the VOL may be ~0.1 V. Assuming VOL = 0.1 V and Voffset = 0.1 V, the level
after four buffers would be 0.5 V, which is only about 0.1 V below the threshold of the
PCA9512A_PCA9512B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 1 March 2013
© NXP B.V. 2013. All rights reserved.
6 of 27
PCA9512A; PCA9512B
NXP Semiconductors
Level shifting hot swappable I2C-bus and SMBus bus buffer
rising edge accelerator (about 0.6 V). With great care a system with four buffers may
work, but as the VOL moves up from 0.1 V, noise or bounces on the line will result in firing
the rising edge accelerator thus introducing false clock edges. Generally it is
recommended to limit the number of buffers in series to two, and to keep the load light to
minimize the offset.
The PCA9510A (rise time accelerator is permanently disabled) and the PCA9512A (rise
time accelerator can be turned off) are a little different with the rise time accelerator turned
off because the rise time accelerator will not pull the node up, but the same logic that turns
on the accelerator turns the pull-down off. If the VIL is above ~0.6 V and a rising edge is
detected, the pull-down will turn off and will not turn back on until a falling edge is
detected.
buffer A
MASTER
buffer B
SLAVE B
common
node
buffer C
SLAVE C
002aab581
Fig 4.
System with 3 buffers connected to common node
Consider a system with three buffers connected to a common node and communication
between the Master and Slave B that are connected at either end of buffer A and buffer B
in series as shown in Figure 4. Consider if the VOL at the input of buffer A is 0.3 V and the
VOL of Slave B (when acknowledging) is 0.4 V with the direction changing from Master to
Slave B and then from Slave B to Master. Before the direction change you would observe
VIL at the input of buffer A of 0.3 V and its output, the common node, is ~0.4 V. The output
of buffer B and buffer C would be ~0.5 V, but Slave B is driving 0.4 V, so the voltage at
Slave B is 0.4 V. The output of buffer C is ~0.5 V. When the Master pull-down turns off, the
input of buffer A rises and so does its output, the common node, because it is the only part
driving the node. The common node will rise to 0.5 V before buffer B’s output turns on, if
the pull-up is strong the node may bounce. If the bounce goes above the threshold for the
rising edge accelerator ~0.6 V the accelerators on both buffer A and buffer C will fire
contending with the output of buffer B. The node on the input of buffer A will go HIGH as
will the input node of buffer C. After the common node voltage is stable for a while the
rising edge accelerators will turn off and the common node will return to ~0.5 V because
the buffer B is still on. The voltage at both the Master and Slave C nodes would then fall to
~0.6 V until Slave B turned off. This would not cause a failure on the data line as long as
the return to 0.5 V on the common node (~0.6 V at the Master and Slave C) occurred
before the data setup time. If this were the SCL line, the parts on buffer A and buffer C
would see a false clock rather than a stretched clock, which would cause a system error.
PCA9512A_PCA9512B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 1 March 2013
© NXP B.V. 2013. All rights reserved.
7 of 27
PCA9512A; PCA9512B
NXP Semiconductors
Level shifting hot swappable I2C-bus and SMBus bus buffer
8.4 Propagation delays
The delay for a rising edge is determined by the combined pull-up current from the bus
resistors and the rise time accelerator current source and the effective capacitance on the
lines. If the pull-up currents are the same, any difference in rise time is directly
proportional to the difference in capacitance between the two sides. The tPLH may be
negative if the output capacitance is less than the input capacitance and would be positive
if the output capacitance is larger than the input capacitance, when the currents are the
same.
The tPHL can never be negative because the output does not start to fall until the input is
below 0.7VCC (or 0.7VCC2 for SDAOUT and SCLOUT), and the output turn-ON has a
non-zero delay, and the output has a limited maximum slew rate, and even if the input
slew rate is slow enough that the output catches up it will still lag the falling voltage of the
input by the offset voltage. The maximum tPHL occurs when the input is driven LOW with
zero delay and the output is still limited by its turn-on delay and the falling edge slew rate.
The output falling edge slew rate is a function of the internal maximum slew rate which is
a function of temperature, VCC or VCC2 and process, as well as the load current and the
load capacitance.
8.5 Rise time accelerators
During positive bus transactions, a 2 mA current source is switched on to quickly slew the
SDA and SCL lines HIGH once the input level of 0.6 V for the PCA9512A is exceeded.
The rising edge rate should be at least 1.25 V/s to guarantee turn on of the accelerators.
The built-in V/t rise time accelerators on all SDA and SCL lines requires the bus pull-up
voltage and respective supply voltage (VCC or VCC2) to be the same. The built-in V/t
rise time accelerators can be disabled through the ACC pin for lightly loaded systems.
8.6 ACC boost current enable
Users having lightly loaded systems may wish to disable the rise time accelerators.
Driving this pin to ground turns off the rise time accelerators on all four SDAn and SCLn
pins. Driving this pin to the VCC2 voltage enables normal operation of the rise time
accelerators.
8.7 Resistor pull-up value selection
The system pull-up resistors must be strong enough to provide a positive slew rate of
1.25 V/s on the SDAn and SCLn pins, in order to activate the boost pull-up currents
during rising edges. Choose maximum resistor value using the formula given in
Equation 1:
3 V CC  min  – 0.6
R PU  800  10  -----------------------------------


C
(1)
where RPU is the pull-up resistor value in , VCC(min) is the minimum VCC voltage in volts,
and C is the equivalent bus capacitance in picofarads.
PCA9512A_PCA9512B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 1 March 2013
© NXP B.V. 2013. All rights reserved.
8 of 27
PCA9512A; PCA9512B
NXP Semiconductors
Level shifting hot swappable I2C-bus and SMBus bus buffer
In addition, regardless of the bus capacitance, always choose RPU  65.7 k for
VCC = 5.5 V maximum, RPU  45 k for VCC = 3.6 V maximum. The start-up circuitry
requires logic HIGH voltages on SDAOUT and SCLOUT to connect the backplane to the
card, and these pull-up values are needed to overcome the precharge voltage. See the
curves in Figure 5 and Figure 6 for guidance in resistor pull-up selection.
002aae782
50
RPU
(kΩ)
Rmax = 45 kΩ
40
(1)
30
rise time = 300 ns(2)
20
rise time = 20 ns
10
Rmin = 1 kΩ
0
0
100
200
300
400
Cb (pF)
(1) Unshaded area indicates recommended pull-up, for rise time < 300 ns, with rise time accelerator turned on.
(2) Rise time accelerator off.
Fig 5.
Bus requirements for 3.3 V systems
002aae783
70
RPU
(kΩ)
Rmax = 65.7 kΩ
60
50
(1)
40
rise time = 300 ns(2)
30
20
rise time = 20 ns
10
Rmin = 1.7 kΩ
0
0
100
200
300
400
Cb (pF)
(1) Unshaded area indicates recommended pull-up, for rise time < 300 ns, with rise time accelerator turned on.
(2) Rise time accelerator off.
Fig 6.
Bus requirements for 5 V systems
PCA9512A_PCA9512B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 1 March 2013
© NXP B.V. 2013. All rights reserved.
9 of 27
PCA9512A; PCA9512B
NXP Semiconductors
Level shifting hot swappable I2C-bus and SMBus bus buffer
8.8 Hot swapping and capacitance buffering application
Figure 7 through Figure 9 illustrate the usage of the PCA9512A in applications that take
advantage of both its hot swapping and capacitance buffering features. In all of these
applications, note that if the I/O cards were plugged directly into the backplane, all of the
backplane and card capacitances would add directly together, making rise time and
fall time requirements difficult to meet. Placing a bus buffer on the edge of each card,
however, isolates the card capacitance from the backplane. For a given I/O card, the
PCA9512A drives the capacitance of everything on the card and the backplane must drive
only the capacitance of the bus buffer, which is less than 10 pF, the connector, trace, and
all additional cards on the backplane.
See Application Note AN10160, ‘Hot Swap Bus Buffer’ for more information on
applications and technical assistance.
BACKPLANE
CONNECTOR
BACKPLANE
R1
10 kΩ
STAGGERED CONNECTOR
VCC
SDA
SCL
STAGGERED CONNECTOR
BD_SEL
I/O PERIPHERAL CARD 1
POWER SUPPLY
HOT SWAP
POWER SUPPLY
HOT SWAP
STAGGERED CONNECTOR
VCC2
POWER SUPPLY
HOT SWAP
R3
5.1 Ω
C2
C1
0.01 μF
R4
10 kΩ
R5
10 kΩ
R6
10 kΩ
PCA9512A
0.01 μF
VCC
SDAIN
SCLIN
VCC2
GND
SDAOUT
SCLOUT
ACC
CARD1_SDA
CARD1_SCL
R2
10 kΩ
I/O PERIPHERAL CARD 2
R7
5.1 Ω
C4
C3
0.01 μF
R8
10 kΩ
R9
10 kΩ
R10
10 kΩ
PCA9512A
0.01 μF
VCC
SDAIN
SCLIN
VCC2
GND
SDAOUT
SCLOUT
ACC
CARD2_SDA
CARD2_SCL
I/O PERIPHERAL CARD N
R11
5.1 Ω
C6
C5
0.01 μF
R12
10 kΩ
R13
10 kΩ
R14
10 kΩ
PCA9512A
0.01 μF
VCC
SDAIN
SCLIN
VCC2
GND
SDAOUT
SCLOUT
ACC
CARDN_SDA
CARDN_SCL
002aab791
Remark: Application assumes bus capacitance within ‘proper operation’ region of Figure 5 and Figure 6.
Fig 7.
Hot swapping multiple I/O cards into a backplane using the PCA9512A in a cPCI, VME, and AdvancedTCA
system
PCA9512A_PCA9512B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 1 March 2013
© NXP B.V. 2013. All rights reserved.
10 of 27
PCA9512A; PCA9512B
NXP Semiconductors
Level shifting hot swappable I2C-bus and SMBus bus buffer
BACKPLANE
CONNECTOR
BACKPLANE
STAGGERED CONNECTOR
I/O PERIPHERAL CARD 1
VCC2
VCC
SDA
SCL
R1
10 kΩ
C1
0.01 μF
R4
10 kΩ
R5
10 kΩ
R6
10 kΩ
PCA9512A
R3
5.1 Ω
C2
0.01 μF
VCC
SDAIN
SCLIN
VCC2
GND
SDAOUT
SCLOUT
ACC
CARD1_SDA
CARD1_SCL
R2
10 kΩ
STAGGERED CONNECTOR
I/O PERIPHERAL CARD 2
C3
0.01 μF
R8
10 kΩ
R9
10 kΩ
R10
10 kΩ
PCA9512A
R7
5.1 Ω
C4
0.01 μF
VCC
SDAIN
SCLIN
VCC2
GND
SDAOUT
SCLOUT
ACC
CARD2_SDA
CARD2_SCL
002aab792
Remark: Application assumes bus capacitance within ‘proper operation’ region of Figure 5 and Figure 6.
Fig 8.
Hot swapping multiple I/O cards into a backplane using the PCA9512A with a custom connector
CARD_VCC (3 V)
VCC (5 V)
R1
10 kΩ
R4
10 kΩ
C2
0.01 μF
C1
0.01 μF
SDAIN
SCLIN
R2
10 kΩ
VCC2
VCC
SDA
SCL
R3
10 kΩ
SDAOUT
PCA9512A SCLOUT
CARD_SDA
CARD_SCL
ACC
GND
002aab793
Remark: Application assumes bus capacitance within ‘proper operation’ region of Figure 5 and Figure 6.
Fig 9.
5 V to 3.3 V level translator and bus buffer
PCA9512A_PCA9512B
Product data sheet
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Level shifting hot swappable I2C-bus and SMBus bus buffer
8.9 Voltage level translator discussion
8.9.1 Summary
There are two popular configurations for the interface of low voltage logic (i.e., core
processor with 3.3 V supply) to standard bus levels (i.e., I2C-bus with 5 V supply). A single
FET transistor and two additional resistors may be used effectively, or an
application-specific IC part requiring no external components and no additional resistors.
The FET solution becomes problematic as the low voltage logic levels trend downwards.
The FET solution will stop working completely when the FET specification is no longer
matched to the LOW level logic supply voltage requirements.
The dominant advantage of the FET solution is cost, but the IC part provides additional
advantages to the design, which increases reliability to the end user.
8.9.2 Why do level translation?
Advances in processing technology require lower supply voltages, due to reduced
clearances in the fabrication technology. Lower supply voltages drive down signal swings,
or require that on die high voltage I/O sections are added, creating larger die area, or
greater I/O pin count. Existing standards for interoperability of equipment connected by
cables or between subsystems require higher voltage signal swings (typically 5 V).
An external voltage level translator solves these problems, but requires additional parts.
8.10 Limitations of the FET voltage level translator
8.10.1 VGSth, gate-source threshold voltage
When the VA input is logic LOW, the FET is turned on, pulling VB output LOW. This can
only occur when the threshold voltage of the FET is less than the VA supply voltage minus
the maximum level of the VA signal, VAIL. Using CMOS logic thresholds of 0.3 and
0.7 times the supply, and a 1.1 V VA gives a worst-case of just 330 mV, much less than
VGSth of the popular 2N7002 FET.
VGSth; ID = 250 A; VDS = VGS; 1.1 V (min.)/1.6 V (typ.)/2.1 V (max.)
Additionally, the FET threshold voltage is specified in the linear region of the FET, with
weak conduction. Ideally the FET should have very low ON-resistance. For the 2N7002,
this is specified at 5 V VGS (not the 1 V available in this application). Note that the
ON-resistance decreases rapidly as VGS is increased beyond the VGSth specification.
Unintended operation in the linear region further compromises logic level noise immunity.
8.10.2 FET body diode voltage
The FET is required to conduct in both directions, as the I2C-bus is bidirectional. When
the VB input is logic LOW, the body diode of the FET conducts first, pulling the FET
source LOW along with the FET drain, until the FET conducts. During this transition the
forward voltage drop of the body diode reduces the available FET gain to source bias. The
body diode is specified:
VSD, source-drain voltage; IS = 115 mA; VGS = 0 V; 0.47 V (min.)/0.75 V (typ.)/1.1 V
(max.)
Conduction of the FET body diode impacts both the delay time and logic transition speed.
PCA9512A_PCA9512B
Product data sheet
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Level shifting hot swappable I2C-bus and SMBus bus buffer
8.11 Additional system compromises
•
•
•
•
•
•
Additional parts
Additional assembly cost
Reduced system reliability due to complexity
Reduced logic level noise margin (immunity)
Sensitivity to ground offsets between sub-systems (cable links, for example)
Increased loading on the low voltage side (must carry the high voltage side
sink current)
• ESD robustness
9. Application design-in information
VCC
(5 V)
R1
10 kΩ
R2
10 kΩ
C2
0.01 μF
VCC
SDA
SCL
CARD_VCC (3 V)
C1
0.01 μF
R3
10 kΩ
R4
10 kΩ
R5
10 kΩ
VCC2
SDAIN
SDAOUT
SCLIN
SCLOUT
CARD_SDA
CARD_SCL
PCA9512A
ACC
GND
002aab794
Fig 10. Typical application
PCA9512A_PCA9512B
Product data sheet
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Level shifting hot swappable I2C-bus and SMBus bus buffer
10. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VCC
supply voltage
Conditions
Min
Max
Unit
0.5
+7
V
0.5
+7
V
0.5
+7
V
input current
[2]
-
20
mA
II/O
input/output current
[3]
-
50
mA
2[1]
VCC2
supply voltage
Vn
voltage on any other pin
II
Toper
operating temperature
40
+85
C
Tstg
storage temperature
65
+125
C
Tsp
solder point temperature
-
300
C
Tj(max)
maximum junction temperature
-
125
C
[1]
Card side supply voltage.
[2]
Maximum current for inputs.
[3]
Maximum current for I/O pins.
10 s maximum
11. Characteristics
Table 6.
Characteristics
VCC = 2.7 V to 5.5 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
[1]
2.7
-
5.5
V
[1]
2.7
-
5.5
V
Power supply
VCC
supply voltage
2[2]
VCC2
supply voltage
ICC
supply current
VCC = 5.5 V;
VSDAIN = VSCLIN = 0 V
-
1.8
3.6
mA
ICC2
supply current 2
VCC = 5.5 V;
VSDAOUT = VSCLOUT = 0 V
-
1.7
2.9
mA
Start-up circuitry
Vpch
ten
tidle
precharge voltage
enable time
SDA, SCL floating
[1]
0.8
1.1
1.2
V
on power-up
[3]
idle time
-
180
-
s
[1][4]
50
140
250
s
[5][6]
1
2
-
mA
Rise time accelerators
Itrt(pu)
transient boosted pull-up
current
positive transition on SDA, SCL;
VACC = 0.7  VCC2; VCC = 2.7 V;
slew rate = 1.25 V/s
Vth(dis)(ACC)
disable threshold voltage
on pin ACC
0.3VCC2
0.5VCC2 -
Vth(en)(ACC)
enable threshold voltage
on pin ACC
-
0.5VCC2 0.7VCC2 V
II(ACC)
input current on pin ACC
1
0.1
+1
A
-
5
-
ns
tPD(on/off)(ACC) on/off propagation delay
on pin ACC
PCA9512A_PCA9512B
Product data sheet
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V
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Level shifting hot swappable I2C-bus and SMBus bus buffer
Table 6.
Characteristics …continued
VCC = 2.7 V to 5.5 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
0
115
175
mV
-
-
10
pF
0
0.3
0.4
V
1
-
+1
A
Input-output connection
Voffset
offset voltage
10 k to VCC on SDA, SCL;
VCC = 3.3 V; VCC2 = 3.3 V;
VI = 0.2 V
Ci
input capacitance
digital; guaranteed by design,
not subject to test
VOL
LOW-level output voltage
VI = 0 V; SDAn, SCLn pins;
Isink = 3 mA; VCC = 2.7 V;
VCC2 = 2.7 V
ILI
input leakage current
SDAn, SCLn pins; VCC = 5.5 V;
VCC2 = 5.5 V
[1][7]
[1]
System characteristics
SCL clock frequency
[8]
0
-
400
kHz
tBUF
bus free time between a
STOP and START
condition
[8]
1.3
-
-
s
tHD;STA
hold time (repeated)
START condition
[8]
0.6
-
-
s
tSU;STA
set-up time for a repeated
START condition
[8]
0.6
-
-
s
tSU;STO
set-up time for STOP
condition
[8]
0.6
-
-
s
tHD;DAT
data hold time
[8]
300
-
-
ns
tSU;DAT
data set-up time
[8]
100
-
-
ns
tLOW
LOW period of the SCL
clock
[8]
1.3
-
-
s
tHIGH
HIGH period of the SCL
clock
[8]
0.6
-
-
s
tf
fall time of both SDA and
SCL signals
[8][9]
20 + 0.1  Cb -
300
ns
tr
rise time of both SDA and
SCL signals
[8][9]
20 + 0.1  Cb -
300
ns
fSCL
[1]
This specification applies over the full operating temperature range.
[2]
Card side supply voltage.
[3]
The enable time is from power-up of VCC and VCC2  2.7 V to when idle or stop time begins.
[4]
Idle time is from when SDAn and SCLn are HIGH after enable time has been met.
[5]
Itrt(pu) varies with temperature and VCC voltage, as shown in Section 11.1 “Typical performance characteristics”.
[6]
Input pull-up voltage should not exceed power supply voltage in operating mode because the rise time accelerator will clamp the voltage
to the positive supply rail.
[7]
The connection circuitry always regulates its output to a higher voltage than its input. The magnitude of this offset voltage as a function
of the pull-up resistor and VCC voltage is shown in Section 11.1 “Typical performance characteristics”.
[8]
Guaranteed by design, not production tested.
[9]
Cb = total capacitance of one bus line in pF.
PCA9512A_PCA9512B
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Level shifting hot swappable I2C-bus and SMBus bus buffer
11.1 Typical performance characteristics
002aab795
2.15
ICC
(mA)
Itrt(pu)
(mA)
VCC = 5.5 V
3.3 V
2.7 V
1.95
002aab796
12
VCC = 5 V
8
1.75
4
3.3 V
1.55
2.7 V
1.35
−40
+25
+90
Tamb (°C)
0
−40
+25
+90
Tamb (°C)
ICC2 (pin 1) typical current averages 0.1 mA less than ICC
on pin 8.
Fig 11. ICC versus temperature
Fig 12. Itrt(pu) versus temperature
002aab589
90
002aab591
350
VCC = 5.5 V
VO − VI
(mV)
tPHL
(ns)
80
250
2.7 V
3.3 V
70
150
VCC = 5 V
3.3 V
60
−40
50
+25
+90
Ci = Co > 100 pF; RPU(in) = RPU(out) = 10 k
Fig 13. Input/output tPHL versus temperature
PCA9512A_PCA9512B
Product data sheet
0
10
20
30
Tamb (°C)
40
RPU (kΩ)
VCC = 3.3 V or 5.5 V
Fig 14. Connection circuitry VO  VI
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Level shifting hot swappable I2C-bus and SMBus bus buffer
12. Test information
VCC
VCC
PULSE
GENERATOR
VI
VO
RL
10 kΩ
DUT
RT
CL
100 pF
002aab595
RL = load resistor
CL = load capacitance includes jig and probe capacitance
RT = termination resistance should be equal to the output impedance Zo of the pulse generator
Fig 15. Test circuitry for switching times
PCA9512A_PCA9512B
Product data sheet
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Level shifting hot swappable I2C-bus and SMBus bus buffer
13. Package outline
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
D
E
A
X
c
y
HE
v M A
Z
5
8
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
4
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
inches
0.069
0.010 0.057
0.004 0.049
0.01
0.019 0.0100
0.014 0.0075
0.20
0.19
0.16
0.15
0.05
0.01
0.01
0.004
0.028
0.012
0.244
0.039 0.028
0.041
0.228
0.016 0.024
θ
8o
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT96-1
076E03
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
Fig 16. Package outline SOT96-1 (SO8)
PCA9512A_PCA9512B
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Level shifting hot swappable I2C-bus and SMBus bus buffer
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm
D
E
SOT505-1
A
X
c
y
HE
v M A
Z
5
8
A2
pin 1 index
(A3)
A1
A
θ
Lp
L
1
4
detail X
e
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(2)
e
HE
L
Lp
v
w
y
Z(1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.45
0.25
0.28
0.15
3.1
2.9
3.1
2.9
0.65
5.1
4.7
0.94
0.7
0.4
0.1
0.1
0.1
0.70
0.35
6°
0°
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-04-09
03-02-18
SOT505-1
Fig 17. Package outline SOT505-1 (TSSOP8)
PCA9512A_PCA9512B
Product data sheet
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Level shifting hot swappable I2C-bus and SMBus bus buffer
14. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
PCA9512A_PCA9512B
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Level shifting hot swappable I2C-bus and SMBus bus buffer
14.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 18) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 7 and 8
Table 7.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
 350
< 2.5
235
220
 2.5
220
220
Table 8.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 18.
PCA9512A_PCA9512B
Product data sheet
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Level shifting hot swappable I2C-bus and SMBus bus buffer
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 18. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
15. Soldering: PCB footprints
5.50
0.60 (8×)
1.30
4.00
6.60
7.00
1.27 (6×)
solder lands
occupied area
placement accuracy ± 0.25
Dimensions in mm
sot096-1_fr
Fig 19. PCB footprint for SOT96-1 (SO8); reflow soldering
PCA9512A_PCA9512B
Product data sheet
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Level shifting hot swappable I2C-bus and SMBus bus buffer
1.20 (2×)
0.60 (6×)
enlarged solder land
0.3 (2×)
1.30
4.00
6.60
7.00
1.27 (6×)
5.50
board direction
solder lands
occupied area
solder resist
placement accurracy ± 0.25
Dimensions in mm
sot096-1_fw
Fig 20. PCB footprint for SOT96-1 (SO8); wave soldering
3.600
2.950
0.125
0.725
0.125
5.750
3.200
3.600
5.500
1.150
0.600
0.450
0.650
solder lands
occupied area
Dimensions in mm
sot505-1_fr
Fig 21. PCB footprint for SOT505-1 (TSSOP8); reflow soldering
PCA9512A_PCA9512B
Product data sheet
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Level shifting hot swappable I2C-bus and SMBus bus buffer
16. Abbreviations
Table 9.
Abbreviations
Acronym
Description
AdvancedTCA
Advanced Telecommunications Computing Architecture
AVL
Approved Vendor List
CDM
Charged-Device Model
CMOS
Complementary Metal-Oxide Semiconductor
cPCI
compact Peripheral Component Interface
ESD
Electrostatic Discharge
FET
Field-Effect Transistor
HBM
Human Body Model
I2C-bus
Inter-Integrated Circuit bus
IC
Integrated Circuit
PCI
Peripheral Component Interface
PICMG
PCI Industrial Computer Manufacturers Group
SMBus
System Management Bus
VME
VERSAModule Eurocard
17. Revision history
Table 10.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCA9512A_PCA9512B v.6
20130301
Product data sheet
-
PCA9512A_PCA9512B v.5
Modifications:
•
•
Section 1 “General description”: second paragraph re-written
•
•
•
•
Added Section 5.1 “Ordering options”
•
•
•
•
Section 2 “Features and benefits”: 11th bullet item: deleted “200 V MM per
JESD22-A115”
Figure 1 “Block diagram of PCA9512A/B”: added “LEVEL SHIFTER” block
Section 8 “Functional description”: added (new) second paragraph
Figure 10 “Typical application”: changed type number from “PCA9512A/B” to
“PCA9512A”
Added Section 8.9 “Voltage level translator discussion”
Added Section 8.10 “Limitations of the FET voltage level translator”
Added Section 8.11 “Additional system compromises”
Added Section 15 “Soldering: PCB footprints”
PCA9512A_PCA9512B v.5
20110105
Product data sheet
-
PCA9512A v.4
PCA9512A v.4
20090819
Product data sheet
-
PCA9512A v.3
PCA9512A v.3
20090720
Product data sheet
-
PCA9512A v.2
PCA9512A v.2
20090528
Product data sheet
-
PCA9512A v.1
PCA9512A v.1
20051007
Product data sheet
-
-
PCA9512A_PCA9512B
Product data sheet
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NXP Semiconductors
Level shifting hot swappable I2C-bus and SMBus bus buffer
18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PCA9512A_PCA9512B
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 1 March 2013
© NXP B.V. 2013. All rights reserved.
25 of 27
PCA9512A; PCA9512B
NXP Semiconductors
Level shifting hot swappable I2C-bus and SMBus bus buffer
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PCA9512A_PCA9512B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 1 March 2013
© NXP B.V. 2013. All rights reserved.
26 of 27
PCA9512A; PCA9512B
NXP Semiconductors
Level shifting hot swappable I2C-bus and SMBus bus buffer
20. Contents
1
2
3
4
5
5.1
6
7
7.1
7.2
8
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Feature selection . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional description . . . . . . . . . . . . . . . . . . . 5
Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Connect circuitry . . . . . . . . . . . . . . . . . . . . . . . . 6
Maximum number of devices in series . . . . . . . 6
Propagation delays . . . . . . . . . . . . . . . . . . . . . . 8
Rise time accelerators . . . . . . . . . . . . . . . . . . . 8
ACC boost current enable . . . . . . . . . . . . . . . . 8
Resistor pull-up value selection . . . . . . . . . . . . 8
Hot swapping and capacitance buffering
application . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
8.9
Voltage level translator discussion . . . . . . . . . 12
8.9.1
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
8.9.2
Why do level translation? . . . . . . . . . . . . . . . . 12
8.10
Limitations of the FET voltage
level translator . . . . . . . . . . . . . . . . . . . . . . . . 12
8.10.1
VGSth, gate-source threshold voltage . . . . . . . 12
8.10.2
FET body diode voltage . . . . . . . . . . . . . . . . . 12
8.11
Additional system compromises . . . . . . . . . . . 13
9
Application design-in information . . . . . . . . . 13
10
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 14
11
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 14
11.1
Typical performance characteristics . . . . . . . . 16
12
Test information . . . . . . . . . . . . . . . . . . . . . . . . 17
13
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18
14
Soldering of SMD packages . . . . . . . . . . . . . . 20
14.1
Introduction to soldering . . . . . . . . . . . . . . . . . 20
14.2
Wave and reflow soldering . . . . . . . . . . . . . . . 20
14.3
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 20
14.4
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 21
15
Soldering: PCB footprints. . . . . . . . . . . . . . . . 22
16
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 24
17
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 24
18
Legal information. . . . . . . . . . . . . . . . . . . . . . . 25
18.1
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 25
18.2
18.3
18.4
19
20
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
25
26
26
27
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 1 March 2013
Document identifier: PCA9512A_PCA9512B