Data Sheet

PCA9517
Level translating I2C-bus repeater
Rev. 03 — 30 January 2007
Product data sheet
1. General description
The PCA9517 is a CMOS integrated circuit that provides level shifting between low
voltage (down to 0.9 V) and higher voltage (2.7 V to 5.5 V) I2C-bus or SMBus applications.
While retaining all the operating modes and features of the I2C-bus system during the
level shifts, it also permits extension of the I2C-bus by providing bidirectional buffering for
both the data (SDA) and the clock (SCL) lines, thus enabling two buses of 400 pF. Using
the PCA9517 enables the system designer to isolate two halves of a bus for both voltage
and capacitance. The SDA and SCL pins are over voltage tolerant and are
high-impedance when the PCA9517 is unpowered.
The 2.7 V to 5.5 V bus B-side drivers behave much like the drivers on the PCA9515A
device, while the adjustable voltage bus A-side drivers drive more current and eliminate
the static offset voltage. This results in a LOW on the B-side translating into a nearly 0 V
LOW on the A-side which accommodates smaller voltage swings of lower voltage logic.
The static offset design of the B-side PCA9517 I/O drivers prevent them from being
connected to another device that has rise time accelerator including the PCA9510,
PCA9511, PCA9512, PCA9513, PCA9514, PCA9515A, PCA9516A, PCA9517 (B-side),
or PCA9518. The A-side of two or more PCA9517s can be connected together, however,
to allow a star topography with the A-side on the common bus, and the A-side can be
connected directly to any other buffer with static or dynamic offset voltage. Multiple
PCA9517s can be connected in series, A-side to B-side, with no build-up in offset voltage
with only time of flight delays to consider.
The PCA9517 drivers are not enabled unless VCCA is above 0.8 V and VCC is above 2.5 V.
The EN pin can also be used to turn the drivers on and off under system control. Caution
should be observed to only change the state of the enable pin when the bus is idle.
The output pull-down on the B-side internal buffer LOW is set for approximately 0.5 V,
while the input threshold of the internal buffer is set about 70 mV lower (0.43 V). When the
B-side I/O is driven LOW internally, the LOW is not recognized as a LOW by the input.
This prevents a lock-up condition from occurring. The output pull-down on the A-side
drives a hard LOW and the input level is set at 0.3VCCA to accommodate the need for a
lower LOW level in systems where the low voltage side supply voltage is as low as 0.9 V.
2. Features
n 2 channel, bidirectional buffer isolates capacitance and allows 400 pF on either side of
the device
n Voltage level translation from 0.9 V to 5.5 V and from 2.7 V to 5.5 V
n Footprint and functional replacement for PCA9515/15A
n I2C-bus and SMBus compatible
PCA9517
NXP Semiconductors
Level translating I2C-bus repeater
n
n
n
n
n
n
n
n
n
n
Active HIGH repeater enable input
Open-drain input/outputs
Lock-up free operation
Supports arbitration and clock stretching across the repeater
Accommodates Standard mode and Fast mode I2C-bus devices and multiple masters
Powered-off high-impedance I2C-bus pins
A-side operating supply voltage range of 0.9 V to 5.5 V
B-side operating supply voltage range of 2.7 V to 5.5 V
5 V tolerant I2C-bus and enable pins
0 Hz to 400 kHz clock frequency (the maximum system operating frequency may be
less than 400 kHz because of the delays added by the repeater).
n ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
n Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
n Packages offered: SO8 and TSSOP8
3. Ordering information
Table 1.
Ordering information
Tamb = −40 °C to +85 °C
Type number
Topside
mark
PCA9517D
PCA9517 SO8
PCA9517DP
[1]
9517
Package
Name
TSSOP8[1]
Description
Version
plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
plastic thin shrink small outline package; 8 leads; body width 3 mm
SOT505-1
Also known as MSOP8
4. Functional diagram
VCCA
VCCB
PCA9517
SDAB
SDAA
SCLB
SCLA
VCCB
pull-up
resistor
EN
002aac200
GND
Fig 1. Functional diagram of PCA9517
PCA9517_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 30 January 2007
2 of 19
PCA9517
NXP Semiconductors
Level translating I2C-bus repeater
5. Pinning information
5.1 Pinning
VCCA
1
8
VCCB
SCLA
2
7
SCLB
SDAA
3
6
SDAB
GND
4
5
EN
PCA9517D
VCCA
1
8
VCCB
SCLA
2
7
SCLB
SDAA
3
6
SDAB
GND
4
5
EN
PCA9517DP
002aac199
002aac198
Fig 2. Pin configuration for SO8
Fig 3. Pin configuration for TSSOP8
(MSOP8)
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
VCCA
1
A-side supply voltage (0.9 V to 5.5 V)
SCLA
2
serial clock A-side bus
SDAA
3
serial data A-side bus
GND
4
supply ground (0 V)
EN
5
active HIGH repeater enable input
SDAB
6
serial data B-side bus
SCLB
7
serial clock B-side bus
VCCB
8
B-side supply voltage (2.7 V to 5.5 V)
6. Functional description
Refer to Figure 1 “Functional diagram of PCA9517”.
The PCA9517 enables I2C-bus or SMBus translation down to VCCA as low as 0.9 V
without degradation of system performance. The PCA9517 contains two bidirectional
open-drain buffers specifically designed to support up-translation/down-translation
between the low voltage (as low as 0.9 V) and a 3.3 V or 5 V I2C-bus or SMBus. All inputs
and I/Os are overvoltage tolerant to 5.5 V even when the device is unpowered (VCCB
and/or VCCA = 0 V). The PCA9517 includes a power-up circuit that keeps the output
drivers turned off until VCCB is above 2.5 V and the VCCA is above 0.8 V. VCCB and VCCA
can be applied in any sequence at power-up. After power-up and with the enable (EN)
HIGH, a LOW level on the A-side (below 0.3VCCA) turns the corresponding B-side driver
(either SDA or SCL) on and drives the B-side down to about 0.5 V. When the A-side rises
above 0.3VCCA the B-side pull-down driver is turned off and the external pull-up resistor
pulls the pin HIGH. When the B-side falls first and goes below 0.3VCCB the A-side driver is
turned on and the A-side pulls down to 0 V. The B-side pull-down is not enabled unless
the B-side voltage goes below 0.4 V. If the B-side low voltage does not go below 0.5 V, the
A-side driver will turn off when the B-side voltage is above 0.7VCCB. If the B-side low
voltage goes below 0.4 V, the B-side pull-down driver is enabled and the B-side will only
PCA9517_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 30 January 2007
3 of 19
PCA9517
NXP Semiconductors
Level translating I2C-bus repeater
be able to rise to 0.5 V until the A-side rises above 0.3VCCA, then the B-side will continue
to rise being pulled up by the external pull-up resistor. The VCCA is only used to provide
the 0.3VCCA reference to the A-side input comparators and for the power good detect
circuit. The PCA9517 logic and all I/Os are powered by the VCCB pin.
6.1 Enable
The EN pin is active HIGH with an internal pull-up to VCCB and allows the user to select
when the repeater is active. This can be used to isolate a badly behaved slave on
power-up until after the system power-up reset. It should never change state during an
I2C-bus operation because disabling during a bus operation will hang the bus and
enabling part way through a bus cycle could confuse the I2C-bus parts being enabled.
The enable pin should only change state when the global bus and the repeater port are in
an idle state to prevent system failures.
6.2 I2C-bus systems
As with the standard I2C-bus system, pull-up resistors are required to provide the logic
HIGH levels on the buffered bus (standard open-collector configuration of the I2C-bus).
The size of these pull-up resistors depends on the system, but each side of the repeater
must have a pull-up resistor. This part designed to work with Standard mode and Fast
mode I2C-bus devices in addition to SMBus devices. Standard mode I2C-bus devices only
specify 3 mA output drive; this limits the termination current to 3 mA in a generic I2C-bus
system where Standard mode devices and multiple masters are possible. Under certain
conditions higher termination currents can be used.
Please see Application Note AN255, I2C/SMBus Repeaters, Hubs and Expanders for
additional information on sizing resistors and precautions when using more than one
PCA9517 in a system or using the PCA9517 in conjunction with other bus buffers.
PCA9517_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 30 January 2007
4 of 19
PCA9517
NXP Semiconductors
Level translating I2C-bus repeater
7. Application design-in information
A typical application is shown in Figure 4. In this example, the system master is running
on a 3.3 V I2C-bus while the slave is connected to a 1.2 V bus. Both buses run at 400 kHz.
Master devices can be placed on either bus.
3.3 V
1.2 V
10 kΩ
10 kΩ
10 kΩ
10 kΩ
VCCB
VCCA
SDA
SDAB
SDAA
SDA
SCL
SCLB
SCLA
SCL
BUS
MASTER
400 kHz
PCA9517
SLAVE
400 kHz
EN
bus B
bus A
002aac201
Fig 4. Typical application
The PCA9517 is 5 V tolerant, so it does not require any additional circuitry to translate
between 0.9 V to 5.5 V bus voltages and 2.7 V to 5.5 V bus voltages.
When the A-side of the PCA9517 is pulled LOW by a driver on the I2C-bus, a comparator
detects the falling edge when it goes below 0.3VCCA and causes the internal driver on the
B-side to turn on, causing the B-side to pull down to about 0.5 V. When the B-side of the
PCA9517 falls, first a CMOS hysteresis type input detects the falling edge and causes the
internal driver on the A-side to turn on and pull the A-side pin down to ground. In order to
illustrate what would be seen in a typical application, refer to Figure 8 and Figure 9. If the
bus master in Figure 4 were to write to the slave through the PCA9517, waveforms shown
in Figure 8 would be observed on the A bus. This looks like a normal I2C-bus transmission
except that the HIGH level may be as low as 0.9 V, and the turn on and turn off of the
acknowledge signals are slightly delayed.
On the B bus side of the PCA9517, the clock and data lines would have a positive offset
from ground equal to the VOL of the PCA9517. After the 8th clock pulse, the data line will
be pulled to the VOL of the slave device which is very close to ground in this example. At
the end of the acknowledge, the level rises only to the LOW level set by the driver in the
PCA9517 for a short delay while the A bus side rises above 0.3VCCA then it continues
HIGH. It is important to note that any arbitration or clock stretching events require that the
LOW level on the B bus side at the input of the PCA9517 (VIL) be at or below 0.4 V to be
recognized by the PCA9517 and then transmitted to the A bus side.
Multiple PCA9517 A-sides can be connected in a star configuration (Figure 5), allowing all
nodes to communicate with each other.
Multiple PCA9517s can be connected in series (Figure 6) as long as the A-side is
connected to the B-side. I2C-bus slave devices can be connected to any of the bus
segments. The number of devices that can be connected in series is limited by repeater
delay/time-of-flight considerations on the maximum bus speed requirements.
PCA9517_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 30 January 2007
5 of 19
PCA9517
NXP Semiconductors
Level translating I2C-bus repeater
VCCA
VCCB
10 kΩ
10 kΩ
10 kΩ
10 kΩ
VCCA
VCCB
SDA
SDAA
SDAB
SDA
SCL
SCLA
SCLB
SCL
BUS
MASTER
PCA9517
SLAVE
400 kHz
EN
10 kΩ
10 kΩ
VCCA
VCCB
SDAA
SDAB
SDA
SCLA
SCLB
SCL
PCA9517
SLAVE
400 kHz
EN
10 kΩ
10 kΩ
VCCA
VCCB
SDAA
SDAB
SDA
SCLA
SCLB
SCL
PCA9517
SLAVE
400 kHz
EN
002aac202
Fig 5. Typical star application
VCC
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
SDA
SDAA
SDAB
SDAA
SDAB
SDAA
SDAB
SDA
SCL
SCLA
SCLB
SCLA
SCLB
SCLA
SCLB
SCL
BUS
MASTER
PCA9517
EN
PCA9517
EN
PCA9517
SLAVE
400 kHz
EN
002aac203
Fig 6. Typical series application
PCA9517_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 30 January 2007
6 of 19
PCA9517
NXP Semiconductors
Level translating I2C-bus repeater
CARD 1
VCCA
CARD 2
RPU
VCCB
RPU
10 kΩ
VCCA
10 kΩ
10 kΩ
(optional)
VCCB
75 Ω
75 Ω
SDAA
SCLA
SDAB
SCLB
EN
MASTER
OR
SLAVE
GND
002aac637
Fig 7. Typical application of PCA9517 driving a short cable
9th clock pulse
acknowledge
SCL
SDA
002aac775
Fig 8. Bus A (0.9 V to 5.5 V bus) waveform
9th clock pulse
acknowledge
SCL
SDA
VOL of PCA9517
002aac205
VOL of slave
Fig 9. Bus B (2.7 V to 5.5 V) waveform
PCA9517_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 30 January 2007
7 of 19
PCA9517
NXP Semiconductors
Level translating I2C-bus repeater
8. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VCCB
supply voltage, B-side bus
2.7 V to 5.5 V
−0.5
+7
V
VCCA
supply voltage, A-side bus
adjustable
−0.5
+7
V
Vbus
voltage on I2C-bus B-side, or enable (EN)
−0.5
+7
V
I
DC current
-
50
mA
Ptot
total power dissipation
-
100
mW
Tstg
storage temperature
−55
+125
°C
Tamb
ambient temperature
−40
+85
°C
Tj
junction temperature
-
+125
°C
any pin
operating in free air
PCA9517_3
Product data sheet
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Rev. 03 — 30 January 2007
8 of 19
PCA9517
NXP Semiconductors
Level translating I2C-bus repeater
9. Static characteristics
Table 4.
Static characteristics
VCC = 2.7 V to 5.5 V; GND = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2.7
-
5.5
V
0.9
-
5.5
V
-
-
1
mA
Supplies
VCCB
supply voltage, B-side bus
VCCA
supply voltage, A-side bus
ICC(VCCA)
supply current on pin VCCA
ICCH
HIGH-state supply current
both channels HIGH;
VCC = 5.5 V;
SDAn = SCLn = VCC
-
1.5
5
mA
ICCL
LOW-state supply current
both channels LOW;
VCC = 5.5 V;
one SDA and one SCL = GND;
other SDA and SCL open
-
1.5
5
mA
ICCAc
quiescent supply current in
contention
VCC = 5.5 V;
SDAn = SCLn = VCC
-
1.5
5
mA
0.7VCCB
-
5.5
V
−0.5
-
+0.3VCCB
V
−0.5
0.4
-
V
[1]
Input and output SDAB and SCLB
VIH
HIGH-level input voltage
VIL
LOW-level input voltage
VILc
LOW-level input voltage contention
[2]
VIK
input clamping voltage
II = −18 mA
-
-
−1.2
V
ILI
input leakage current
VI = 3.6 V
-
-
±1
µA
IIL
LOW-level input current
SDA, SCL; VI = 0.2 V
-
-
10
µA
VOL
LOW-level output voltage
IOL = 100 µA or 6 mA
0.47
0.52
0.6
V
VOL−VILc
LOW-level input voltage below
output LOW-level voltage
guaranteed by design
-
-
70
mV
ILOH
HIGH-level output leakage current
VO = 3.6 V
-
-
10
µA
Cio
input/output capacitance
VI = 3 V or 0 V; VCC = 3.3 V
-
6
7
pF
VI = 3 V or 0 V; VCC = 0 V
-
6
7
pF
0.7VCCA
-
5.5
V
−0.5
-
+0.3VCCA
V
Input and output SDAA and SCLA
VIH
HIGH-level input voltage
VIL
LOW-level input voltage
[3]
VIK
input clamping voltage
II = −18 mA
-
-
−1.2
V
ILI
input leakage current
VI = 3.6 V
-
-
±1
µA
IIL
LOW-level input current
SDA, SCL; VI = 0.2 V
-
-
10
µA
VOL
LOW-level output voltage
IOL = 6 mA
-
0.1
0.2
V
ILOH
HIGH-level output leakage current
VO = 3.6 V
-
-
10
µA
Cio
input/output capacitance
VI = 3 V or 0 V; VCC = 3.3 V
-
6
7
pF
VI = 3 V or 0 V; VCC = 0 V
-
6
7
pF
PCA9517_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 30 January 2007
9 of 19
PCA9517
NXP Semiconductors
Level translating I2C-bus repeater
Table 4.
Static characteristics …continued
VCC = 2.7 V to 5.5 V; GND = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
−0.5
-
+0.3VCCB
V
0.7VCCB
-
5.5
V
-
−10
−30
µA
−1
-
+1
µA
-
6
7
pF
Enable
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
IIL(EN)
LOW-level input current on pin EN
ILI
input leakage current
Ci
input capacitance
VI = 0.2 V, EN; VCC = 3.6 V
VI = 3.0 V or 0 V
[1]
LOW-level supply voltage.
[2]
VIL specification is for the first LOW level seen by the SDAB/SCLB lines. VILc is for the second and subsequent LOW levels seen by the
SDAB/SCLB lines.
[3]
VIL for A-side with envelope noise must be below 0.3VCCA for stable performance.
10. Dynamic characteristics
Table 5.
Dynamic characteristics
VCC = 2.7 V to 5.5 V; GND = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.[1][2]
Symbol
Parameter
Min
Typ[3]
Max
Unit
[4]
100
170
250
ns
[5]
30
80
110
ns
10
66
300
ns
10
20
30
ns
1
77
105
ns
Conditions
tPLH
LOW-to-HIGH propagation delay
B-side to A-side; Figure 12
tPHL
HIGH-to-LOW propagation delay
B-side to A-side; Figure 10
VCCA ≤ 2.7 V
VCCA ≥ 3 V
tt(LH)
LOW-to-HIGH transition time
A-side; Figure 10
tt(HL)
HIGH-to-LOW transition time
A-side; Figure 10
VCCA ≤ 2.7 V
[5]
VCCA ≥ 3 V
LOW-to-HIGH propagation delay
tPLH
20
70
175
ns
A-side to B-side; Figure 11
[6]
25
53
110
ns
[6]
60
79
230
ns
120
140
170
ns
tPHL
HIGH-to-LOW propagation delay
A-side to B-side; Figure 11
tt(LH)
LOW-to-HIGH transition time
B-side; Figure 11
tt(HL)
HIGH-to-LOW transition time
B-side; Figure 11
set-up time
tsu
hold time
th
30
48
90
ns
EN HIGH before START condition
[7]
100
-
-
ns
EN HIGH after STOP condition
[7]
100
-
-
ns
[1]
Times are specified with loads of 1.35 kΩ pull-up resistance and 57 pF load capacitance on the B-side, and 167 Ω pull-up resistance
and 57 pF load capacitance on the A-side. Different load resistance and capacitance will alter the RC time constant, thereby changing
the propagation delay and transition times.
[2]
Pull-up voltages are VCCA on the A-side and VCCB on the B-side.
[3]
Typical values were measured with VCCA = 3.3 V at Tamb = 25 °C, unless otherwise noted.
[4]
The tPLH delay data from B-side to A-side is measured at 0.5 V on the B-side to 0.5VCCA on the A-side when VCCA is less than 2 V, and
1.5 V on the A-side if VCCA is greater than 2 V.
[5]
Typical value measured with VCCA = 2.7 V at Tamb = 25 °C.
[6]
The proportional delay data from A-side to B-side is measured at 0.3VCCA on the A-side to 1.5 V on the B-side.
[7]
The enable pin, EN, should only change state when the global bus and the repeater port are in an idle state.
PCA9517_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 30 January 2007
10 of 19
PCA9517
NXP Semiconductors
Level translating I2C-bus repeater
10.1 AC waveforms
3.0 V
input
1.5 V
VCCA
1.5 V
input
0.3VCCA
0.3VCCA
0.1 V
tPHL
80 %
output
tPHL
tPLH
0.6 V
20 %
tt(HL)
0.6 V
20 %
1.2 V
80 %
3.0 V
80 %
1.5 V
20 %
1.5 V
20 %
output
tt(LH)
tPLH
VOL
tt(HL)
tt(LH)
002aac207
Fig 10. Propagation delay and transition times;
B-side to A-side
80 %
002aac208
Fig 11. Propagation delay and transition times;
A-side to B-side
input
SDAB, SCLB
0.5 V
output
SCLA, SDAA
50 % if VCCA is less than 2 V
1.5 V if VCCA is greater than 2 V
tPLH
002aac209
Fig 12. Propagation delay
11. Test information
VCC(B)
VCC(B)
VCC(A)
PULSE
GENERATOR
VI
RL
VO
DUT
CL
RT
002aab649
RL = load resistor; 1.35 kΩ on B-side; 167 Ω on A-side (0.9 V to 2.7 V) and 450 Ω on A-side
(3.0 V to 5.5 V).
CL = load capacitance includes jig and probe capacitance; 57 pF
RT = termination resistance should be equal to Zo of pulse generators
Fig 13. Test circuit for open-drain outputs
PCA9517_3
Product data sheet
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Rev. 03 — 30 January 2007
11 of 19
PCA9517
NXP Semiconductors
Level translating I2C-bus repeater
12. Package outline
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
D
E
A
X
c
y
HE
v M A
Z
5
8
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
4
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
inches
0.069
0.010 0.057
0.004 0.049
0.01
0.019 0.0100
0.014 0.0075
0.20
0.19
0.16
0.15
0.05
0.01
0.01
0.004
0.028
0.012
0.244
0.039 0.028
0.041
0.228
0.016 0.024
θ
8o
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT96-1
076E03
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
Fig 14. Package outline SOT96-1 (SO8)
PCA9517_3
Product data sheet
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Rev. 03 — 30 January 2007
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TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm
D
E
SOT505-1
A
X
c
y
HE
v M A
Z
5
8
A2
pin 1 index
(A3)
A1
A
θ
Lp
L
1
4
detail X
e
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(2)
e
HE
L
Lp
v
w
y
Z(1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.45
0.25
0.28
0.15
3.1
2.9
3.1
2.9
0.65
5.1
4.7
0.94
0.7
0.4
0.1
0.1
0.1
0.70
0.35
6°
0°
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-04-09
03-02-18
SOT505-1
Fig 15. Package outline SOT505-1 (TSSOP8)
PCA9517_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 30 January 2007
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PCA9517
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13. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus PbSn soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
PCA9517_3
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Rev. 03 — 30 January 2007
14 of 19
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13.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 16) than a PbSn process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 6 and 7
Table 6.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 7.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 16.
PCA9517_3
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Rev. 03 — 30 January 2007
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maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 16. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
14. Abbreviations
Table 8.
Abbreviations
Acronym
Description
CDM
Charged Device Model
CMOS
Complementary Metal Oxide Silicon
ESD
ElectroStatic Discharge
HBM
Human Body Model
I2C-bus
Inter Integrated Circuit bus
MM
Machine Model
SMBus
System Management Bus
PCA9517_3
Product data sheet
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Rev. 03 — 30 January 2007
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15. Revision history
Table 9.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCA9517_3
20070130
Product data sheet
-
PCA9517_2
Modifications:
•
The format of this data sheet has been redesigned to comply with the new identity guidelines of
NXP Semiconductors.
•
•
Legal texts have been adapted to the new company name where appropriate.
•
Table 4 “Static characteristics” added new Table note 3, and its reference in sub-section “Input
and output SDAA and SCLA”, symbol VIL.
•
•
•
•
added (new) Figure 7 “Typical application of PCA9517 driving a short cable”
Section 2 “Features”, 15th bullet item: changed “200 V MM per JESD22-A115” to “150 V MM per
JESD22-A115”
Figure 8 “Bus A (0.9 V to 5.5 V bus) waveform”: SDA signal modified
Figure 9 “Bus B (2.7 V to 5.5 V) waveform”: SDA signal modified
Table 5 “Dynamic characteristics”:
– tt(LH), A-side: changed reference to timing diagram from Figure 11 to Figure 10
– tt(HL), A-side: changed reference to timing diagram from Figure 11 to Figure 10
– tt(LH), B-side: changed reference to timing diagram from Figure 10 to Figure 11
– tt(HL), B-side: changed reference to timing diagram from Figure 10 to Figure 11
PCA9517_2
(9397 750 14918)
20060615
Product data sheet
-
PCA9517_1
PCA9517_1
(9397 750 13252)
20041005
Product data sheet
-
-
PCA9517_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 30 January 2007
17 of 19
PCA9517
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16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
17. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: [email protected]
PCA9517_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 30 January 2007
18 of 19
PCA9517
NXP Semiconductors
Level translating I2C-bus repeater
18. Contents
1
2
3
4
5
5.1
5.2
6
6.1
6.2
7
8
9
10
10.1
11
12
13
13.1
13.2
13.3
13.4
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
I2C-bus systems . . . . . . . . . . . . . . . . . . . . . . . . 4
Application design-in information . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8
Static characteristics. . . . . . . . . . . . . . . . . . . . . 9
Dynamic characteristics . . . . . . . . . . . . . . . . . 10
AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 11
Test information . . . . . . . . . . . . . . . . . . . . . . . . 11
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Introduction to soldering . . . . . . . . . . . . . . . . . 14
Wave and reflow soldering . . . . . . . . . . . . . . . 14
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 14
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 15
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17
Legal information. . . . . . . . . . . . . . . . . . . . . . . 18
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Contact information. . . . . . . . . . . . . . . . . . . . . 18
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 30 January 2007
Document identifier: PCA9517_3
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