Data Sheet

INTEGRATED CIRCUITS
PCA9559
5-bit multiplexed/1-bit latched 6-bit I2C
EEPROM DIP switch
Product data
Supersedes data of 2002 May 24
Philips
Semiconductors
2003 Jun 27
Philips Semiconductors
Product data
5-bit multiplexed/1-bit latched 6-bit
I2C EEPROM DIP switch
PCA9559
PIN CONFIGURATION
FEATURES
• 5-bit 2-to-1 multiplexer, 1-bit latch DIP switch
• 6-bit internal non-volatile register
• Internal non-volatile register programmable and readable via
I2C SCL
1
20 VCC
I2C
SDA
2
19 WP
A1
3
18 OVERRIDE_N
A0
4
17 NON_MUXED_OUT
MUX_IN A
5
16 MUX_OUT A
MUX_IN B
6
15 MUX_OUT B
MUX_IN C
7
14 MUX_OUT C
MUX_IN D
8
13 MUX_OUT D
MUX_IN E
9
12 MUX_OUT E
GND 10
11 MUX_SELECT
I2C-bus
SW00216
• Override input forces all outputs to logic 0
• 5 open drain multiplexed outputs
• 1 open drain non-multiplexed (latched) output
• 5 V and 2.5 V tolerant inputs
• Useful for ‘jumperless’ configuration of PC motherboards
• 2 address pins, allowing up to 4 devices on the I2C-bus
• ESD protection exceeds 2000 V HBM per JESD22-A114,
Figure 1. Pin configuration
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
1
I2C SCL
Serial I2C-bus clock
2
I2C SDA
Serial bi-directional I2C-bus data
3
A1 Address
A1
4
A0 Address
A0
5-9
MUX_IN A-E
10
GND
11
MUX_SELECT
Selects MUX_IN inputs or register
contents for MUX_OUT outputs
12-16
MUX_OUT E-A
Open drain multiplexed outputs
17
NON_MUXED_
OUT
Open drain outputs from
non-volatile memory
18
OVERRIDE_N
Forces all outputs to logic 0
19
WP
Non-volatile register write-protect
20
VCC
Power supply: +3.0 to +3.6 V
200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
• Latch-up testing is done to JESDEC Standard JESD78 which
exceeds 100 mA
DESCRIPTION
The PCA9559 is a 20-pin CMOS device consisting of one 6-bit
non-volatile EEPROM registers, 5 hardware pin inputs and a 5-bit
multiplexed output with one latched EEPROM bit. It is used for DIP
switch-free or jumper-less system configuration and supports Mobile
and Desktop VID Configuration, where 2 preset values (1 set of
internal non-volatile registers and 1 set of external hardware pins)
set processor voltage for operation in either performance or deep
sleep modes. The PCA9559 is also useful in server and
telecom/networking applications when used to replace DIP switches
or jumpers, since the settings can be easily changed via I2C/SMBus
without having to power down the equipment to open the cabinet.
The non-volatile memory retains the most current setting selected
before the power is turned off.
FUNCTION
External inputs to multiplexer
Ground
The PCA9559 typically resides between the CPU and Voltage
Regulator Module (VRM) when used for CPU VID (Voltage
IDentification code) configuration. It is used to bypass the
CPU-defined VID values and provide a different set of VID values to
the VRM, if an increase in the CPU voltage is desired. An increase
in CPU voltage combined with an increase in CPU frequency leads
to a performance boost of up to 7.5%. Lower CPU voltage reduces
power consumption.
The PCA9559 has 2 address pins allowing up to 4 devices to be
placed on the same I2C-bus or SMBus.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
TOPSIDE MARK
DRAWING NUMBER
20-Pin Plastic TSSOP
0 to +70 °C
PCA9559PW
PCA9559
SOT360-1
Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.
2003 Jun 27
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Philips Semiconductors
Product data
5-bit multiplexed/1-bit latched 6-bit
I2C EEPROM DIP switch
PCA9559
FUNCTIONAL DESCRIPTION
I2C INTERFACE
When the MUX_SELECT signal is logic 0, the multiplexer will select
the data from the non-volatile register to drive on the MUX_OUT
pins. When the MUX_SELECT signal is logic 1, the multiplexer will
select the MUX_IN lines to drive on the MUX_OUT pins. The
MUX_SELECT signal is also used to latch the NON_MUXED_OUT
signal which outputs data from the non-volatile register. The
NON_MUXED_OUT signal latch is transparent when MUX_SELECT
is in a logic 0 state, and will latch data when MUX_SELECT is in a
logic 1 state. When the active-LOW OVERRIDE_N signal is set to
logic 0 and the MUX_SELECT signal is at a logic 0, all outputs will
be driven to logic 0. This information is summarized in Table 1.
Communicating with this device is initiated by sending a valid
address on the I2C-bus. The address format (see FIgure 1) has 5
fixed bits and two user-programmable bits followed by a 1-bit
read/write value which determines the direction of the data transfer.
MSB
1
NON_MUXED_OUT
OUTPUT
0
All 0’s
All 0’s
1
MUX_IN
inputs
Latched
NON_MUXED_OUT 1
From non-volatile
register
From non-volatile
register
0
1
0
From nonvolatile
register
1
1
MUX_IN
inputs
1
A1
A0
R/W
HARDWARE
SELECTABLE
NOTE:
1. To ensure data integrity, the non-volatile register must be
internally write protected when VCC to the I2C-bus is powered
down or VCC to the component is dropped below normal
operating levels.
FUNCTION TABLE
0
1
Following the address and acknowledge bit are 8 data bits which,
depending on the read/write bit in the address, will read data from or
write data to the non-volatile register. Data will be written to the
register if the read/write bit is logic 0 and the WP input is logic 0.
Data will be read from the register if the bit is logic 1. The four
high-order bits are latched outputs, while the four low order bits are
multiplexed outputs (Figure 3).
The OVERRIDE_N, WP, MUX_IN, and MUX_SELECT signals have
internal pull-up resistors. See the DC and AC Characteristics for
hysteresis and signal spike suppression figures.
MUX_OUT
OUTPUTS
0
Figure 2. I2C Address Byte
The factory default for the contents of the non-volatile register are all
logic 0. These stored values can be read or written using the
I2C-bus (described in the next section).
MUX_SELECT
0
FIXED
The Write Protect (WP) input is used to control the ability to write the
contents of the 6-bit non-volatile register. If the WP signal is logic 0,
the I2C-bus will be able to write the contents of the non-volatile
register. If the WP signal is logic 1, data will not be allowed to be
written into the non-volatile register.
OVERRIDE_N
LSB
MSB
0
LSB
0
NONMUXED
DATA
MUX
MUX
MUX
MUX
DATA E DATA D DATA C DATA B
MUX
DATA A
Figure 3. I2C Data Byte
NOTE:
1. NON_MUXED_OUT state will be the value present on the output
at the time of the MUX_SELECT input transitioned from a logic 0
to a logic 1 state.
POWER-ON RESET (POR)
When power is applied to VCC, an internal power-on reset holds the
PCA9559 in a reset state until VCC has reached VPOR. At that point,
the reset condition is released and the PCA9559 volatile registers
and I2C/SMBus state machine will initialize to their default states.
The MUX_OUT and NON_MUXED_OUT pin values depend on:
- the OVERRIDE # and MUX_SELECT logic levels
- the previously stored values in the EEPROM register/current
MUX_IN pin values as shown in the Function Table.
2003 Jun 27
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Philips Semiconductors
Product data
5-bit multiplexed/1-bit latched 6-bit
I2C EEPROM DIP switch
PCA9559
BLOCK DIAGRAM
PCA9559
10-30 kΩ
11
18
MUX_SELECT
OVERRIDE_N
4
A0
3
A1
6-BIT EEPROM
100-150 kΩ
LATCH
SCL
INPUT
FILTER
SDA
2
VDD
20
POWER-ON
RESET
NMO
2
I C/SMBus CONTROL LOGIC
1
SELECT
17
NON_MUXED_OUT
0
16
MUX_OUT A
GND
10
WRITE
OE
5-BIT 2 to 1 DEMULTIPLEXER
19
PROTECT
5
MUX_IN A
6
7
8
15
MUX_OUT B
MUX_IN B
MUX_OUT C
14
13
MUX_OUT D
MUX_OUT E
12
MUX_IN C
MUX_IN D
1
9
MUX_IN E
10-30 kΩ
SW00400
Figure 4. Block diagram
2003 Jun 27
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Philips Semiconductors
Product data
5-bit multiplexed/1-bit latched 6-bit
I2C EEPROM DIP switch
PCA9559
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0 V)
SYMBOL
VCC
VI
VOUT
Tstg
PARAMETER
CONDITIONS
DC supply voltage
RATING
UNIT
-0.5 to +4.6
V
DC input voltage
Note 3
-1.5 to VCC +1.5
V
DC output voltage
Note 3
-0.5 to VCC +0.5
-60 to +150
V
Storage temperature range
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
LIMITS
MIN
MAX
UNIT
VCC
DC supply voltage
3.0
3.6
V
VIL
LOW-level input voltage
SCL, SDA
IOL= 3 mA
-0.5
0.9
V
VIH
HIGH-level input voltage
SCL, SDA
IOL= 3 mA
2.7
4.0
V
IOL= 3 mA
—
0.4
IOL= 6 mA
—
0.6
VOL
LOW-level output voltage
SCL, SDA
V
VIL
LOW-level input voltage
OVERRIDE_N,
MUX_IN,
MUX_SELECT
-0.5
0.8
V
VIH
HIGH-level input voltage
OVERRIDE_N,
MUX_IN,
MUX_SELECT
2.0
4.0
V
IOL
LOW-level output current
MUX_OUT,
NON_MUXED_OUT
—
8
mA
IOH
HIGH-level output current
MUX_OUT,
NON_MUXED_OUT
—
100
µA
dt/dv
Input transition rise or fall time
0
10
ns/V
Tamb
Operating temperature
0
70
°C
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Philips Semiconductors
Product data
5-bit multiplexed/1-bit latched 6-bit
I2C EEPROM DIP switch
PCA9559
DC CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITION
MIN.
TYP.
MAX.
UNIT
Supply
VCC
Supply voltage
3
—
3.8
V
ICCL
Supply current
Operating mode ALL inputs = 0 V
—
—
10
mA
ICCH
Supply current
Operating mode ALL inputs = VCC
—
—
600
µA
VPOR
Power-on reset voltage
no load; VI = VCC or GND
—
1.9
2.6
V
Input SCL: Input/Output SDA
VIL
LOW-level input voltage
-0.5
—
0.8
V
VIH
HIGH-level input voltage
2
—
VCC + 0.5
V
IOL
LOW-level output curret
VOL = 0.4 V
3
—
—
mA
IOL
LOW-level output curret
VOL = 0.6 V
6
—
—
mA
IIH
Leakage current HIGH
VI = VCC
-1.5
—
-12
µA
IIL
Leakage current LOW
VI = GND
-7
—
-32
µA
CI
Input capacitance
—
—
10
pF
OVERRIDE_N, WP, MUX_SELECT
IIH
Leakage current HIGH
VI = VCC
-20
—
-100
µA
IIL
Leakage current LOW
VI = GND
-86
—
-267
µA
CI
Input capacitance
—
—
10
pF
MUX_IN A ⇒ E
IIH
Leakage current HIGH
VI = VCC
-0.166
—
-0.75
mA
IIL
Leakage current LOW
VI = GND
-0.72
—
-2
mA
CI
Input capacitance
—
—
10
pF
1
µA
A0, A1 Inputs
IIH
Leakage current HIGH
VI = VCC
-1
—
IIL
Leakage current LOW
VI = GND
-1
—
1
µA
CI
Input capacitance
—
—
10
pF
MUX_OUT E ⇒ A
VOL
LOW-level output curret
IOL = 100 µA
—
—
0.4
V
VOL
LOW-level output curret
IOL = 2 mA
—
—
0.7
V
NON_MUXED_OUT
VOL
LOW-level output curret
IOL = 100 µA
—
—
0.4
V
VOL
LOW-level output curret
IOL = 2 mA
—
—
0.7
V
NOTES:
1. VHYS is the hysteresis of Schmitt-Trigger inputs
NON-VOLATILE STORAGE SPECIFICATIONS
PARAMETER
SPECIFICATION
Memory cell data retention
10 years min
Number of memory cell write cycles
100,00 cycles min
Application Note AN250 I 2C DIP Switch provides additional information on memory cell data retention and the minimum number of write cycles.
2003 Jun 27
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Philips Semiconductors
Product data
5-bit multiplexed/1-bit latched 6-bit
I2C EEPROM DIP switch
PCA9559
AC CHARACTERISTICS
SYMBOL
LIMITS
PARAMETER
MIN.
TYP.
MAX.
UNIT
MUX_IN ⇒ MUX_OUT
tPLH
LOW-to-HIGH transition time
—
28
37
ns
tPHL
HIGH-to-LOW transition time
—
16
21
ns
Select ⇒ MUX_OUT
tPLH
LOW-to-HIGH transition time
—
30
39
ns
tPHL
HIGH-to-LOW transition time
—
17
22
ns
OVERRIDE_N ⇒ NON-MUXED_OUT
tPLH
LOW-to-HIGH transition time
—
34
43
ns
tPHL
HIGH-to-LOW transition time
—
19
25
ns
OVERRIDE_N ⇒ MUX_OUT
tPLH
LOW-to-HIGH transition time
—
31
41
ns
tPHL
HIGH-to-LOW transition time
—
21
27
ns
tR
Output rise time
1.0
—
3
ns/V
tF
Output fall time
1.0
—
3
ns/V
PF
Pull-up resistor for outputs
1.0
—
—
ns/V
CL
Test load capacitance on outputs
—
—
—
pF
tSCL
SCL clock frequency
10
—
400
kHz
tBUF
Bus free time between a STOP and a START condition
1.3
—
—
µs
Hold time (repeated) START condition. After this period, the first
clock pulse is generated
600
—
—
ns
I2C-bus
tHD:STA
tLOW
LOW period of SCL clock
1.3
—
—
µs
tHIGH
HIGH period of SCL clock
600
—
-12
ns
600
—
-32
ns
0
—
10
ns
100
—
-100
ns
tSU:STA
Set-up time for a repeated START condition
tHD:DAT
Data hold time
tSU:DAT
Data set-up time
tSP
Data spike time
0
—
50
ns
Set-up time for STOP condition
600
—
10
ns
tR
Rise time for both SDA and SCL signals (10 - 400 pF bus)
20
—
300
ns
tI
tSU:STO
Fall time for both SDA and SCL signals (10 - 400 pF bus)
20
—
300
ns
CL
Capacitive load for each bus line
—
—
400
pF
TW
Write cycle time1
—
15
—
ms
NOTE:
1. WRITE CYCLE time can only be measured indirectly during the write cycle. During this time, the device will not acknowledge its I2C Address.
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Philips Semiconductors
Product data
5-bit multiplexed/1-bit latched 6-bit
I2C EEPROM DIP switch
PCA9559
SDA
tBUF
tR
tLOW
tF
tHD;STA
tSP
SCL
tHD;STA
P
tSU;STA
tHD;DAT
S
tHIGH
tSU;DAT
tSU;STO
Sr
P
SU00645
Figure 5. Definition of timing
VCC
MUX INPUT
VM
tPLZ
tPHL
MUX OUTPUT
VO
VM
VIN
VO
VOUT
PULSE
GENERATOR
RL
D.U.T.
VM
RT
VOL + 0.3V
CL
VOL
Test Circuit for Open Drain Outputs
SW00500
DEFINITIONS
Figure 6. Open drain output enable and disable times
RL = Load resistor; 1 kΩ
CL = Load capacitance includes jig and probe capacitance;
10 pF
RT = Termination resistance should be equal to ZOUT of
pulse generators.
SW00510
Figure 7. Test circuit
2003 Jun 27
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Philips Semiconductors
Product data
5-bit multiplexed/1-bit latched 6-bit
I2C EEPROM DIP switch
PCA9559
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
2003 Jun 27
9
SOT360-1
Philips Semiconductors
Product data
5-bit multiplexed/1-bit latched 6-bit
I2C EEPROM DIP switch
REVISION HISTORY
Rev
Date
_4
20030627
PCA9559
Description
Product data (9397 750 11675); ECN 853-2181 29936 dated 19 May 2003.
Supersedes data of 2002 May 24 (9397 750 09891).
Modifications:
• Update marketing information.
• Increase number of write cycles from 3K to 100K.
_3
2003 Jun 27
20020524
Product data (9397 750 09891); ECN 853-2181 28310 of 24 May 2002.
10
Philips Semiconductors
Product data
5-bit multiplexed/1-bit latched 6-bit
I2C EEPROM DIP switch
PCA9559
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent
to use the components in the I2C system provided the system conforms to the
I2C specifications defined by Philips. This specification can be ordered using the
code 9398 393 40011.
Data sheet status
Level
Data sheet status[1]
Product
status[2] [3]
Definitions
I
Objective data
Development
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described
or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated
via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys
no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent,
copyright, or mask work right infringement, unless otherwise specified.
 Koninklijke Philips Electronics N.V. 2003
All rights reserved. Printed in U.S.A.
Contact information
For additional information please visit
http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
Date of release: 06-03
For sales offices addresses send e-mail to:
[email protected]
Document order number:
Philips
Semiconductors
2003 Jun 27
11
9397 750 11675
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