PCA9509P
Low power level translating I2C-bus/SMBus repeater
Rev. 3 — 19 July 2013
Product data sheet
1. General description
The PCA9509P is a level translating I2C-bus/SMBus repeater with two voltage supplies
that enables processor low voltage 2-wire serial bus to interface with standard I2C-bus or
SMBus I/O. While retaining all the operating modes and features of the I2C-bus system
during the level shifts, it also permits extension of the I2C-bus by providing bidirectional
buffering for both the data (SDA) and the clock (SCL) lines, thus enabling the I2C-bus or
SMBus maximum capacitance of 400 pF on the higher voltage side. Port A allows a
voltage range from 0.8 V to 1.5 V and is overvoltage tolerant. Port B allows a voltage
range from 2.3 V to 5.5 V and is overvoltage tolerant. Both port A and port B SDA and
SCL pins are high-impedance when the PCA9509P is unpowered.
The bus port B drivers are compliant with SMBus I/O levels, while port A uses an offset
LOW which prevents bus lock-up and allows the bidirectional nature of the device. The
output pull-down on the port A internal buffer LOW is set for approximately 0.2VCC(A),
while the input threshold of the internal buffer is set about 0.1VCC(A) lower than that of the
output voltage LOW. When the port A I/O is driven LOW internally, the LOW is not
recognized as a LOW by the input. This prevents a lock-up condition from occurring. The
output pull-down on the port B drives a hard LOW and the input level is set at 0.3 of
SMBus or I2C-bus voltage level which enables port B to connect to any other I2C-bus
devices or buffer.
The PCA9509P drivers are not enabled unless VCC(A) is above 0.7 V and VCC(B) is above
1.7 V. The enable (EN) pin can also be used to turn on and turn off the drivers under
system control. Caution should be observed to change only the state of the EN pin when
the bus is idle.
The PCA9509P is the same as the PCA9509A but without the port A internal current
source to allow high value pull-up resistors to reduce current consumption in portable
applications.
PCA9509P
NXP Semiconductors
Low power level translating I2C-bus/SMBus repeater
1.1 Selection recommendations
The PCA9509P should be used if an external A-port pull-up resistor is required to adjust
current for noise margin considerations or to reduce operating current consumption. See
Table 1 for comparison.
Table 1.
Device selection recommendation
Concern
Recommended device
PCA9509
PCA9509A
PCA9509P
A-port — lowest voltage
1.0 V
0.85 V
0.85 V
A-port — current source[1]
yes — 1 mA
yes — 270 A
no — external pull-up
< 6.1 mA
< 1.9 mA
< 0.95 mA
< 2 mA
< 22 A max.
< 22 A max.
operating
current[2]
standby current EN = LOW
[1]
The PCA9509 current mirrors do not shut down when the device is disabled allowing instant turn-on, but at
the cost of the higher standby current. The PCA9509A and PCA9509P current mirrors are turned off when
disabled for lowest standby power consumption, but sufficient delay (10 s) after enable is needed before
resuming operation.
[2]
Operating currents do not include the current consumed by the external pull-ups on B-port or the external
pull-ups on the A-port of the PCA9509P.
2. Features and benefits
Bidirectional buffer isolates capacitance and allows 400 pF on port B of the device
Voltage level translation from port A (0.8 V to 1.5 V) to port B (2.3 V to 5.5 V)
No internal current source on A port to reduce current consumption for portable
applications
Active HIGH enable input disables current mirrors to reduce standby power
Open-drain inputs/outputs
Lock-up free operation
Supports arbitration and clock stretching across the repeater
Accommodates Standard-mode and Fast-mode I2C-bus devices and multiple masters
Powered-off high-impedance I2C-bus pins
Operating supply voltage range of 0.8 V to 1.5 V on port A, 2.3 V to 5.5 V on port B
All pins are 5 V tolerant with respect to ground pin
0 Hz to 400 kHz clock frequency
Remark: The maximum system operating frequency may be less than 400 kHz
because of the delays added by the repeater.
ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Packages offered: TSSOP8, XQFN8
PCA9509P
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 19 July 2013
© NXP B.V. 2013. All rights reserved.
2 of 25
PCA9509P
NXP Semiconductors
Low power level translating I2C-bus/SMBus repeater
3. Ordering information
Table 2.
Ordering information
Type number
Topside
mark
Package
Name
Description
Version
PCA9509PDP
9509P
TSSOP8
plastic thin shrink small outline package; 8 leads; body width 3 mm
SOT505-1
PCA950PGM
9PX[1]
XQFN8
plastic, extremely thin quad flat package; no leads; 8 terminals;
body 1.6 1.6 0.5 mm
SOT902-2
[1]
‘X’ changes based on date code.
3.1 Ordering options
Table 3.
Ordering options
Type number
Orderable
part number
Package
Packing method
Minimum
order quantity
Temperature
PCA9509PDP
PCA9509PDP,118
TSSOP8
Reel 13” Q1/T1
*standard mark SMD
2500
Tamb = 40 C to +85 C
PCA950PGM
PCA9509PGM,125
XQFN8
Reel 7” Q3/T4
*standard mark
4000
Tamb = 40 C to +85 C
4. Functional diagram
VCC(A)
VCC(B)
PCA9509P
A1
B1
A2
B2
EN
002aag171
GND
Fig 1.
PCA9509P
Product data sheet
Functional diagram of PCA9509P
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Rev. 3 — 19 July 2013
© NXP B.V. 2013. All rights reserved.
3 of 25
PCA9509P
NXP Semiconductors
Low power level translating I2C-bus/SMBus repeater
5. Pinning information
5.1 Pinning
PCA9509PGM
8
VCC(B)
2
7
B1
A2
3
6
B2
GND
4
5
EN
PCA9509PDP
A1
A2
Pin configuration for TSSOP8
7
B1
2
6
B2
3
5
EN
002aag174
Transparent top view
002aag172
Fig 2.
8
1
4
1
A1
VCC(A)
GND
VCC(A)
VCC(B)
terminal 1
index area
Fig 3.
Pin configuration for XQFN8
5.2 Pin description
Table 4.
Symbol
Pin
Description
VCC(A)
1
port A power supply
A1[1]
2
port A (lower voltage side)
A2[1]
3
port A (lower voltage side)
GND
4
ground (0 V)
EN
5
enable input (active HIGH)
B2[1]
6
port B (SMBus/I2C-bus side)
B1[1]
7
port B (SMBus/I2C-bus side)
VCC(B)
8
port B power supply
[1]
PCA9509P
Product data sheet
Pin description
Port A and port B can be used for either SCL or SDA.
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4 of 25
PCA9509P
NXP Semiconductors
Low power level translating I2C-bus/SMBus repeater
6. Functional description
Refer to Figure 1 “Functional diagram of PCA9509P”.
The PCA9509P enables I2C-bus or SMBus translation down to VCC(A) as low as 0.8 V
without degradation of system performance. The PCA9509P contains 2 bidirectional
open-drain buffers specifically designed to support up-translation/down-translation
between the low voltage and 3.3 V SMBus or 5 V I2C-bus. The port A and port B I/Os are
over-voltage tolerant to 5.5 V even when the device is unpowered.
The PCA9509P includes a power-up circuit that keeps the output drivers turned off until
VCC(B) is above 1.7 V and the VCC(A) is above 0.7 V. VCC(B) and VCC(A) can be applied in
any sequence at power-up. After power-up and with the EN pin HIGH, a LOW level on
port A (below approximately 0.15VCC(A)) turns on the corresponding port B driver (either
SDA or SCL) and drives port B down to about 0 V. When port A rises above approximately
0.15VCC(A), the port B pull-down driver is turned off and the external pull-up resistor pulls
the pin HIGH. When port B falls first and goes below 0.3VCC(B), the port A driver is turned
on and port A pulls down to 0.2VCC(A) (typical). The port B pull-down is not enabled unless
the port A voltage goes below VIL. If the port A low voltage goes below VIL, the port B
pull-down driver is enabled until port A rises above approximately 0.15VCC(A) (VIL), then
port B, if not externally driven LOW, rises, being pulled up by the external pull-up resistor.
When port B voltage rises above 50 % of VCC(B), port A continues to rise being pulled up
by external pull-up resistor.
Remark: Ground offset between the PCA9509P ground and the ground of devices on
port A of the PCA9509P must be avoided.
The reason for this cautionary remark is that a CMOS/NMOS open-drain capable of
sinking 3 mA of current at 0.4 V has an output resistance of 133 or less (R = E / I). Such
a driver shares enough current with the port A output pull-down of the PCA9509P to be
seen as a LOW as long as the ground offset is zero. If the ground offset is greater than
0 V, then the driver resistance must be less. Since VIL can be as low as 80 mV at cold
temperatures and the low end of the current distribution, the maximum ground offset
should not exceed 40 mV.
Bus repeaters that use an output offset are not interoperable with the port A of the
PCA9509P as their output LOW levels are not recognized by the PCA9509P as a LOW. If
the PCA9509P is placed in an application where the VIL of port A of the PCA9509P does
not go below its VIL, the port B does not go LOW.
Port B provides normal I2C-bus voltage levels and is interoperable with all I2C-bus slaves,
masters and repeaters.
6.1 Enable
The EN pin is active HIGH and allows the user to select when the repeater is active. This
can be used to isolate a badly behaved slave on power-up until after the system power-up
reset. It should never change state during an I2C-bus operation because disabling during
a bus operation hangs the bus and enabling part way through a bus cycle could confuse
the I2C-bus parts being enabled. The EN also puts the PCA9509P in a standby condition
to reduce power consumption.
PCA9509P
Product data sheet
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Rev. 3 — 19 July 2013
© NXP B.V. 2013. All rights reserved.
5 of 25
PCA9509P
NXP Semiconductors
Low power level translating I2C-bus/SMBus repeater
The enable pin should only change state when the bus and the repeater port are in an idle
state to prevent system failures.
Because the enable pin (EN) can put the PCA9509P in Standby mode, and when in
standby the current mirrors are turned OFF to save power, the recovery from the
disabled/standby state is slow so that the current mirrors can return to full current before
the channels are enabled.
Remark: The system design should allow sufficient time after STOP before disabling the
PCA9509P so that both sides of the SDA and SCL channels are HIGH. It should also
allow sufficient time before the START such that the channel is disabled before the SDA
goes LOW. The PCA9509P should only be enabled during a bus idle state and there also
must be sufficient time allowed before the START such that the PCA9509P is fully active
before the falling edge of the SDA that defines a START.
6.2 I2C-bus systems
As with the standard I2C-bus system, pull-up resistors are required to provide the logic
HIGH levels. The size of these pull-up resistors depends on the system. Port A is
designed to work with pull-up resistor’s size as required to meet rise time requirements
but minimize current consumption. Port B is designed to work with Standard-mode and
Fast-mode I2C-bus devices in addition to SMBus devices. Standard-mode I2C-bus
devices only specify 3 mA output drive; this limits the termination current to 3 mA in a
generic I2C-bus system where Standard-mode devices and multiple masters are possible.
Under certain conditions higher termination currents can be used (when all currents are
> 3 mA).
6.3 Edge rate control
The PCA9509P includes circuitry that slows down the falling edge of both the A side and
B side open-drain output pull-downs. This slowdown reduces system noise and
undershoot when the signal reflects off of the end of the bus. The slew rate control circuit
limits the maximum slew rate, and is relatively insensitive to the load capacitance, the bus
high voltage and to the pull-up value. The rising edge slew rate on the A side and B side is
controlled by RC time constant of the bus pull-up resistor and the bus capacitance, which
are system level considerations and not under the control of the PCA9509P. The pull-up
resistors should be chosen based on the total bus capacitance to result in a reasonable
rising edge transition time that is less than the maximum allowed rise time, and slow
enough not to make system level noise problems, and to make the A side low voltage less
than VIL.
6.4 Bus pull-up resistor selection
The AC test load for the PCA9509P is 1.35 k and 50 pF total capacitance. This results in
a rise time of approximately 60 ns. The 1.35 k resistor is chosen to provide a little less
than 3 mA in a 3.3 V application so it is compatible with Standard-mode I2C-bus devices
as well as Fast-mode devices. The B side output pull-down is a strong driver and is
capable of sinking Fast-mode Plus (Fm+) currents, however the pull-up must be sized for
the weakest part in the system, so if Standard-mode I2C-bus parts are present on the
B side, the pull-up must be limited to less than 3 mA. If only Fm+ parts are used on the
B side, the maximum pull-up current may be up to 30 mA. The pull-up resistor should
always be sized to provide less than the rated pull-up current for the weakest part on the
bus under the maximum bus voltage expected in the system. When the bus capacitance
PCA9509P
Product data sheet
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© NXP B.V. 2013. All rights reserved.
6 of 25
PCA9509P
NXP Semiconductors
Low power level translating I2C-bus/SMBus repeater
is high, the current should be set near the maximum current drive for the weakest part.
However, if the bus capacitance is low a lower current/higher resistor value should be
used to keep the rise time from getting so fast that it causes problems. The A side pull-up
resistor must be selected to keep the LOW-level voltage at the A side input below
0.1VCC(A).
6.4.1 Port A pull-up resistor sizing
When selecting the pull-up resistor for the A side of the PCA9509P there are several
considerations and limitations from both the PCA9509P and the other parts on the A-side
bus that must be taken into account.
6.4.1.1
Minimum resistor size
The first limitation is that in order for the PCA9509P to recognize a LOW on the A side, the
voltage level must be below 0.1VCC(A) including ground offset. This and the drive strength
of the parts driving the less than 0.1VCC(A) level define the minimum resistor value that
can be used based on the other parts on the A-side bus. There is also a limit of 4 mA
maximum current that can be applied to the PCA9509P A side when it is LOW. For
example, if the part driving the PCA9509P A side is rated at 3 mA at 0.4 V (and it is a
MOS part) and assuming that VCC(A) = 0.8 V, then the part has an effective output
resistance of 0.4 V / 3 mA = 133 , so the maximum current is 0.08 V / 133 = ~600 A,
so the maximum pull-up current would be 600 A. And for VCC(A) = 0.8 V the minimum
resistance would be 0.72 V / 600 A = 1.2 k. If the part providing the 0.1VCC(A) has a
very low output resistance, then the current is limited to 4 mA by the PCA9509P, and for
VCC(A) = 0.8 V the minimum pull-up resistance would be 0.64 V / 4 mA = 160 . Since the
ground offset will never be zero, the minimum resistor value needs to be increased
accordingly.
6.4.1.2
Maximum resistance sizing
The pull-up resistor on the A side of the PCA9509P should be chosen to provide at least
100 A of pull-up current. So for VCC(A) = 0.8 V the maximum resistor value looks like
0.64 V / 100 A = 6.4 k.
6.4.1.3
Rise time constraints
In addition to the current minimum and maximum considerations, the RC time constant of
the A-side bus must be considered. It is recommended that the RC time constant be
chosen so that it is greater than 60 ns in order to control the size of the bounce that results
when a driver on the A side turns off that was driving a <0.1VCC(A) level and before the
offset output driver in the PCA9509P can turn on and hold the voltage to ~0.2VCC(A). The
maximum RC time constant is limited by the I2C-bus family specification for maximum
rise time between 0.3VCC(A) and 0.7VCC(A) (400 ns for Fast mode and 1000 ns for
Standard mode operation). Although the maximum current and maximum rise time limits
predict an allowable capacitance well above the 400 pF I2C-bus family specification, this
is not likely to be possible in a typical I2C-bus system since there is so little voltage margin
for the VIL of the PCA9509P ground offset is more likely to limit the effective capacitance
than current drive capability because high-capacitance buses tend to be physically large
and large size tends to result in larger ground offset voltages, which must be severely
limited to be successful at a bus voltage of 1 V and below.
PCA9509P
Product data sheet
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Rev. 3 — 19 July 2013
© NXP B.V. 2013. All rights reserved.
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PCA9509P
NXP Semiconductors
Low power level translating I2C-bus/SMBus repeater
7. Application design-in information
A typical application is shown in Figure 4. In this example, the CPU is running on a 0.9 V
I2C-bus while the slave is connected to a 3.3 V bus. Both buses run at 400 kHz. Master
devices can be placed on either bus.
0.9 V
3.3 V
10 kΩ
VCC(A)
10 kΩ
VCC(B)
SDA
A1
B1
SDA
SCL
A2
B2
SCL
PCA9509P
0.9 V
MASTER
CPU
SLAVE
400 kHz
10 kΩ
EN
bus A
Fig 4.
bus B
002aag176
Typical application
When port B of the PCA9509P is pulled LOW by a driver on the I2C-bus, a CMOS
hysteresis input detects the falling edge when it goes below 0.3VCC(B) and causes the
internal driver on port A to turn on, causing port A to pull down to about 0.2VCC(A). When
port A of the PCA9509P falls, a comparator detects the falling edge when it falls below
0.15VCC(A) and causes the internal driver on port B to turn on and pull the port B pin down
to ground. In order to illustrate what would be seen in a typical application, refer to
Figure 5 and Figure 6. If the bus master in Figure 4 were to write to the slave through the
PCA9509P, waveforms shown in Figure 5 would be observed on the B bus. This looks
like a normal I2C-bus transmission.
On the A bus side of the PCA9509P, the clock and data lines are driven by the master and
swing nearly to ground. After the eighth clock pulse, the slave replies with an ACK that
causes a LOW on the A side equal to the VOL of the PCA9509P, which the master
recognizes as a LOW. It is important to note that any arbitration or clock stretching events
require that the LOW level on the A bus side at the input of the PCA9509P (VIL) is below
0.1VCC(A) to be recognized by the PCA9509P and then transmitted to the B bus side.
WKFORFNSXOVH
DFNQRZOHGJHIURPVODYHRQ%VLGH
6&/
6'$
DDD
Fig 5.
PCA9509P
Product data sheet
Bus B SMBus/I2C-bus waveform
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Rev. 3 — 19 July 2013
© NXP B.V. 2013. All rights reserved.
8 of 25
PCA9509P
NXP Semiconductors
Low power level translating I2C-bus/SMBus repeater
WKFORFNSXOVH
DFNQRZOHGJHIURPVODYHRQ%VLGH
6&/
6'$
92/RI3&$3
92/RIPDVWHU
Fig 6.
DDD
Bus A lower voltage waveform
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VCC(B)
supply voltage port B
VCC(A)
supply voltage port A
voltage on an input/output pin
VI/O
Product data sheet
Min
Max
Unit
0.5
+6.0
V
0.5
+6.0
V
port A
[1]
0.5
+6.0
V
port B; enable pin (EN)
[1]
0.5
+6.0
V
-
20
mA
A-side I/O active LOW
-
20
mA
B-side I/O active LOW
II/O
input/output current
IOL
LOW-level output current
-
40
mA
II
input current
-
20
mA
Ptot
total power dissipation
-
100
mW
Tstg
storage temperature
65
+150
C
Tamb
ambient temperature
Tj
junction temperature
Tsp
solder point temperature
[1]
PCA9509P
Conditions
operating in free air
10 s max.
40
+85
C
-
+125
C
-
300
C
With I/O pins OFF. If active, see IOL.
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PCA9509P
NXP Semiconductors
Low power level translating I2C-bus/SMBus repeater
9. Static characteristics
Table 6.
Static characteristics
GND = 0 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
Supplies
VCC(B)
supply voltage port B
2.3
-
5.5
V
VCC(A)
supply voltage port A
0.8[2]
-
1.5
V
ICC(A)
supply current port A
all port A static HIGH or LOW
2
5
12
A
ICC(B)
supply current port B
all port B static HIGH
200
500
850
A
all port B static LOW
200
510
950
A
ICC(B)stb
standby port B supply current
EN = LOW
0.5
1.5
10
A
port A
0.2VCC(A) -
VCC(A)
V
Input and output of port A (A1 to A2)
VIH
HIGH-level input voltage
VIL
LOW-level input voltage
0.5
-
+0.1VCC(A) V
VIK
input clamping voltage
IL = 18 mA
1.5
-
0.5
V
ILI
input leakage current
VI = VCC(A);
EN = HIGH; B1 = HIGH
10
-
+10
A
A
VOL
LOW-level output voltage
VCC(A) = 0.8 V to 1.5 V;
Iload = 100 A
VOLVIL
difference between LOW-level
output and LOW-level input
voltage
Cio
input/output capacitance
1
-
+1
[3]
-
0.2VCC(A)
0.25VCC(A) V
[4]
-
0.05VCC(A) -
mV
disabled
-
7
10
pF
V
EN = GND
Input and output of port B (B1 to B2)
VIH
HIGH-level input voltage
port B
0.7VCC(B) -
VCC(B)
VIL
LOW-level input voltage
port B
0.5
-
+0.3VCC(B) V
VIK
input clamping voltage
IL = 18 mA
1.5
-
0.5
V
ILI
input leakage current
VI = 3.6 V with An input HIGH
1.0
-
+1.0
A
IIL
LOW-level input current
VI = 200 mV; VCC(B) = 5.5 V;
VCC(A) = 1.5 V; port A = 1.35 k
pull-up to VCC(A)
10
-
+10
A
VOL
LOW-level output voltage
IOL = 6 mA
-
0.1
0.2
V
IOL = 30 mA at VCC(B) = 3.0 V
-
0.2
0.5
V
Cio
input/output capacitance
disabled
-
3
5
pF
0.5
-
+0.2VCC(A) V
Enable
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
0.8VCC(A) -
VCC(B)
V
IIL(EN)
LOW-level input current on
pin EN
VI = 0.2 V; VCC(B) = 3.6 V;
VCC(A) = 1.1 V
10
-
+1
A
ILI
input leakage current
VI = VCC(A)
1
-
+1
A
Ci
input capacitance
VI = 3.0 V
-
2
3
pF
[1]
Typical values with VCC(A) = 1.1 V, VCC(B) = 3.3 V.
PCA9509P
Product data sheet
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Rev. 3 — 19 July 2013
© NXP B.V. 2013. All rights reserved.
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PCA9509P
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Low power level translating I2C-bus/SMBus repeater
[2]
Care must be taken to minimize the resistance in series with the ground pin of the PCA9509P to the ground reference point of the VCC(A)
supply because there is only 80 mV margin between the power good threshold and the 0.8 V minimum supply voltage at cold
temperature (40 C). Because the B-side IOL of up to 30 mA flows through the resistance causing a voltage drop that effectively
reduces the VCC(A) to chip ground voltage and when VCC(A) is less than the power good voltage ~0.72 V, the PCA9509P is disabled. For
example, if the resistance is 1.4 , then 1.4 60 mA = 84 mV and 0.8 V 0.084 V = 0.716 V, which is less than the power good
threshold, so the PCA9509P disables when both outputs drive LOW.
[3]
As long as the chip ground is common with the input ground reference the driver resistance may be as large as 120 . However, ground
offset rapidly decreases the maximum allowed driver resistance.
[4]
Guaranteed by design.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
VCC(A) = 0.8 V to 1.5 V; VCC(B) = 2.3 V to 5.5 V; GND = 0 V; Tamb = 40 C to +85 C; unless otherwise specified.[1]
Symbol
Parameter
LOW to HIGH propagation delay
tPLH
HIGH to LOW propagation delay
tPHL
Min
Typ[2]
Max
Unit
port B to port A
[1]
70
110
180
ns
port B to port A
[1]
104
156
270
ns
Conditions
SRf
falling slew rate
port A; 0.7VCC(A) to 0.3VCC(A)
[1]
0.007 0.015
0.036 V/ns
tPLH
LOW to HIGH propagation delay
port A to port B
[1]
72
110
175
ns
[1]
61
98
266
ns
tPLH2
LOW to HIGH propagation delay 2
port A to port B;
measured from 0.15VCC(A) on port A
to 0.5VCC(B) on port B
tPHL
HIGH to LOW propagation delay
port A to port B
[1]
52
89
226
ns
port B; 0.7VCC(B) to 0.3VCC(B)
[1]
0.02
0.05
0.1
V/ns
EN HIGH to enabled
[3]
10
-
-
s
EN LOW to disabled
[3]
300
-
-
ns
falling slew rate
SRf
ten
enable time
disable time
tdis
[1]
Load capacitance = 50 pF; load resistance on port B = 1.35 k. Port A = 1.35 k, and an input falling slew rate of 0.05 V/ns.
[2]
Typical values were measured with VCC(A) = 1.1 V, VCC(B) = 3.3 V at Tamb = 25 C.
[3]
Enable pin (EN) should only change state when the bus and the repeater port are in an idle state. That is, the ten should be considered
the set-up time before START and tdis should be considered the hold time after STOP.
PCA9509P
Product data sheet
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10.1 AC waveforms
VCC(B)
input
tPHL
output
70 %
VCC(A)
0.5VCC(B)
0.5VCC(B)
input
0.1 V
tPLH
SRf
tPHL
VCC(A)
70 %
0.5VCC(A) 0.5VCC(A)
30 %
30 %
output
70 %
VOL
SRr
0.5VCC(A)
0.5VCC(A)
tPLH
VCC(B)
0.5VCC(B)
30 %
0.5VCC(B)
SRf
002aag139
Fig 7.
002aag140
Propagation delay times and slew rate;
port B to port A
Fig 8.
Propagation delay times and slew rate;
port A to port B
tPLH
0.5VCC(A)
input
port A
0.15VCC(A)
0.5VCC(B)
output
port B
tPLH2
Fig 9.
002aaf976
Propagation delay from the port A’s external driver switching off to port B LOW-to-HIGH transition;
port A to port B
10.2 Performance curves
time
(ns)
002aag178
180
002aag179
−102
tPLH
(ns)
−106
(1)
160
140
−110
120
(2)
100
−114
(3)
(4)
80
−50
−25
0
25
50
75
100
125
Tamb (°C)
−118
−50
VCC(A) = 1.1 V; VCC(B) = 3.3 V
−25
0
25
50
75
100
125
Tamb (°C)
VCC(A) = 1.1 V; VCC(B) = 3.3 V
(1) Port A tPHL
(2) Port A tPLH
(3) Port B tPLH2
(4) Port B tPHL
Fig 10. Typical propagation delay versus
ambient temperature
PCA9509P
Product data sheet
Fig 11. Typical port B LOW to HIGH propagation delay
versus ambient temperature
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002aag183
0.06
time
(ns)
(1)
SR
(V/ns)
002aag184
190
0.04
(1)
150
(2)
0.02
(2)
110
(3)
(3)
(4)
0
−50
(4)
−25
0
25
50
75
70
0.8
100
125
Tamb (°C)
1.0
0.9
1.1
1.2
1.3
1.4
1.5
VCC(A) (V)
Tamb = 27 C; VCC(B) = 3.3 V
VCC(A) = 1.1 V; VCC(B) = 3.3 V
(1) Slew rate of falling signal, port B
(1) Port A tPHL
(2) Slew rate of rising signal, port B
(2) Port A tPLH
(3) Slew rate of falling signal, port A
(3) Port B tPLH2
(4) Slew rate of rising signal, port A
(4) Port B tPHL
Fig 12. Typical slew rate versus ambient temperature
002aag191
−108
Fig 13. Typical propagation delay versus port A
supply voltage
002aag192
0.06
tPLH
(ns)
(1)
SR
(V/ns)
−109
0.04
−110
(2)
0.02
(3)
−111
(4)
−112
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
VCC(A) (V)
0
0.8
Tamb = 27 C; VCC(B) = 3.3 V
0.9
1.0
1.1
1.2
1.3
1.4
1.5
VCC(A) (V)
Tamb = 27 C; VCC(B) = 3.3 V
(1) Slew rate of falling signal, port B
(2) Slew rate of rising signal, port B
(3) Slew rate of falling signal, port A
(4) Slew rate of rising signal, port A
Fig 14. Typical port B LOW to HIGH propagation delay
versus port A supply voltage
PCA9509P
Product data sheet
Fig 15. Typical slew rate versus port A supply voltage
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002aag193
170
time
(ns)
150
002aag194
−90
tPLH
(ns)
−100
(1)
130
−110
(2)
110
−120
(3)
90
−130
(4)
70
2.0
2.5
3.0
3.5
4.0
4.5
−140
2.0
5.0
5.5
VCC(B) (V)
Tamb = 27 C; VCC(A) = 1.1 V
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VCC(B) (V)
Tamb = 27 C; VCC(A) = 1.1 V
(1) Port A tPHL
(2) Port A tPLH
(3) Port B tPLH2
(4) Port B tPHL
Fig 16. Typical propagation delay versus port B
supply voltage
Fig 17. Typical port B LOW to HIGH propagation delay
versus port B supply voltage
002aag195
0.08
SR
(V/ns)
(1)
0.06
0.04
(2)
(3)
0.02
(4)
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VCC(B) (V)
Tamb = 27 C; VCC(A) = 1.1 V
(1) Slew rate of falling signal, port B
(2) Slew rate of rising signal, port B
(3) Slew rate of falling signal, port A
(4) Slew rate of rising signal, port A
Fig 18. Typical slew rate versus port B supply voltage
PCA9509P
Product data sheet
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11. Test information
VCC(A)
VCC(B)
VCC(A)
VCC(B)
RL
OPEN-DRAIN
BUFFER
PULSE
GENERATOR
VI
VO
A
DUT
B
CL
RT
002aag196
RL = load resistor; 1.35 k
CL = load capacitance includes jig and probe capacitance; 50 pF
RT = termination resistance should be equal to Zo of pulse generators
Fig 19. Test circuit for open-drain outputs A to B
VCC(B)
VCC(B)
VCC(B)
VCC(A)
RL
RL
OPEN-DRAIN
BUFFER
PULSE
GENERATOR
VI
VO
B
DUT
A
RT
CL
002aag197
RL = load resistor; 1.35 k
CL = load capacitance includes jig and probe capacitance; 50 pF
RT = termination resistance should be equal to Zo of pulse generators
Fig 20. Test circuit for open-drain outputs B to A
PCA9509P
Product data sheet
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12. Package outline
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Fig 21. Package outline SOT505-1 (TSSOP8)
PCA9509P
Product data sheet
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Rev. 3 — 19 July 2013
© NXP B.V. 2013. All rights reserved.
16 of 25
PCA9509P
NXP Semiconductors
Low power level translating I2C-bus/SMBus repeater
;4)1SODVWLFH[WUHPHO\WKLQTXDGIODWSDFNDJHQROHDGV
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Fig 22. Package outline SOT902-2 (XQFN8)
PCA9509P
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 19 July 2013
© NXP B.V. 2013. All rights reserved.
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Low power level translating I2C-bus/SMBus repeater
13. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
PCA9509P
Product data sheet
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Rev. 3 — 19 July 2013
© NXP B.V. 2013. All rights reserved.
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Low power level translating I2C-bus/SMBus repeater
13.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 23) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 8 and 9
Table 8.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350
< 2.5
235
220
2.5
220
220
Table 9.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 23.
PCA9509P
Product data sheet
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Low power level translating I2C-bus/SMBus repeater
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 23. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
14. Soldering: PCB footprints
VROGHUODQGV
RFFXSLHGDUHD
'LPHQVLRQVLQPP
VRWBIU
Fig 24. PCB footprint for SOT505-1 (TSSOP8); reflow soldering
PCA9509P
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 19 July 2013
© NXP B.V. 2013. All rights reserved.
20 of 25
PCA9509P
NXP Semiconductors
Low power level translating I2C-bus/SMBus repeater
)RRWSULQWLQIRUPDWLRQIRUUHIORZVROGHULQJRI;4)1SDFNDJH
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Fig 25. PCB footprint for SOT902-2 (XQFN8); reflow soldering
PCA9509P
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 19 July 2013
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Low power level translating I2C-bus/SMBus repeater
15. Abbreviations
Table 10.
Abbreviations
Acronym
Description
CDM
Charged-Device Model
CMOS
Complementary Metal-Oxide Semiconductor
CPU
Central Processing Unit
ESD
ElectroStatic Discharge
HBM
Human Body Model
I/O
Input/Output
I2C-bus
Inter-Integrated Circuit bus
NMOS
Negative-channel Metal-Oxide Semiconductor
RC
Resistor-Capacitor network
SMBus
System Management Bus
16. Revision history
Table 11.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCA9509P v.3
20130719
Product data sheet
-
PCA9509P v.2
Modifications:
•
Section 7 “Application design-in information”:
– Third paragraph rewritten to describe timing events better
– Figure 5 “Bus B SMBus/I2C-bus waveform” modified: added phrase “from slave on B side”
– Figure 6 “Bus A lower voltage waveform” modified: added phrase “from slave on B side” and
adjusted SDA waveform
PCA9509P v.2
20130515
Product data sheet
-
PCA9509P v.1
PCA9509P v.1
20120814
Product data sheet
-
-
PCA9509P
Product data sheet
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17. Legal information
18. Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
18.1 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
18.2 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PCA9509P
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 19 July 2013
© NXP B.V. 2013. All rights reserved.
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No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
18.3 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PCA9509P
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 19 July 2013
© NXP B.V. 2013. All rights reserved.
24 of 25
PCA9509P
NXP Semiconductors
Low power level translating I2C-bus/SMBus repeater
20. Contents
1
1.1
2
3
3.1
4
5
5.1
5.2
6
6.1
6.2
6.3
6.4
6.4.1
6.4.1.1
6.4.1.2
6.4.1.3
7
8
9
10
10.1
10.2
11
12
13
13.1
13.2
13.3
13.4
14
15
16
17
18
18.1
18.2
18.3
19
20
General description . . . . . . . . . . . . . . . . . . . . . . 1
Selection recommendations . . . . . . . . . . . . . . . 2
Features and benefits . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
I2C-bus systems . . . . . . . . . . . . . . . . . . . . . . . . 6
Edge rate control . . . . . . . . . . . . . . . . . . . . . . . 6
Bus pull-up resistor selection . . . . . . . . . . . . . . 6
Port A pull-up resistor sizing . . . . . . . . . . . . . . . 7
Minimum resistor size . . . . . . . . . . . . . . . . . . . . 7
Maximum resistance sizing. . . . . . . . . . . . . . . . 7
Rise time constraints . . . . . . . . . . . . . . . . . . . . 7
Application design-in information . . . . . . . . . . 8
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 9
Static characteristics. . . . . . . . . . . . . . . . . . . . 10
Dynamic characteristics . . . . . . . . . . . . . . . . . 11
AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . 12
Performance curves . . . . . . . . . . . . . . . . . . . . 12
Test information . . . . . . . . . . . . . . . . . . . . . . . . 15
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
Soldering of SMD packages . . . . . . . . . . . . . . 18
Introduction to soldering . . . . . . . . . . . . . . . . . 18
Wave and reflow soldering . . . . . . . . . . . . . . . 18
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 18
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 19
Soldering: PCB footprints. . . . . . . . . . . . . . . . 20
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 22
Legal information. . . . . . . . . . . . . . . . . . . . . . . 23
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Contact information. . . . . . . . . . . . . . . . . . . . . 24
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 19 July 2013
Document identifier: PCA9509P