Data Sheet

PCA9704
18 V tolerant SPI 8-bit GPI with maskable INT
Rev. 1 — 10 December 2015
Product data sheet
1. General description
The PCA9704 is a low power 18 V tolerant SPI General Purpose Input (GPI) shift register
designed to monitor the status of switch inputs. It generates an interrupt when one or
more of the switch inputs change state but allows selected inputs to not generate
interrupts using the interrupt masking feature. The input level is recognized as a HIGH
when it is greater than 0.8  VDD and as a LOW when it is less than 0.55  VDD (minimum
LOW threshold of 2.5 V at 5 V node). The PCA9704 can monitor up to 8 switch inputs.
The falling edge of the CS pin samples the input port status and clears the interrupt. When
CS is LOW, the rising edge of the SCLK loads the shift register and shifts the value out of
the shift register. The serial input is sampled on the falling edge of SCLK. The contents of
the shift register are loaded into the interrupt mask register of the device on the rising
edge of CS.
Each of the input ports has a 18 V breakdown ESD protection circuit, which dumps the
ESD/overvoltage current to ground. When used with a series resistor (minimum 100 k),
the input can connect to a 12 V battery and support double battery, reverse battery, 27 V
jump start and 40 V load dump conditions in automotive applications. Higher voltages can
be tolerated on the inputs depending on the series resistor used to limit the input current.
The INT_EN pin is used to both enable the GPI pins and to enable the INT output pin to
minimize battery drain in cyclically supplied pull-up or pull-down applications. The SDIN
pull-down prevents floating nodes when the device is used in daisy-chain applications.
With both the high breakdown voltage and high ESD, this device is useful for both
automotive (AEC-Q100 compliance available) and mobile applications.
2. Features and benefits











8 general purpose input ports
18 V tolerant input ports with 100 k external series resistor
Input LOW threshold 0.55  VDD with minimum of 2.5 V at VDD = 4.5 V
Open-drain interrupt output
Interrupt enable pin (INT_EN) disables GPI pins and interrupt output
Interrupt-masking feature allows no interrupt generation from selected inputs
VDD range: 4.5 V to 5.5 V
IDD is very low 2.5 A maximum
SPI serial interface with speeds up to 5 MHz
SPI supports daisy-chain connection for large switch numbers
AEC-Q100 compliance available
PCA9704
NXP Semiconductors
18 V tolerant SPI 8-bit GPI with maskable INT
 ESD protection exceeds 5 kV HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
 Operating temperature range: 40 C to +125 C
 Offered in TSSOP16 package
3. Applications
 Automotive
 Body control modules
 Electronic control units (for example, for body controller)
 Switch monitoring
 SBC wake pin extension
 Industrial equipment
 Cellular telephones
 Emergency lighting
4. Ordering information
Table 1.
Ordering information
Type number
Topside
marking
Package
Name
Description
Version
PCA9704
TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
PCA9704PW/Q900[1] PCA9704
TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
PCA9704PW
[1]
PCA9704PW/Q900 is AEC-Q100 compliant. Contact [email protected] for PPAP.
4.1 Ordering options
Table 2.
Ordering options
Type number
Orderable
part number
Package
Packing method
Minimum
Temperature
order quantity
PCA9704PW
PCA9704PWJ
TSSOP16
Reel 13” Q1/T1
*Standard mark
SMD
2500
Tamb = 40 C to +125 C
PCA9704PW/Q900
PCA9704PW/Q900J TSSOP16
Reel 13” Q1/T1
*Standard mark
SMD
2500
Tamb = 40 C to +125 C
PCA9704
Product data sheet
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Rev. 1 — 10 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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PCA9704
NXP Semiconductors
18 V tolerant SPI 8-bit GPI with maskable INT
5. Block diagram
VDD
INT
PCA9704
DFF0
IN1
INPUT
DFF1
IN7
MASK REGISTER
INPUT
SHIFT REGISTER
INT_EN
IN0
SDOUT
SDIN
SCLK
CS
DFF15
INPUT
INPUT
STATUS
REGISTER
20 μA
aaa-016387
VSS
Fig 1.
Block diagram of PCA9704
6. Pinning information
6.1 Pinning
SDOUT
1
16 VDD
INT
2
15 SDIN
INT_EN
3
14 SCLK
IN0
4
IN1
5
IN2
6
11 IN6
IN3
7
10 IN5
VSS
8
PCA9704PW
PCA9704PW/Q900
13 CS
12 IN7
9
IN4
002aae025
Fig 2.
PCA9704
Product data sheet
Pin configuration for TSSOP16
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Rev. 1 — 10 December 2015
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PCA9704
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18 V tolerant SPI 8-bit GPI with maskable INT
6.2 Pin description
Table 3.
Pin description
Symbol
Pin
Type
Description
output
3-state serial data output; normally high-impedance
TSSOP16
SDOUT
1
INT
2
output
open-drain interrupt output (active LOW)
INT_EN
3
input
GPI pin enable and interrupt output enable
1 = GPI pin and interrupt output are enabled
0 = GPI pin and interrupt output are disabled and interrupt
output is high-impedance
PCA9704
Product data sheet
IN0
4
input
input port 0
IN1
5
input
input port 1
IN2
6
input
input port 2
IN3
7
input
input port 3
VSS
8
ground
ground supply
IN4
9
input
input port 4
IN5
10
input
input port 5
IN6
11
input
input port 11
IN7
12
input
input port 12
CS
13
input
chip select (active LOW)
SCLK
14
input
serial input clock
SDIN
15
input
serial data input (20 A pull-down)
VDD
16
supply
supply voltage
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Rev. 1 — 10 December 2015
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PCA9704
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18 V tolerant SPI 8-bit GPI with maskable INT
7. Functional description
PCA9704 is a 8-bit General Purpose Input (GPI) with an open-drain interrupt output
designed to monitor switch status. By putting an external 100 k series resistor at the
input port, the device allows the input to tolerate momentary double 12 V battery, reverse
battery, 27 V jump start or 40 V load dump conditions. The interrupt output is asserted
when an input port status changes, the input is not masked and the interrupt output is
enabled. The open-drain interrupt output is enabled when INT_EN is HIGH and disabled
when INT_EN is LOW. The INT_EN also enables the GPI pins when it is HIGH. In
cyclically supplied pull-up or pull-down applications, the GPI pull-ups or pull-downs should
be active before the INT_EN is taken HIGH and the INT output should only be sampled
after transient conditions have settled. Additionally, interrupts can be disabled in software
by using the interrupt mask feature. The input port status is accessed via the 4-wire SPI
interface.
Upon power-up, the power-up reset cell clears all the registers, resulting in all zeros in
both the input status register and the interrupt mask register. Since a zero in the interrupt
mask register masks the interrupt from that pin, there will not be any interrupts generated.
After power-up it is necessary to access the PCA9704 through the SPI pins in order to
activate the interrupt for any GPI pins. When the PCA9704 is read over the SPI wires, the
input conditions are clocked into the input status register on the CS falling edge. Since the
inputs and the input status register now match, no interrupt is generated and any
pre-existing interrupt is cleared. The input status register data is parallel loaded into the
shift register on the first rising edge of the SCLK. The serial input data is captured on the
opposite clock edge so that there is a 1⁄2 clock cycle hold time. The set-up time is
diminished by the propagation time so the SCLK falling edge to rising edge must be long
enough to provide sufficient set-up time. Successive clock cycles on the SCLK pin clock
the data out of the PCA9704 and new data from the SDIN into the shift register. There is
no limit to the number of clock cycles that can be applied with the CS LOW, however
sufficient clock cycles should be used to both shift out all of the GPI data and shift in the
new interrupt mask data to the correct position with the MSB first before the CS rising
edge.
For cyclic switch bias applications the switch bias should be applied first, then after the
input voltage is settled the general purpose inputs are switched on by taking the INT_EN
HIGH. This also enables the interrupt output, which will only indicate an interrupt if the GPI
data does not match the input status register on a bit that is enabled by the interrupt mask
register value. If an interrupt is generated, the pull-up or pull-down source should remain
active and the INT_EN should remain active and the SPI pins are used to update the input
status register and read the data out. They are also used to store the new interrupt mask
on the rising edge of CS. After the SPI transaction is complete the INT_EN is taken LOW
to turn the inputs off and disable the INT output. Then the GPI pull-ups or pull-downs can
be turned off. The GPI pins are specifically designed so that any ESD/overstress current
flows to ground, not VDD. They are also specifically designed so that if the input voltage
returns to the same value after pull-up or pull-down bias cycling as before the input pull-up
or pull-down bias cycling, before the input is enabled it will be detected as the same state.
If the Input Status register is read when INT_EN is LOW, the input state at the INT_EN
transition will be output regardless of the actual input levels since the GPI pins are turned
off.
PCA9704
Product data sheet
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Rev. 1 — 10 December 2015
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PCA9704
NXP Semiconductors
18 V tolerant SPI 8-bit GPI with maskable INT
If the VDD falls below the 4.5 V minimum specified supply voltage, the input threshold will
move down since they are a function of the VDD voltage. The input status register and the
interrupt mask register retain their values to below VDD = 2.0 V and power-down can only
be used to generate a power-up reset if the VDD falls below 0.2 V before returning to the
operating range.
Multiple PCA9704 devices can be serially connected for monitoring a large number of
switches by connecting the SDOUT of one device to the SDIN of the next device. SCLK
and CS must be common among all devices and interrupt outputs may be tied together.
No external logic is necessary because all the devices’ interrupt outputs are open-drain
that function as ‘wired-AND’ and can simply be connected together to a single pull-up
resistor.
7.1 SPI bus operation
The PCA9704 interfaces with the controller via the 4-wire SPI bus that is comprised of the
following signals: chip select (CS), serial clock (SCLK), serial data in (SDIN), and serial
data out (SDOUT). To access the device, the controller asserts CS LOW, then sends
SCLK and SDIN. When reading is complete and the interrupt mask data is in place, the
controller de-asserts CS. See Figure 3 for register access timing.
7.1.1 CS - chip select
The CS pin is the device chip select and is an active LOW input. The falling edge of CS
captures the input port status in the input status register. If the interrupt output is asserted,
the falling edge of CS will clear the interrupt. When CS is LOW, the SPI interface is active.
When CS transitions HIGH the interrupt mask is stored and when CS is HIGH, the SPI
interface is disabled.
7.1.2 SCLK - serial clock input
SCLK is the serial clock input to the device. It should be LOW and remain LOW during the
falling and rising edge of CS. When CS is LOW, the first rising edge of SCLK parallel
loads the shift register from the input status register. The subsequent rising edges on
SCLK serially shifts data out from the shift register. The falling edge of SCLK samples the
data on SDIN.
7.1.3 SDIN - serial data input
SDIN is the serial data input port. The data is sampled into the shift register on the falling
edge of SCLK. SDIN is only active when CS is LOW. This input has a 20 A pull-down
current source to prevent the SDIN node from floating when CS is HIGH.
7.1.4 SDOUT - serial data output
SDOUT is the serial data output signal. SDOUT is high-impedance when CS is HIGH and
switches to low-impedance after CS goes LOW. When CS is LOW, after the first rising
edge of SCLK the most significant bit in the shift register is presented on SDOUT.
Subsequent rising edges of SCLK shift the remaining data from the shift register onto
SDOUT.
PCA9704
Product data sheet
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Rev. 1 — 10 December 2015
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PCA9704
NXP Semiconductors
18 V tolerant SPI 8-bit GPI with maskable INT
7.1.5 Register access timing
Figure 3 shows the waveforms of the device operation. Initially CS is HIGH and SCLK is
LOW. On the falling edge of CS, input port status, DATA[n:0] is captured into the input
status register, and subsequently the first rising edge of SCLK parallel loads the shift
register. The falling edge of SCLK samples the data on the SDIN. The MSB from the shift
register is valid and available on the SDOUT after the first rising edge of SCLK.
sample
SDIN
CS
SCLK
SDIN
MSB in
MSB - 1 in
LSB in
SDOUT
MSB out
MSB - 1 out
LSB out
shift
register
DATA[7:0]
high-impedance
input status
register
DATA[7:0]
interrupt mask
register
aaa-016390
DATA[7:0] is data on the input pins, IN[7:0].
Shaded areas indicate active but invalid data.
Fig 3.
Register access timing
7.1.6 Software reset operation
Software reset will be activated by writing all zeroes into the shift register. This is identical
to having an interrupt mask value of 0X00. Such an operation will reset the device, clear
the input status register to zero and set the interrupt output to HIGH (no interrupt).
7.2 Interrupt output
INT is the open-drain interrupt output and is active LOW. A pull-up resistor of
approximately 10 k is recommended.
A user-defined interrupt mask bit pattern is shifted into the shift register via SDIN. The
value of bits in the mask pattern will determine which input pins will cause an interrupt.
Any bit that is = 0 will disable the input pin corresponding to that bit position from
generating an interrupt. Interrupts will be enabled for bits having value = 1. The mask bit
pattern is not automatically aligned with the desired input pins. It is the responsibility of the
programmer to shift the correct number of (mask) bits to the correct positions into the shift
PCA9704
Product data sheet
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PCA9704
NXP Semiconductors
18 V tolerant SPI 8-bit GPI with maskable INT
register. The interrupt mask bit pattern must be positioned into the shift register prior to the
CS rising edge. Misaligned mask pattern will result in unexpected activation of the
interrupt signal.
The interrupt output is asserted when the input status is changed, and the interrupt mask
bit corresponding to the input pin that caused the change is unmasked (bit value = 1), and
is cleared on the falling edge of CS or when the input port status matches the input status
register. When there are multiple devices, the INT outputs may be tied together to a single
pull-up.
Table 4 illustrates the state of the interrupt output versus the state of the input port and
input status register. The interrupt output is asserted when the input port and input status
register differ.
Table 4.
Interrupt output function truth table
H = HIGH; L = LOW; X = don’t care
INT_EN
Input port status
Input status register[1]
INT output[2]
Mask bit = 1
(unmasked)
Mask bit = 0
(masked)
L
H
H
H
L
H
L
H
L
H
H
H
L
L
H
H
H
H
H
H
L
X
X
H
H
[1]
Input status register is the value or content of the D flip-flops.
[2]
Logic states shown for INT pin assumes 10 k pull-up resistor.
7.3 Interrupt enable
INT_EN is the interrupt output enable input and the general purpose input enable input. It
is an active HIGH input. When the INT_EN pin is LOW the GPI pins are turned off and the
input state is saved to minimize power loss when the input pull-ups or pull-downs are
cycled and the INT output is disabled. The cycled pull-ups or pull-downs should be active
sufficiently long before the INT_EN is taken active that the GPI pin voltage is completely
settled to prevent false or transient interrupt signals.
7.4 General Purpose Inputs
The General Purpose Inputs (GPI) are designed to behave like a typical input in the 0 V to
5.5 V range, but are also designed to have low leakage currents at elevated voltages. The
input structure allows for elevated voltages to be applied through a series resistor. The
series resistor is required when the input voltage is above 5.5 V. The series resistor is
required for two reasons: first, to prevent damage to the input avalanche diode, and
second, to prevent the ESD protection circuitry from creating an excessive current flow.
The ESD protection circuitry includes a latch-back style device, which provides excellent
ESD protection during assembly or typical 5.5 V applications. The series resistor limits the
current flowing into the part and provides additional ESD protection. The limited current
prevents the ESD latch-back device from latching back to a low voltage, which would
cause excessive current flow and damage the part when the input voltage is above 5.5 V.
PCA9704
Product data sheet
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Rev. 1 — 10 December 2015
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PCA9704
NXP Semiconductors
18 V tolerant SPI 8-bit GPI with maskable INT
The minimum required series resistance for applications with input voltages above 5.5 V
is 100 k. For applications requiring an applied voltage above 27 V, Equation 1 is
recommended to determine the series resistor. Failure to include the appropriate input
series resistor may result in product failure and will void the warranty.
voltage applied – 17 V
R s = -----------------------------------------------------------II
(1)
The series resistor should be place physically as close as possible to the connected input
to reduce the effective node capacitance. The node between the 100 k resistor and the
GPI input is effectively a low pass filter with a time constant of 200 ns to 500 ns due to the
input capacitance of the pin and any extra metal on that node will add more capacitance
further increasing the RC time constant. Long interconnect lengths between the 100 k
resistor and the GPI input pin will act like an antenna on this high impedance node and
should be avoided to prevent noise injection.
7.4.1 VIL, VIH and switching points
A minimum LOW threshold of 2.5 V is guaranteed for the logical switching points for the
inputs. See Figure 4 for details.
VI
HIGH
VDD
0.8VDD
VIH
VIL
0.55VDD
hysteresis
minimum = 0.04VDD
possible ground shift
LOW
0V
aaa-016559
Fig 4.
Logic level thresholds
The VIL is specified as a maximum of 0.55  VDD and is 2.5 V at 4.5 V VDD. This means
that if the user applies 2.5 V or less to the input (with VDD = 4.5 V), or as the voltage
passes this threshold, they will always see a LOW.
The VIH is specified as a minimum of 0.8  VDD. This means that if the user applies 3.6 V
or more to the input (with VDD = 4.5 V), or as the voltage passes this threshold, they will
always see a HIGH.
Hysteresis minimum is specified as 180 mV at VDD = 4.5 V. This means there will always
be at least 180 mV of difference between the LOW threshold and HIGH threshold to help
prevent oscillations and handle higher noise.
PCA9704
Product data sheet
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Rev. 1 — 10 December 2015
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PCA9704
NXP Semiconductors
18 V tolerant SPI 8-bit GPI with maskable INT
When measuring hysteresis without the 100 K external series resistor, the apparent value
will be considerably less than the specified value due to the interaction of the input
structure and the external resistor.
8. Application design-in information
8.1 General application
4.5 V to 5.5 V
18 V
1.5 kΩ
100 kΩ
IN0
VDD
10 kΩ
relay
INT
CS
SCLK
SDIN
SDOUT
18 V
CONTROLLER
OR
PROCESSOR
100 kΩ
INT_EN
IN1
180 V
open
PCA9704
500 kΩ
IN2
50 kΩ
5V
10 kΩ
IN7
VSS
aaa-016391
Fig 5.
Typical application
8.2 Automotive application
Supports:
•
•
•
•
•
PCA9704
Product data sheet
12 V battery (8 V to 16 V)
Double battery (16 V to 32 V)
Reverse battery (8 V to 16 V)
Jump start (27 V for 60 seconds)
Load dump (40 V)
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PCA9704
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18 V tolerant SPI 8-bit GPI with maskable INT
8.2.1 SBC wake port extension with cyclic biasing
System Basis Chips (SBC) offer many functions needed for in-vehicle networking
solutions. Some of the features built into SBC are:
•
•
•
•
Transceivers (HS-CAN, LIN 2.0)
Scalable voltage regulators
Watchdog timers; wake-up function
Fail-safe function
For more information on SBC, refer to
www.nxp.com/products/interface_and_connectivity/system_basis_chips/.
8.2.1.1
UJA106x with PCA9704, standby
V3
alternate
PVR100AD-B5V0
UJA106x
IN0
INT
IN1
INT_EN
PCA9704
V2
V1
GND
VDD
CS
SDIN
SDOUT
SCLK
IN7
WAKE
VSS
VCC
CSN
μC
MOSI
MISO
SCLK
GND
aaa-016392
Fig 6.
•
•
•
•
UJA106x with PCA9704 with supplied microcontroller (standby)
PCA9704 fits to SBC UJA106x and UJA107xA family
PCA9704 can be powered by V1 of SBC
Extends the SBC with 16 additional wake inputs
C can be set to stop-mode during standby to save ECU standby current. SBC with
GPI periodically monitors the wake inputs
– Cyclic bias via V3
– Very low system current consumption even with clamped switches
– Interrupt enable control via V2
PCA9704
Product data sheet
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Rev. 1 — 10 December 2015
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PCA9704
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18 V tolerant SPI 8-bit GPI with maskable INT
8.2.1.2
UJA107xA with PCA9704, standby and sleep
alternate PDTA114E
BAT
10 kΩ
WBIAS
V1
1 kΩ
1 kΩ
10 kΩ
alternate
PDTA144E
1 kΩ
UJA107xA
47 kΩ
WAKE1
WAKE2
RSTN
V1
GND
47 kΩ
VDD
PCA9704
100 kΩ
10 kΩ
INT
INT_EN
IN0
100 kΩ
IN1
IN7
VSS
100 kΩ
10 kΩ
CS
SDIN
SDOUT
SCLK
VCC
CSN
μC
MOSI
MISO
SCLK
GND
aaa-016393
Fig 7.
UJA107xA with PCA9704 with supplied microcontroller (standby)
alternate PDTA114E
BAT
10 kΩ
WBIAS
6.8 kΩ
alternate
PVR100AD-B5V0
10 kΩ
1 kΩ
1 kΩ
470 nF
UJA107xA
1 kΩ
alternate PDTA144E
47 kΩ
47 kΩ
VDD
10 kΩ
PCA9704
100 kΩ
INT
INT_EN
IN0
100 kΩ
IN1
IN7
100 kΩ
VSS
10 kΩ
alternate
PDTC144T
WAKE1
WAKE2
RSTN
V1
GND
47 kΩ
10 kΩ
CS
SDIN
SDOUT
SCLK
VCC
CSN
μC
MOSI
MISO
SCLK
GND
aaa-016394
Fig 8.
UJA107xA with PCA9704 with supplied microcontroller (sleep)
• UJA107xA SBC provides WBIAS pin for cyclic biasing of the inputs
• Compatible with UJA107xA based ASSPs
PCA9704
Product data sheet
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Rev. 1 — 10 December 2015
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PCA9704
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18 V tolerant SPI 8-bit GPI with maskable INT
8.2.2 Application examples including switches to battery
BAT BAT
switch bias
switch bias
IN0
IN0
IN1
IN1
PCA9704
PCA9704
IN7
IN7
clamp 15
aaa-016408
aaa-016395
Fig 9.
Clamp 15 (ignition) detection
Fig 10. Switches to battery and ground with
cyclic biasing
9. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Tamb = 40 C to +125 C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Max
Unit
VDD
supply voltage
0.5
+6.0
V
II
input current
IN[7:0] pins with series resistor and
VI > 5.5 V
[1]
-
350
A
VI
input voltage
GPI pins IN[7:0]; no series resistor
[1]
0.5
+6
V
Tstg
storage temperature
Tj(max)
maximum junction temperature
SPI pins
[1]
operating
0.5
+6
V
65
+150
C
-
125
C
With GPI external series resistors, the inputs support double battery, reverse battery and load dump conditions. During double battery or
load dump the input pin will drain slightly higher leakage current until the input drops to 18 V. For more detail of leakage current
specification, please refer to Table 6 “Static characteristics”. See Section 7.4 for series resistor requirements.
PCA9704
Product data sheet
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Rev. 1 — 10 December 2015
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PCA9704
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18 V tolerant SPI 8-bit GPI with maskable INT
10. Static characteristics
Table 6.
Static characteristics
VDD = 4.5 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +125 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
4.5
5.0
5.5
V
-
1.0
2.5
A
[1]
-
1.8
2.2
V
[2]
-
-
0.55VDD V
0.8VDD
-
-
V
Supply
VDD
supply voltage
IDD
supply current
VPOR
power-on reset voltage
VDD = 5.5 V; input = 5 V or 18 V;
INT_EN = VDD
General Purpose Inputs (IN0 to IN7)
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
Vhys
hysteresis voltage
VDD = 4.5 V
-
0.04VDD
-
V
Vhysr
hysteresis voltage with
external resistor
VDD = 4.5 V; 100 k external series
resistor
0.04VDD
0.05VDD
-
V
II
input current
GPI recommended maximum current;
VI > 5.5 V; with series resistor Rs
-
-
100
A
IIH
HIGH-level input current
each input; VI = VDD
1
-
+1
A
ILI
input leakage current
VI = 17 V; 100 k series resistor
1
-
+1
A
Ci
input capacitance
VI = VSS or VDD
-
2.0
5.0
pF
[3]
Interrupt output (INT)
IOL
LOW-level output current
VDD = 4.5 V; VOL = 0.4 V
6
-
-
mA
IOH
HIGH-level output current
VOH = VDD
1
-
+1
A
Co
output capacitance
-
2
5
pF
SPI and control (SDOUT, SDIN, SCLK, CS, INT_EN)
VIL
LOW-level input voltage
-
-
0.3VDD
V
VIH
HIGH-level input voltage
0.7VDD
-
5.5
V
IIH
HIGH-level input current
SDIN; VI = VDD = 5.5 V
-
20
40
A
IOL
LOW-level output current
SDOUT; VOL = 0.4 V; VDD = 4.5 V
5
-
-
mA
IOH
HIGH-level output current
SDOUT; VOH = VDD  0.5 V;
VDD = 4.5 V
5
11
-
mA
Ci
input capacitance
VI = VSS or VDD
-
2
5
pF
Co
output capacitance
SDOUT; CS = VDD
-
4
6
pF
[1]
VDD must be lowered to 0.2 V for at least 5 s in order to reset device.
[2]
Minimum VIL is 2.5 V at VDD = 4.5 V.
[3]
For GPI pin voltages > 5.5 V, see Section 7.4.
PCA9704
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18 V tolerant SPI 8-bit GPI with maskable INT
11. Dynamic characteristics
Table 7.
Dynamic characteristics
VDD = 4.5 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +125 C; unless otherwise specified.
Symbol
Parameter
Conditions
fmax
maximum input clock frequency
Min
Typ
Max
Unit
-
-
5
MHz
tr
rise time
SDOUT; 10 % to 90 % at 5 V
-
35
60
ns
tf
fall time
SDOUT; 90 % to 10 % at 5 V
-
25
50
ns
tWH
pulse width HIGH
SCLK
50
-
-
ns
tWL
pulse width LOW
SCLK
50
-
-
ns
tSPILEAD
SPI enable lead time
CS falling edge to SCLK rising edge
50
-
-
ns
tSPILAG
SPI enable lag time
SCLK falling edge to CS rising edge
50
-
-
ns
tsu(SDIN)
SDIN set-up time
SDIN to SCLK falling edge
20
-
-
ns
th(SDIN)
SDIN hold time
from SCLK falling edge
30
-
-
ns
ten(SDOUT)
SDOUT enable time
from CS LOW to
SDOUT low-impedance; Figure 14
-
-
55
ns
tdis(SDOUT)
SDOUT disable time
from rising edge of CS to SDOUT
high-impedance; Figure 14
-
-
85
ns
tv(SDOUT)
SDOUT valid time
from rising edge of SCLK; Figure 15
-
-
55
ns
tsu(SCLK)
SCLK set-up time
SCLK falling to CS falling
50
-
-
ns
th(SCLK)
SCLK hold time
SCLK rising after CS rising
50
-
-
ns
tPOR
power-on reset pulse time
time before CS is active
after VDD > VPOR
-
-
250
ns
trel(int)
interrupt release time
after CS going LOW; Figure 16
-
-
500
ns
-
200
800
ns
valid time on pin INT
tv(INT)
[1]
after INn changes or INT_EN
goes HIGH
[1]
Timing will be affected by the low pass filter caused by the 100 k series resistor and the GPI pin capacitance including the PC board
trace capacitance
CS
tsu(SCLK) tSPILEAD
tWH
50 %
tsu(SDIN)
SCLK
tSPILAG
tWL
th(SCLK)
50 %
th(SDIN)
MSB in
SDIN
ten(SDOUT)
tv(SDOUT)
tdis(SDOUT)
high-impedance
MSB out
SDOUT
trel(int)
INT
002aac428
Fig 11. Timing diagram
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18 V tolerant SPI 8-bit GPI with maskable INT
2.5 V
VDD
VPOR
0V
CS
SCLK
SDOUT
MSB − 1
MSB out
tPOR
002aad158
Fig 12. AC waveform for tPOR timing
CS
INn
STATE 0
STATE 1
STATE 0
INT_EN
tv(INT)
tv(INT)
INT
trel(int)
trel(int)
002aaf294
Fig 13. AC waveform for INT timing
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18 V tolerant SPI 8-bit GPI with maskable INT
12. Test information
VDD
open
VDD
PULSE
GENERATOR
VI
RL
10 kΩ
VO
DUT
CL
50 pF
RT
10 kΩ
002aac580
Fig 14. Test circuitry for enable/disable times, SDOUT (ten(SDOUT) and tdis(SDOUT))
VDD
PULSE
GENERATOR
VI
VO
DUT
CL
50 pF
RT
002aac581
Fig 15. Test circuitry for switching times, SDOUT (tv(SDOUT))
VDD
VDD
PULSE
GENERATOR
VI
RL
10 kΩ
VO
DUT
CL
50 pF
RT
002aac582
Fig 16. Test circuitry for switching times, INT
RL = load resistance.
CL = load capacitance includes jig and probe capacitance.
RT = termination resistance should be equal to the output impedance Zo of the pulse
generators.
PCA9704
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18 V tolerant SPI 8-bit GPI with maskable INT
13. Package outline
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
E
D
A
X
c
y
HE
v M A
Z
9
16
Q
(A 3)
A2
A
A1
pin 1 index
θ
Lp
L
1
8
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.40
0.06
8o
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT403-1
REFERENCES
IEC
JEDEC
JEITA
MO-153
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
Fig 17. Package outline SOT403-1 (TSSOP16)
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18 V tolerant SPI 8-bit GPI with maskable INT
14. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
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18 V tolerant SPI 8-bit GPI with maskable INT
14.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 18) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 8 and 9
Table 8.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
 350
< 2.5
235
220
 2.5
220
220
Table 9.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 18.
PCA9704
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18 V tolerant SPI 8-bit GPI with maskable INT
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 18. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
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18 V tolerant SPI 8-bit GPI with maskable INT
15. Soldering: PCB footprints
Footprint information for reflow soldering of TSSOP16 package
SOT403-1
Hx
Gx
P2
(0.125)
Hy
Gy
(0.125)
By
Ay
C
D2 (4x)
D1
P1
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1
P2
Ay
By
C
D1
D2
Gx
Gy
Hx
Hy
0.650
0.750
7.200
4.500
1.350
0.400
0.600
5.600
5.300
5.800
7.450
sot403-1_fr
Fig 19. PCB footprint for SOT403-1 (TSSOP16); reflow soldering
PCA9704
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18 V tolerant SPI 8-bit GPI with maskable INT
16. Abbreviations
Table 10.
Abbreviations
Acronym
Description
ASSP
Application Specific Standard Product
CAN
Controller Area Network
CDM
Charged-Device Model
DUT
Device Under Test
ECU
Electronic Control Unit
ESD
ElectroStatic Discharge
GPI
General Purpose Input
HBM
Human Body Model
HS-CAN
High-Speed Controller Area Network
LIN
Local Interconnect Network
MSB
Most Significant Bit
PCB
Printed-Circuit Board
PPAP
Production Part Approval Process
RC
Resistor-Capacitor network
SBC
System Basis Chip
SPI
Serial Peripheral Interface
C
microcontroller
17. Revision history
Table 11.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCA9704 v.1
20151210
Product data sheet
-
-
PCA9704
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18 V tolerant SPI 8-bit GPI with maskable INT
18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PCA9704
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
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18 V tolerant SPI 8-bit GPI with maskable INT
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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18 V tolerant SPI 8-bit GPI with maskable INT
20. Contents
1
2
3
4
4.1
5
6
6.1
6.2
7
7.1
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
7.2
7.3
7.4
7.4.1
8
8.1
8.2
8.2.1
8.2.1.1
8.2.1.2
8.2.2
9
10
11
12
13
14
14.1
14.2
14.3
14.4
15
16
17
18
18.1
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
SPI bus operation . . . . . . . . . . . . . . . . . . . . . . . 6
CS - chip select . . . . . . . . . . . . . . . . . . . . . . . . 6
SCLK - serial clock input . . . . . . . . . . . . . . . . . 6
SDIN - serial data input. . . . . . . . . . . . . . . . . . . 6
SDOUT - serial data output . . . . . . . . . . . . . . . 6
Register access timing . . . . . . . . . . . . . . . . . . . 7
Software reset operation. . . . . . . . . . . . . . . . . . 7
Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . . 7
Interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . 8
General Purpose Inputs . . . . . . . . . . . . . . . . . . 8
VIL, VIH and switching points. . . . . . . . . . . . . . . 9
Application design-in information . . . . . . . . . 10
General application. . . . . . . . . . . . . . . . . . . . . 10
Automotive application . . . . . . . . . . . . . . . . . . 10
SBC wake port extension with cyclic biasing . 11
UJA106x with PCA9704, standby. . . . . . . . . . 11
UJA107xA with PCA9704, standby and sleep 12
Application examples including switches to
battery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 13
Static characteristics. . . . . . . . . . . . . . . . . . . . 14
Dynamic characteristics . . . . . . . . . . . . . . . . . 15
Test information . . . . . . . . . . . . . . . . . . . . . . . . 17
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18
Soldering of SMD packages . . . . . . . . . . . . . . 19
Introduction to soldering . . . . . . . . . . . . . . . . . 19
Wave and reflow soldering . . . . . . . . . . . . . . . 19
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 19
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 20
Soldering: PCB footprints. . . . . . . . . . . . . . . . 22
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 23
Legal information. . . . . . . . . . . . . . . . . . . . . . . 24
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 24
18.2
18.3
18.4
19
20
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
24
25
25
26
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2015.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 10 December 2015
Document identifier: PCA9704
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