Data Sheet

PCA9670
Remote 8-bit I/O expander for Fm+ I2C-bus with reset
Rev. 3 — 30 May 2013
Product data sheet
1. General description
The PCA9670 provides general-purpose remote I/O expansion via the two-wire
bidirectional I2C-bus (serial clock (SCL), serial data (SDA)).
The devices consist of eight quasi-bidirectional ports, 1 MHz 30 mA drive I2C-bus
interface, three hardware address inputs and a reset input operating between 2.3 V and
5.5 V. 1 MHz I2C-bus Fast-mode Plus (Fm+) can support PWM dimming of LEDs, and
higher I2C-bus drive 30 mA allows more devices to be on the bus without the need for bus
buffers. The quasi-bidirectional port can be independently assigned as an input to monitor
interrupt status or keypads, or as an output to activate indicator devices such as LEDs.
The system master can read from the input port or write to the output port through a single
register.
The low current consumption of 2.5 A (typical, static) is great for mobile applications and
the latched output ports have 25 mA high current sink drive capability for directly driving
LEDs.
The PCA9670 has three hardware address pins and allows up to 64 of these PCA9670
I/O expanders on the same I2C-bus without the need for bus buffers, supporting up to
512 I/Os (for example, 512 LEDs).
The internal Power-On Reset (POR) and active LOW hardware reset pin (RESET)
initialize the I/Os as inputs with a weak internal pull-up 100 A current source.
2. Features and benefits













I2C-bus to parallel port expander
1 MHz I2C-bus interface (Fast-mode Plus I2C-bus)
SDA with 30 mA sink capability for 4000 pF buses
Operating supply voltage 2.3 V to 5.5 V with 5.5 V tolerant I/Os held to VDD with
100 A current source
8-bit remote I/O pins that default to inputs at power-up
Latched outputs with 25 mA sink capability for directly driving LEDs
Total package sink capability of 200 mA
Active LOW reset input
Sixty-four programmable slave addresses using three address pins
Readable device ID (manufacturer, device type, and revision)
Software reset
Low standby current (2.5 A typical)
40 C to +85 C operation
PCA9670
NXP Semiconductors
Remote 8-bit I/O expander for Fm+ I2C-bus with reset
 ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
 Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA
 Packages offered: SO16, TSSOP16 and HVQFN16
3. Applications










LED signs and displays
Servers
Keypads
Industrial control
Medical equipment
PLCs
Cellular telephones
Mobile devices
Gaming machines
Instrumentation and test measurement
4. Ordering information
Table 1.
Ordering information
Type number
Topside
marking
Package
Name
Description
Version
PCA9670BS
670
HVQFN16
plastic thermal enhanced very thin quad flat package; no leads;
16 terminals; body 3  3  0.85 mm
SOT758-1
PCA9670D
PCA9670D
SO16
plastic small outline package; 16 leads; body width 7.5 mm
SOT162-1
PCA9670PW
PCA9670
TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
4.1 Ordering options
Table 2.
Ordering options
Type number
Orderable
part number
Package
Packing method
Minimum
order
quantity
Temperature range
PCA9670BS
PCA9670BS,118
HVQFN16
Reel 13” Q1/T1
*standard mark SMD
6000
Tamb = 40 C to +85 C
PCA9670D
PCA9670PW
PCA9670D,512
SO16
Standard marking * tube dry pack 1920
Tamb = 40 C to +85 C
PCA9670D,518
SO16
Reel 13” Q1/T1
*standard mark SMD dry pack
1000
Tamb = 40 C to +85 C
PCA9670PW,112
TSSOP16
Standard marking *
IC’s tube - DSC bulk pack
2400
Tamb = 40 C to +85 C
PCA9670PW,118
TSSOP16
Reel 13” Q1/T1
*standard mark SMD
2500
Tamb = 40 C to +85 C
PCA9670
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 30 May 2013
© NXP B.V. 2013. All rights reserved.
2 of 35
PCA9670
NXP Semiconductors
Remote 8-bit I/O expander for Fm+ I2C-bus with reset
5. Block diagram
PCA9670
AD0
AD1
AD2
SCL
SDA
RESET
VDD
INPUT
FILTER
I2C-BUS
CONTROL
SHIFT
REGISTER
8 BITS
I/O
PORT
P0 to P7
write pulse
read pulse
POWER-ON
RESET
VSS
002aac256
Fig 1.
Block diagram of PCA9670
IOH
write pulse
VDD
100 µA
Itrt(pu)
data from Shift Register
D
Q
FF
IOL
CI
P0 to P7
S
power-on reset
VSS
D
Q
FF
read pulse
CI
S
data to Shift Register
Fig 2.
PCA9670
Product data sheet
002aah741
Simplified schematic diagram of P0 to P7
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Rev. 3 — 30 May 2013
© NXP B.V. 2013. All rights reserved.
3 of 35
PCA9670
NXP Semiconductors
Remote 8-bit I/O expander for Fm+ I2C-bus with reset
6. Pinning information
6.1 Pinning
AD0
1
1
16 VDD
2
16 VDD
15 SDA
AD0
AD1
AD1
2
15 SDA
AD2
3
14 SCL
AD2
3
14 SCL
P0
4
13 RESET
P0
4
P1
5
12 P7
P1
5
P2
6
11 P6
P2
6
11 P6
P3
7
10 P5
P3
7
10 P5
VSS
8
9
VSS
8
PCA9670D
P4
PCA9670PW
12 P7
9
002aac257
P4
002aac258
AD2
1
P0
2
Pin configuration for TSSOP16
13 SDA
terminal 1
index area
14 VDD
Fig 4.
15 AD0
Pin configuration for SO16
16 AD1
Fig 3.
13 RESET
12 SCL
11 RESET
PCA9670BS
7
8
P5
9
P4
4
6
P2
VSS
10 P7
5
3
P3
P1
P6
002aac261
Transparent top view
Fig 5.
Pin configuration for HVQFN16
6.2 Pin description
Table 3.
Symbol
AD0
PCA9670
Product data sheet
Pin description
Pin
Description
SO16, TSSOP16
HVQFN16
1
15
address input 0
AD1
2
16
address input 1
AD2
3
1
address input 2
P0
4
2
quasi-bidirectional I/O 0
P1
5
3
quasi-bidirectional I/O 1
P2
6
4
quasi-bidirectional I/O 2
P3
7
5
quasi-bidirectional I/O 3
VSS
8
6[1]
supply ground
P4
9
7
quasi-bidirectional I/O 4
P5
10
8
quasi-bidirectional I/O 5
P6
11
9
quasi-bidirectional I/O 6
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 30 May 2013
© NXP B.V. 2013. All rights reserved.
4 of 35
PCA9670
NXP Semiconductors
Remote 8-bit I/O expander for Fm+ I2C-bus with reset
Table 3.
Symbol
Pin description …continued
Pin
Description
SO16, TSSOP16
HVQFN16
P7
12
10
quasi-bidirectional I/O 7
RESET
13
11
reset input (active LOW)
SCL
14
12
serial clock line
SDA
15
13
serial data line
VDD
16
14
supply voltage
[1]
HVQFN16 package die supply ground is connected to both the VSS pin and the exposed center pad. The
VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical,
and board-level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board, and for proper heat conduction through the board thermal vias need to be
incorporated in the PCB in the thermal pad region.
7. Functional description
Refer to Figure 1 “Block diagram of PCA9670”.
7.1 Device address
Following a START condition, the bus master must send the address of the slave it is
accessing and the operation it wants to perform (read or write). The address format of the
PCA9670 is shown in Figure 6. Slave address pins AD2, AD1, and AD0 are used to
choose one of 64 slave addresses. These devices can monitor the change in SDA or SCL
in addition to the static levels of VDD or VSS to decode four states allowing a larger
address range. To conserve power, no internal pull-up resistors are incorporated on AD2,
AD1, or AD0 so they must be externally connected to VDD, VSS directly or through
resistors, or to SCL or SDA directly. Address values depending on AD2, AD1, and AD0
can be found in Table 4 “PCA9670 address map”.
Remark: When using the PCA9670, reserved I2C-bus addresses must be used with
caution since they can interfere with:
• “reserved for future use” I2C-bus addresses (0000 011, 1111 101, 1111 110, 1111 111)
• slave devices that use the 10-bit addressing scheme (1111 0xx)
• High speed mode (Hs-mode) master code (0000 1xx)
slave address
A6
A5
A4
A3
A2
A1
programmable
Fig 6.
A0 R/W
002aab636
PCA9670 address
The last bit of the first byte defines the operation to be performed. When set to logic 1 a
read is selected, while a logic 0 selects a write operation.
When AD2, AD1 and AD0 are held to VDD or VSS, the same address as the PCF8574 or
newer PCA8574 is applied.
PCA9670
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 30 May 2013
© NXP B.V. 2013. All rights reserved.
5 of 35
PCA9670
NXP Semiconductors
Remote 8-bit I/O expander for Fm+ I2C-bus with reset
7.1.1 Address maps
Table 4.
PCA9670 address map
Pin connectivity
PCA9670
Product data sheet
Address of PCA9670
Address byte value
Write
Read
7-bit
hexadecimal
address
without R/W
-
20h
21h
10h
1
-
22h
23h
11h
1
0
-
24h
25h
12h
1
1
-
26h
27h
13h
1
0
0
-
28h
29h
14h
1
0
1
-
2Ah
2Bh
15h
0
-
2Ch
2Dh
16h
1
-
2Eh
2Fh
17h
0
-
30h
31h
18h
0
1
-
32h
33h
19h
0
1
0
-
34h
35h
1Ah
0
1
1
-
36h
37h
1Bh
1
1
0
0
-
38h
39h
1Ch
1
1
1
0
1
-
3Ah
3Bh
1Dh
0
1
1
1
1
0
-
3Ch
3Dh
1Eh
0
1
1
1
1
1
-
3Eh
3Fh
1Fh
0
1
0
0
0
0
0
-
40h
41h
20h
VDD
0
1
0
0
0
0
1
-
42h
43h
21h
VDD
VSS
0
1
0
0
0
1
0
-
44h
45h
22h
VDD
VDD
0
1
0
0
0
1
1
-
46h
47h
23h
VDD
VSS
VSS
0
1
0
0
1
0
0
-
48h
49h
24h
VDD
VSS
VDD
0
1
0
0
1
0
1
-
4Ah
4Bh
25h
VDD
VDD
VSS
0
1
0
0
1
1
0
-
4Ch
4Dh
26h
VDD
VDD
VDD
0
1
0
0
1
1
1
-
4Eh
4Fh
27h
VSS
VSS
SCL
0
1
0
1
0
0
0
-
50h
51h
28h
VSS
VSS
SDA
0
1
0
1
0
0
1
-
52h
53h
29h
VSS
VDD
SCL
0
1
0
1
0
1
0
-
54h
55h
2Ah
VSS
VDD
SDA
0
1
0
1
0
1
1
-
56h
57h
2Bh
VDD
VSS
SCL
0
1
0
1
1
0
0
-
58h
59h
2Ch
VDD
VSS
SDA
0
1
0
1
1
0
1
-
5Ah
5Bh
2Dh
VDD
VDD
SCL
0
1
0
1
1
1
0
-
5Ch
5Dh
2Eh
VDD
VDD
SDA
0
1
0
1
1
1
1
-
5Eh
5Fh
2Fh
AD2
AD1
AD0 A6 A5 A4 A3 A2 A1 A0 R/W
VSS
SCL
VSS
0
0
1
0
0
0
0
VSS
SCL
VDD
0
0
1
0
0
0
VSS
SDA
VSS
0
0
1
0
0
VSS
SDA
VDD
0
0
1
0
0
VDD
SCL
VSS
0
0
1
0
VDD
SCL
VDD
0
0
1
0
VDD
SDA
VSS
0
0
1
0
1
1
VDD
SDA
VDD
0
0
1
0
1
1
VSS
SCL
SCL
0
0
1
1
0
0
VSS
SCL
SDA
0
0
1
1
0
VSS
SDA
SCL
0
0
1
1
VSS
SDA
SDA
0
0
1
1
VDD
SCL
SCL
0
0
1
VDD
SCL
SDA
0
0
VDD
SDA
SCL
0
VDD
SDA
SDA
0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
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Rev. 3 — 30 May 2013
© NXP B.V. 2013. All rights reserved.
6 of 35
PCA9670
NXP Semiconductors
Remote 8-bit I/O expander for Fm+ I2C-bus with reset
Table 4.
PCA9670 address map …continued
Pin connectivity
AD2
PCA9670
Product data sheet
AD1
Address of PCA9670
Address byte value
AD0 A6 A5 A4 A3 A2 A1 A0 R/W
Write
Read
7-bit
hexadecimal
address
without R/W
SCL
SCL
VSS
1
0
1
0
0
0
0
-
A0h
A1h
50h
SCL
SCL
VDD
1
0
1
0
0
0
1
-
A2h
A3h
51h
SCL
SDA
VSS
1
0
1
0
0
1
0
-
A4h
A5h
52h
SCL
SDA
VDD
1
0
1
0
0
1
1
-
A6h
A7h
53h
SDA
SCL
VSS
1
0
1
0
1
0
0
-
A8h
A9h
54h
SDA
SCL
VDD
1
0
1
0
1
0
1
-
AAh
ABh
55h
SDA
SDA
VSS
1
0
1
0
1
1
0
-
ACh
ADh
56h
SDA
SDA
VDD
1
0
1
0
1
1
1
-
AEh
AFh
57h
SCL
SCL
SCL
1
0
1
1
0
0
0
-
B0h
B1h
58h
SCL
SCL
SDA
1
0
1
1
0
0
1
-
B2h
B3h
59h
SCL
SDA
SCL
1
0
1
1
0
1
0
-
B4h
B5h
5Ah
SCL
SDA
SDA
1
0
1
1
0
1
1
-
B6h
B7h
5Bh
SDA
SCL
SCL
1
0
1
1
1
0
0
-
B8h
B9h
5Ch
SDA
SCL
SDA
1
0
1
1
1
0
1
-
BAh
BBh
5Dh
SDA
SDA
SCL
1
0
1
1
1
1
0
-
BCh
BDh
5Eh
SDA
SDA
SDA
1
0
1
1
1
1
1
-
BEh
BFh
5Fh
SCL
VSS
VSS
1
1
0
0
0
0
0
-
C0h
C1h
60h
SCL
VSS
VDD
1
1
0
0
0
0
1
-
C2h
C3h
61h
SCL
VDD
VSS
1
1
0
0
0
1
0
-
C4h
C5h
62h
SCL
VDD
VDD
1
1
0
0
0
1
1
-
C6h
C7h
63h
SDA
VSS
VSS
1
1
0
0
1
0
0
-
C8h
C9h
64h
SDA
VSS
VDD
1
1
0
0
1
0
1
-
CAh
CBh
65h
SDA
VDD
VSS
1
1
0
0
1
1
0
-
CCh
CDh
66h
SDA
VDD
VDD
1
1
0
0
1
1
1
-
CEh
CFh
67h
SCL
VSS
SCL
1
1
1
0
0
0
0
-
E0h
E1h
70h
SCL
VSS
SDA
1
1
1
0
0
0
1
-
E2h
E3h
71h
SCL
VDD
SCL
1
1
1
0
0
1
0
-
E4h
E5h
72h
SCL
VDD
SDA
1
1
1
0
0
1
1
-
E6h
E7h
73h
SDA
VSS
SCL
1
1
1
0
1
0
0
-
E8h
E9h
74h
SDA
VSS
SDA
1
1
1
0
1
0
1
-
EAh
EBh
75h
SDA
VDD
SCL
1
1
1
0
1
1
0
-
ECh
EDh
76h
SDA
VDD
SDA
1
1
1
0
1
1
1
-
EEh
EFh
77h
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 30 May 2013
© NXP B.V. 2013. All rights reserved.
7 of 35
PCA9670
NXP Semiconductors
Remote 8-bit I/O expander for Fm+ I2C-bus with reset
7.2 Software Reset Call, and device ID addresses
Two other different addresses can be sent to the PCA9670.
• General Call address: allows resetting the PCA9670 through the I2C-bus upon
reception of the right I2C-bus sequence. See Section 7.2.1 “Software Reset” for more
information.
• Device ID address: allows reading ID information from the device (manufacturer, part
identification, revision). See Section 7.2.2 “Device ID (PCA9670 ID field)” for more
information.
R/W
0
0
0
0
0
0
0
0
002aac115
Fig 7.
General Call address
1
1
1
1
1
0
0
R/W
002aac116
Fig 8.
Device ID address
7.2.1 Software Reset
The Software Reset Call allows all the devices in the I2C-bus to be reset to the power-up
state value through a specific formatted I2C-bus command. To be performed correctly, it
implies that the I2C-bus is functional and that there is no device hanging the bus.
The Software Reset sequence is defined as following:
1. A START command is sent by the I2C-bus master.
2. The reserved General Call I2C-bus address ‘0000 000’ with the R/W bit set to 0 (write)
is sent by the I2C-bus master.
3. The PCA9670 device(s) acknowledge(s) after seeing the General Call address
‘0000 0000’ (00h) only. If the R/W bit is set to 1 (read), no acknowledge is returned to
the I2C-bus master.
4. Once the General Call address has been sent and acknowledged, the master sends
1 byte. The value of the byte must be equal to 06h.
a. The PCA9670 acknowledges this value only. If the byte is not equal to 06h, the
PCA9670 does not acknowledge it.
If more than 1 byte of data is sent, the PCA9670 does not acknowledge any more.
5. Once the right byte has been sent and correctly acknowledged, the master sends a
STOP command to end the Software Reset sequence: the PCA9670 then resets to
the default value (power-up value) and is ready to be addressed again within the
specified bus free time. If the master sends a Repeated START instead, no reset is
performed.
PCA9670
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 30 May 2013
© NXP B.V. 2013. All rights reserved.
8 of 35
PCA9670
NXP Semiconductors
Remote 8-bit I/O expander for Fm+ I2C-bus with reset
The I2C-bus master must interpret a non-acknowledge from the PCA9670 (at any time) as
a ‘Software Reset Abort’. The PCA9670 does not initiate a reset of its registers.
The unique sequence that initiates a Software Reset is described in Figure 9.
SWRST Call I2C-bus address
S
0
0
0
0
0
START condition
0
0
SWRST data = 06h
0
A
0
0
R/W
acknowledge
from slave(s)
0
0
0
1
1
0
A
P
acknowledge
from slave(s)
PCA9670 is(are) reset.
Registers are set to default power-up values.
002aac263
Fig 9.
Software Reset sequence
Simple code for Software Reset:
<S> <00h> <ACK> <06h> <ACK> <P>
7.2.2 Device ID (PCA9670 ID field)
The Device ID field is a 3-byte read-only (24 bits) word giving the following information:
• 12 bits with the manufacturer name, unique per manufacturer (for example, NXP).
• 9 bits with the part identification, assigned by manufacturer.
• 3 bits with the die revision, assigned by manufacturer (for example, Rev X).
The Device ID is read-only, hardwired in the device and can be accessed as follows:
1. START command
2. The master sends the Reserved Device ID I2C-bus address ‘1111 100’ with the R/W
bit set to 0 (write).
3. The master sends the I2C-bus slave address of the slave device it needs to identify.
The LSB is a ‘Don’t care’ value. Only one device must acknowledge this byte (the one
that has the I2C-bus slave address).
4. The master sends a Re-START command.
Remark: A STOP command followed by a START command will reset the slave state
machine and the Device ID read cannot be performed.
Remark: A STOP command or a Re-START command followed by an access to
another slave device will reset the slave state machine and the Device ID read cannot
be performed.
5. The master sends the Reserved Device ID I2C-bus address ‘1111 100’ with the R/W
bit set to 1 (read).
6. The device ID read can be done, starting with the 12 manufacturer bits (first byte +
4 MSB of the second byte), followed by the 9 part identification bits and then the 3 die
revision bits (3 LSB of the third byte).
7. The master ends the reading sequence by NACKing the last byte, thus resetting the
slave device state machine and allowing the master to send the STOP command.
PCA9670
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PCA9670
NXP Semiconductors
Remote 8-bit I/O expander for Fm+ I2C-bus with reset
Remark: The reading of the Device ID can be stopped anytime by sending a NACK
command.
Remark: If the master continues to ACK the bytes after the third byte, the PCA9670
rolls back to the first byte and keeps sending the Device ID sequence until a NACK
has been detected.
For the PCA9670, the Device ID is as shown in Figure 10.
manufacturer
0
0
0
part identification
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
revision
0
002aac264
Fig 10. PCA9670 Device ID field
acknowledge from
one or several slaves
Device ID address
S 1
1
1
1
1
0
START condition
0
I2C-bus slave address
of the device to be identified
acknowledge from
slave to be identified
Device ID address
0 A A6 A5 A4 A3 A2 A1 A0 0 A Sr 1
R/W
don’t care
acknowledge
from master
acknowledge from
slave to be identified
1
1
1
repeated START
condition
acknowledge
from master
1
0
0
1 A
R/W
no acknowledge
from master
M M
A M3 M2 M1 M0 P8 P7 P6 P5 A P4 P3 P2 P1 P0 R2 R1 R0 A P
11 10 M9 M8 M7 M6 M5 M4
STOP condition
manufacturer name = 000000000000
part identification = 100000000
revision = 000
002aac267
If more than 2 bytes are read, the slave device loops back to the first byte (manufacturer byte) and keeps sending data until the
master generates a ‘no acknowledge’.
Fig 11. Device ID field reading
Simple code for reading Device ID:
<S> <F8h> <ACK> <slave address> <ACK> <SR> <F9h > <ACK> <DATA1>
<ACK> <DATA2> <ACK> <DATA3> <NACK> <P>
PCA9670
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PCA9670
NXP Semiconductors
Remote 8-bit I/O expander for Fm+ I2C-bus with reset
8. I/O programming
8.1 Quasi-bidirectional I/O architecture
A quasi-bidirectional I/O is an input or output port without using a direction control register.
Whenever the master reads the register, the value returned to master depends on the
actual voltage or status of the pin. At power-on, all the ports are HIGH with a weak 100 A
internal pull-up to VDD but can be driven LOW by an internal transistor, or an external
signal. The I/O ports are entirely independent of each other but each I/O octal is controlled
by the same read or write data byte.
Advantages of the quasi-bidirectional I/O over totem pole I/O include:
• Better for driving LEDs since the p-channel (transistor to VDD) is small, which saves
die size and therefore cost. LED drive only requires an internal transistor to ground,
while the LED is connected to VDD through a current-limiting resistor. Totem pole I/O
have both an n-channel and p-channel transistors, which allow solid HIGH and LOW
output levels without a pull-up resistor — good for logic levels.
• Simpler architecture — only a single register and the I/O can be both input and output
at the same time. Totem pole I/O have a direction register which specifies the port pin
direction and it is always in that configuration unless the direction is explicitly
changed.
• Does not require a command byte. The simplicity of one register (no need for the
pointer register or technically, the command byte) is an advantage in some embedded
systems where every byte counts because of memory or bandwidth limitations.
There is only one register to control four possibilities of the port pin: Input HIGH, input
LOW, output HIGH or output LOW.
Input HIGH: The master needs to write 1 to the register to set the port as an input mode
if the device is not in the default power-on condition. The master reads the register to
check the input status. If the external source pulls the port pin up to VDD or drives
logic 1, then the master will read the value of 1.
Input LOW: The master needs to write 1 to the register to set the port to input mode if
the device is not in the default power-on condition. The master reads the register to
check the input status. If the external source pulls the port pin down to VSS or drives
logic 0, which sinks the weak 100 A current source, then the master will read the value
of 0.
Output HIGH: The master writes 1 to the register. There is an additional ‘accelerator’ or
strong pull-up current when the master sets the port HIGH. The additional strong pull-up
is only active during the HIGH time of the acknowledge clock cycle. This accelerator
current helps the port’s 100 A current source make a faster rising edge into a heavily
loaded output, but only at the start of the acknowledge clock cycle to avoid bus
contention if an external signal is pulling the port LOW to VSS/driving the port with
logic 0 at the same time. After the half clock cycle there is only the 100 A current
source to hold the port HIGH.
Output LOW: The master writes 0 to the register. There is a strong current sink
transistor that holds the port pin LOW. A large current may flow into the port, which
could potentially damage the part if the master writes a 0 to the register and an external
source is pulling the port HIGH at the same time.
PCA9670
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PCA9670
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Remote 8-bit I/O expander for Fm+ I2C-bus with reset
VDD
input HIGH
weak 100 µA
current source
(inactive when
output LOW)
pull-up with
resistor to VDD or
external drive HIGH
output HIGH
accelerator
pull-up
P port
P7 - P0
pull-down with
resistor to VSS or
external drive LOW
output LOW
input LOW
VSS
002aah683
Fig 12. Simple quasi-bidirectional I/O
8.2 Writing to the port (Output mode)
The master (microcontroller) sends the START condition and slave address, setting the
last bit of the address byte to logic 0 for the write mode. The PCA9670 acknowledges and
the master then sends the data byte for P7 to P0 to the port register. As the clock line
goes HIGH, the 8-bit data is presented on the port lines after it has been acknowledged by
the PCA9670. If a LOW is written, the strong pull-down turns on and stays on. If a HIGH is
written, the strong pull-up turns on for 1⁄2 of the clock cycle, then the line is held HIGH by
the weak current source. The master can then send a STOP condition or continuing
sending data. The number of data bytes that can be sent successively is not limited and
the previous data is overwritten every time a data byte has been sent and acknowledged.
Ensure a logic 1 is written for any port that is being used as an input to ensure the strong
external pull-down is turned off.
SCL
1
2
3
4
5
6
7
8
9
slave address
data 1
SDA S A6 A5 A4 A3 A2 A1 A0 0
START condition
R/W
data 2
A P7 P6 1 P4 P3 P2 P1 P0 A P7 0 P5 P4 P3 P2 P1 P0 A
P5
P5
acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
write to port
tv(Q)
tv(Q)
data output from port
DATA 1 VALID
DATA 2 VALID
P5 output voltage
P5 pull-up output current
Itrt(pu)
IOH
002aac265
Fig 13. Write mode (output)
PCA9670
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PCA9670
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Remote 8-bit I/O expander for Fm+ I2C-bus with reset
8.3 Reading from a port (Input mode)
The port must have been previously written to logic 1, which is the condition after
power-on reset or hardware reset or software reset. To enter the Read mode the master
(microcontroller) addresses the slave device and sets the last bit of the address byte to
logic 1 (address byte read). The slave will acknowledge and then send the data byte to
the master. The master will NACK and then send the STOP condition or ACK and read the
input register again.
The read of any pin being used as an output will indicate HIGH or LOW depending on the
actual state of the input pin.
If the data on the input port changes faster than the master can read, this data may be
lost. The DATA 2 and DATA 3 are lost because these data did not meet the set-up time
and hold time (see Figure 14).
slave address
data from port
SDA S A6 A5 A4 A3 A2 A1 A0 1
START condition
R/W
DATA 1
A
data from port
A
acknowledge
from slave
DATA 4
no acknowledge
from master
1
P
STOP
condition
acknowledge
from master
read from port
DATA 2
data at port
DATA 1
DATA 3
th(D)
tsu(D)
DATA 4
002aac266
A LOW-to-HIGH transition of SDA while SCL is HIGH is defined as the STOP condition (P). Transfer of data can be stopped at
any moment by a STOP condition. When this occurs, data present at the last acknowledge phase is valid (Output mode). Input
data is lost.
Fig 14. Read input port register
8.4 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9670 in
a reset condition until VDD has reached VPOR. At that point, the reset condition is released
and the PCA9670 registers and I2C-bus/SMBus state machine will initialize to their default
states of all I/Os to inputs with weak current source to VDD. Thereafter VDD must be
lowered below VPOR and back up to the operation voltage for power-on reset cycle.
8.5 RESET input
A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). The
PCA9670 registers and I2C-bus state machine will be held in their default state until the
RESET input is once again HIGH. This RESET input pin requires a pull-up resistor to VDD
if no active connection is used.
PCA9670
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PCA9670
NXP Semiconductors
Remote 8-bit I/O expander for Fm+ I2C-bus with reset
9. Characteristics of the I2C-bus
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
9.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 15).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
mba607
Fig 15. Bit transfer
9.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 16.)
SDA
SCL
S
P
START condition
STOP condition
mba608
Fig 16. Definition of START and STOP conditions
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PCA9670
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Remote 8-bit I/O expander for Fm+ I2C-bus with reset
9.2 System configuration
A device generating a message is a ‘transmitter'; a device receiving is the ‘receiver'. The
device that controls the message is the ‘master' and the devices which are controlled by
the master are the ‘slaves' (see Figure 17).
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
I2C-BUS
MULTIPLEXER
SLAVE
002aaa966
Fig 17. System configuration
9.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit (see Figure 18). The acknowledge bit is an active LOW level (generated
by the receiving device) that indicates to the transmitter that the data transfer was
successful.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that wants to issue an
acknowledge bit has to pull down the SDA line during the acknowledge clock pulse, so
that the SDA line is stable LOW during the HIGH period of the acknowledge bit related
clock pulse; set-up and hold times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from master
1
2
S
START
condition
8
9
clock pulse for
acknowledgement
002aaa987
Fig 18. Acknowledgement on the I2C-bus
PCA9670
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15 of 35
PCA9670
NXP Semiconductors
Remote 8-bit I/O expander for Fm+ I2C-bus with reset
10. Application design-in information
10.1 Bidirectional I/O expander applications
In the 8-bit I/O expander application shown in Figure 19, P0 and P1 are inputs, and P2 to
P7 are outputs. When used in this configuration, during a write, the input (P0 and P1)
must be written as HIGH so the external devices fully control the input ports. The
desired HIGH or LOW logic levels may be written to the I/Os used as outputs (P2 to P7).
If 10 A internal output HIGH is not enough current source, the port needs external pull-up
resistor. During a read, the logic levels of the external devices driving the input ports (P0
and P1) and the previous written logic level to the output ports (P2 to P7) will be read.
The GPIO also has a reset line (RESET) that can be connected to an output pin of the
microprocessor. Since the device does not have an interrupt output, changes of the I/Os
can be monitored by reading the input register. If both a RESET and INT are needed, use
the PCA9672.
VDD
VDD
CORE
PROCESSOR
VDD
SDA
SCL
RESET
AD0
AD1
AD2
P0
P1
P2
P3
P4
P5
P6
P7
temperature sensor
battery status
control for latch
control for switch
control for audio
control for camera
control for MP3
002aac298
Fig 19. Bidirectional I/O expander application
10.2 How to read and write to I/O expander (example)
In the application example of PCA9670 shown in Figure 19, the microcontroller wants to
control the P3 switch ON and the P7 LED ON when the temperature sensor P0 changes.
1. When the system power on:
Core Processor needs to issue an initial command to set P0 and P1 as inputs and
P[7:2] as outputs with value 1010 00 (LED off, MP3 off, camera on, audio off, switch
off and latch off).
2. Operation:
When the temperature changes above the threshold, the temperature sensor signal
will toggle from HIGH to LOW. The INT will be activated and notifies the ‘core
processor’ that there have been changes on the input pins. Read the input register.
If P0 = 0 (temperature sensor has changed), then turn on LED and turn on switch.
3. Software code:
//System Power on
// write to PCA9670 with data 1010 0011b to set P[7:2] outputs and P[1:0] inputs
<S> <0100 0000> <ACK> <1010 0011> <ACK> <P>//Initial setting for PCA9670
while (1) //Looping look for P0 = 0
PCA9670
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PCA9670
NXP Semiconductors
Remote 8-bit I/O expander for Fm+ I2C-bus with reset
{
<S> <0100 0001> <ACK> <1010 0010> <NACK> <P> //Read PCA9670 data
If (P0 == 0) //Temperature sensor activated
{
// write to PCA9670 with data 0010 1011b to turn on LED (P7), on Switch (P3)
and keep P[1:0] as input ports.
<S> <0100 0000> <ACK> <0010 1011> <ACK> <P> // Write to PCA9670
Exit the loop;
}
}
10.3 High current-drive load applications
The GPIO has a minimum guaranteed sinking current of 25 mA per bit at 5.5 V. In
applications requiring additional drive, two port pins may be connected together to sink up
to 50 mA current. Both bits must then always be turned on or off together. Up to 8 pins can
be connected together to drive 200 mA, which is the device recommended total limit.
Each pin needs its own limiting resistor as shown in Figure 20 to prevent damage to the
device should all ports not be turned on at the same time.
VDD
VDD
SDA
SCL
RESET
CORE
PROCESSOR
AD0
AD1
AD2
VDD
P0
P1
P2
P3
P4
P5
P6
P7
LOAD
002aac299
Fig 20. High current-drive load application
10.4 Migration path
NXP offers new, more capable drop-in replacements for the PCA9670 in newer
space-saving packages.
Table 5.
PCA9670 migration path
Type number
I2C-bus
frequency
Voltage range
Number of
addresses
per device
Interrupt
Reset
Total package
sink current
PCF8574/74A
100 kHz
2.5 V to 6 V
8
yes
no
80 mA
PCA8574/74A
400 kHz
2.3 V to 5.5 V
8
yes
no
200 mA
PCA9674/74A
1 MHz Fm+
2.3 V to 5.5 V
64
yes
no
200 mA
PCA9670
1 MHz Fm+
2.3 V to 5.5 V
64
no
yes
200 mA
PCA9672
1 MHz Fm+
2.3 V to 5.5 V
16
yes
yes
200 mA
PCA9670 replaces the interrupt output of the PCA9674 with hardware reset input to retain
the maximum number of addresses. PCA9672 replaces address A2 of the PCA9674 with
hardware reset input to retain the interrupt, but limit the number of addresses.
PCA9670
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PCA9670
NXP Semiconductors
Remote 8-bit I/O expander for Fm+ I2C-bus with reset
11. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD
supply voltage
Conditions
Min
Max
Unit
0.5
+6
V
IDD
supply current
-
100
mA
ISS
ground supply current
-
400
mA
VI
input voltage
VSS  0.5
5.5
V
II
input current
-
20
mA
IO
output current
-
50
mA
Ptot
total power dissipation
-
400
mW
P/out
power dissipation per output
-
100
mW
Tj(max)
maximum junction temperature
-
125
C
Tstg
storage temperature
65
+150
C
Tamb
ambient temperature
40
+85
C
[1]
[1]
operating
Total package (maximum) output current is 400 mA.
12. Thermal characteristics
Table 7.
PCA9670
Product data sheet
Thermal characteristics
Symbol
Parameter
Conditions
Typ
Unit
Rth(j-a)
thermal resistance from junction
to ambient
SO16 package
115
C/W
TSSOP16 package
160
C/W
HVQFN16 package
40
C/W
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PCA9670
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Remote 8-bit I/O expander for Fm+ I2C-bus with reset
13. Static characteristics
Table 8.
Static characteristics
VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supplies
VDD
supply voltage
2.3
-
5.5
V
IDD
supply current
Operating mode; no load;
VI = VDD or VSS; fSCL = 1 MHz;
AD0, AD1, AD2 = static H or L
-
266
500
A
Istb
standby current
Standby mode; no load;
VI = VDD or VSS; fSCL = 0 kHz
-
2.5
10
A
VPOR
power-on reset voltage
-
1.8
2.0
V
[1]
Input SCL; input/output SDA
VIL
LOW-level input voltage
0.5
-
+0.3VDD
V
VIH
HIGH-level input voltage
0.7VDD
-
5.5
V
IOL
LOW-level output current
VOL = 0.4 V; VDD = 2.3 V
20
-
-
mA
VOL = 0.4 V; VDD = 3.0 V
25
-
-
mA
VOL = 0.4 V; VDD = 4.5 V
30
-
-
mA
IL
leakage current
VI = VDD or VSS
1
-
+1
A
Ci
input capacitance
VI = VSS
-
4
10
pF
I/Os; P0 to P7
VIL
LOW-level input voltage
0.5
-
+0.3VDD
V
VIH
HIGH-level input voltage
0.7VDD
-
5.5
V
IOL
LOW-level output current
VOL = 0.5 V; VDD = 2.3 V
[2]
12
27
-
mA
VOL = 0.5 V; VDD = 3.0 V
[2]
17
35
-
mA
25
41
-
mA
-
-
200
mA
30
250
300
A
VOL = 0.5 V; VDD = 4.5 V
[2]
IOL(tot)
total LOW-level output current
VOL = 0.5 V; VDD = 4.5 V
[2]
IOH
HIGH-level output current
VOH = VSS
Itrt(pu)
transient boosted pull-up current VOH = VSS; see Figure 13
Ci
input capacitance
[3]
Co
output capacitance
[3]
0.5
1.0
-
mA
-
3
10
pF
-
3
10
pF
Input RESET
VIL
LOW-level input voltage
0.5
-
+0.8
V
VIH
HIGH-level input voltage
2
-
5.5
V
ILI
input leakage current
1
-
+1
A
Ci
input capacitance
-
3
5
pF
Inputs AD0, AD1, AD2
VIL
LOW-level input voltage
0.5
-
+0.3VDD
V
VIH
HIGH-level input voltage
0.7VDD
-
5.5
V
ILI
input leakage current
1
-
+1
A
Ci
input capacitance
-
3
5
pF
[1]
The power-on reset circuit resets the I2C-bus logic with VDD < VPOR and set all I/Os to logic 1 (with current source to VDD).
[2]
Each bit must be limited to a maximum of 25 mA and the total package limited to 200 mA due to internal busing limits.
PCA9670
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PCA9670
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Remote 8-bit I/O expander for Fm+ I2C-bus with reset
[3]
The value is not tested, but verified on sampling basis.
14. Dynamic characteristics
Table 9.
Dynamic characteristics
VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Standard mode
I2C-bus
Min
Max
Fast mode I2C-bus
Min
Max
Fast-mode Plus Unit
I2C-bus
Min
Max
fSCL
SCL clock frequency
0
100
0
400
0
1000
tBUF
bus free time between a
STOP and START
condition
4.7
-
1.3
-
0.5
-
kHz
s
tHD;STA
hold time (repeated)
START condition
4.0
-
0.6
-
0.26
-
s
tSU;STA
set-up time for a repeated
START condition
4.7
-
0.6
-
0.26
-
s
tSU;STO
set-up time for STOP
condition
4.0
-
0.6
-
0.26
-
s
tHD;DAT
data hold time
0
-
0
-
0
-
ns
0.3
3.45
0.1
0.9
0.05
0.45
s
300
-
50
-
50
450
ns
tVD;ACK
data valid acknowledge
time
[1]
tVD;DAT
data valid time
[2]
tSU;DAT
data set-up time
250
-
100
-
50
-
ns
tLOW
LOW period of the SCL
clock
4.7
-
1.3
-
0.5
-
s
tHIGH
HIGH period of the SCL
clock
4.0
-
0.6
-
0.26
-
s
tf
fall time of both SDA and
SCL signals
-
300
20 + 0.1Cb[3]
300
-
120
ns
tr
rise time of both SDA and
SCL signals
-
1000
20 + 0.1Cb[3]
300
-
120
ns
tSP
pulse width of spikes that
must be suppressed by
the input filter
-
50
-
50
-
50
ns
-
4
-
4
-
4
s
[4][5]
[6]
Port timing; CL  100 pF (see Figure 14 and Figure 13)
tv(Q)
data output valid time
tsu(D)
data input set-up time
0
-
0
-
0
-
s
th(D)
data input hold time
4
-
4
-
4
-
s
4
-
4
-
4
-
s
Reset timing (see Figure 22)
tw(rst)
reset pulse width
trec(rst)
reset recovery time
trst
reset time
0
-
0
-
0
-
s
100
-
100
-
100
-
s
[1]
tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
[2]
tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.
[3]
Cb = total capacitance of one bus line in pF.
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Remote 8-bit I/O expander for Fm+ I2C-bus with reset
[4]
A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to
bridge the undefined region SCL’s falling edge.
[5]
The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at
250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without
exceeding the maximum specified tf.
[6]
Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
START
condition
(S)
protocol
bit 7
MSB
(A7)
tSU;STA
tLOW
bit 6
(A6)
tHIGH
bit 0
(R/W)
acknowledge
(A)
STOP
condition
(P)
1 / fSCL
0.7 × VDD
SCL
0.3 × VDD
tBUF
tf
tr
0.7 × VDD
SDA
0.3 × VDD
tSU;DAT
tHD;STA
tHD;DAT
tVD;ACK
tVD;DAT
tSU;STO
002aab175
Rise and fall times refer to VIL and VIH.
Fig 21. I2C-bus timing diagram
ACK or read cycle
START
SCL
SDA
30 %
trst
RESET
50 %
50 %
50 %
trec(rst)
tw(rst)
trst
50 %
IOx_y
output off
002aac018
Fig 22. Reset timing
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Remote 8-bit I/O expander for Fm+ I2C-bus with reset
15. Package outline
HVQFN16: plastic thermal enhanced very thin quad flat package; no leads;
16 terminals; body 3 x 3 x 0.85 mm
A
B
D
SOT758-1
terminal 1
index area
A
E
A1
c
detail X
e1
C
1/2
e
e
5
y
y1 C
v M C A B
w M C
b
8
L
4
9
e
e2
Eh
1/2
e
12
1
16
terminal 1
index area
13
Dh
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
c
D (1)
Dh
E (1)
Eh
e
e1
e2
L
v
w
y
y1
mm
1
0.05
0.00
0.30
0.18
0.2
3.1
2.9
1.75
1.45
3.1
2.9
1.75
1.45
0.5
1.5
1.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT758-1
---
MO-220
---
EUROPEAN
PROJECTION
ISSUE DATE
02-03-25
02-10-21
Fig 23. Package outline SOT758-1 (HVQFN16)
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Remote 8-bit I/O expander for Fm+ I2C-bus with reset
SO16: plastic small outline package; 16 leads; body width 7.5 mm
SOT162-1
D
E
A
X
c
HE
y
v M A
Z
9
16
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
8
e
detail X
w M
bp
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
mm
2.65
0.3
0.1
2.45
2.25
0.25
0.49
0.36
0.32
0.23
10.5
10.1
7.6
7.4
1.27
10.65
10.00
1.4
1.1
0.4
1.1
1.0
0.25
0.25
0.1
0.01
0.019 0.013
0.014 0.009
0.41
0.40
0.30
0.29
0.05
0.419
0.043
0.055
0.394
0.016
inches
0.1
0.012 0.096
0.004 0.089
0.043
0.039
0.01
0.01
Z
(1)
0.9
0.4
0.035
0.004
0.016
θ
8o
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT162-1
075E03
MS-013
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 24. Package outline SOT162-1 (SO16)
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Remote 8-bit I/O expander for Fm+ I2C-bus with reset
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
E
D
A
X
c
y
HE
v M A
Z
9
16
Q
(A 3)
A2
A
A1
pin 1 index
θ
Lp
L
1
8
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.40
0.06
8o
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT403-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
MO-153
Fig 25. Package outline SOT403-1 (TSSOP16)
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Remote 8-bit I/O expander for Fm+ I2C-bus with reset
16. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling ensure that the appropriate precautions are taken as
described in JESD625-A or equivalent standards.
17. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
17.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
17.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
17.3 Wave soldering
Key characteristics in wave soldering are:
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Remote 8-bit I/O expander for Fm+ I2C-bus with reset
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
17.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 26) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 10 and 11
Table 10.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
 350
< 2.5
235
220
 2.5
220
220
Table 11.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 26.
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Remote 8-bit I/O expander for Fm+ I2C-bus with reset
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 26. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
PCA9670
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Remote 8-bit I/O expander for Fm+ I2C-bus with reset
18. Soldering: PCB footprints
Footprint information for reflow soldering of HVQFN16 package
SOT758-1
Hx
Gx
D
P
0.025
0.025
C
(0.105)
SPx
Hy
SPy tot
nSPx
Gy
SPy
nSPy
SLy
By
Ay
SPx tot
SLx
Bx
Ax
solder land
solder paste deposit
solder land plus solder paste
occupied area
nSPx
nSPy
2
2
Dimensions in mm
P
Ax
Ay
Bx
By
C
D
SLx
SLy
0.50
4.00
4.00
2.20
2.20
0.90
0.24
1.50
1.50
Issue date
SPx tot SPy tot
0.90
0.90
SPx
SPy
Gx
Gy
Hx
Hy
0.30
0.30
3.30
3.30
4.25
4.25
12-03-07
12-03-08
sot758-1_fr
Fig 27. PCB footprint for SOT758-1 (HVQFN16); reflow soldering
PCA9670
Product data sheet
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Remote 8-bit I/O expander for Fm+ I2C-bus with reset
Footprint information for reflow soldering of SO16 package
SOT162-1
Hx
Gx
P2
(0.125)
Hy
Gy
(0.125)
By
Ay
C
D2 (4x)
D1
P1
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1
1.270
P2
Ay
1.320 11.200
By
C
D1
D2
6.400
2.400
0.700
Gx
0.800 10.040
Gy
Hx
Hy
8.600 11.900 11.450
sot162-1_fr
Fig 28. PCB footprint for SOT162-1 (SO16); reflow soldering
PCA9670
Product data sheet
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PCA9670
NXP Semiconductors
Remote 8-bit I/O expander for Fm+ I2C-bus with reset
Footprint information for reflow soldering of TSSOP16 package
SOT403-1
Hx
Gx
P2
(0.125)
Hy
Gy
(0.125)
By
Ay
C
D2 (4x)
D1
P1
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1
P2
Ay
By
C
D1
D2
Gx
Gy
Hx
Hy
0.650
0.750
7.200
4.500
1.350
0.400
0.600
5.600
5.300
5.800
7.450
sot403-1_fr
Fig 29. PCB footprint for SOT403-1 (TSSOP16); reflow soldering
PCA9670
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Remote 8-bit I/O expander for Fm+ I2C-bus with reset
19. Abbreviations
Table 12.
Abbreviations
Acronym
Description
CDM
Charged-Device Model
CMOS
Complementary Metal-Oxide Semiconductor
ESD
ElectroStatic Discharge
GPIO
General Purpose Input/Output
HBM
Human Body Model
LED
Light Emitting Diode
IC
Integrated Circuit
I2C-bus
Inter IC bus
ID
Identification
LSB
Least Significant Bit
MSB
Most Significant Bit
PLC
Programmable Logic Controller
RAID
Redundant Array of Independent Disks
20. Revision history
Table 13.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCA9670 v.3
20130530
Product data sheet
-
PCA9670 v.2
Modifications:
•
•
•
Section 1 “General description” re-written
Section 2 “Features and benefits” re-written
Section 3 “Applications”:
– Added (new) third bullet, “Keypads”
– Added (new) eighth bullet, “Mobile devices”
•
•
•
•
•
•
Added Section 4.1 “Ordering options”
Figure 2 “Simplified schematic diagram of P0 to P7” modified: removed diode between “VDD” and “P0
to P7”; removed exclusive-OR gate and signal “to interrupt logic”
Section 7.1 “Device address”: re-written
Table 4 “PCA9670 address map” updated: added separate columns for “Write” and “Read” under
“Address byte value” column; added (new) column “7-bit hexadecimal address without R/W”
Section 7.2.1 “Software Reset”: added paragraph that follows Figure 9
Section 7.2.2 “Device ID (PCA9670 ID field)”:
– first bullet item following first paragraph changed from “8 bits with the manufacturer name” to
“12 bits with the manufacturer name”
– second bullet item re-written
– List item 6. on page 9 changed from “starting with the 8 manufacturer bits ... , followed by the 13
part identification bits” to “starting with the 12 manufacturer bits ... , followed by the 9 part
identification bits”
– Figure 10 “PCA9670 Device ID field” modified
– Figure 11 modified: added “Sr” bit
– added paragraph that follows Figure 11
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Remote 8-bit I/O expander for Fm+ I2C-bus with reset
Table 13.
Revision history …continued
Document ID
Modifications:
(continued)
Release date
•
•
•
•
•
•
•
•
Data sheet status
Change notice
Supersedes
Section 8.1 “Quasi-bidirectional I/O architecture” re-written
Section 8.2 “Writing to the port (Output mode)”, first paragraph: first, second and third sentences
re-written
Figure 13 “Write mode (output)” updated
Section 8.3 “Reading from a port (Input mode)” re-written
Figure 14 “Read input port register” updated: label corrected from “data into port” to “data at port”
Section 8.4 “Power-on reset”: second and third sentences re-written
Section 8.5 “RESET input”: added new third sentence
Section 9.3 “Acknowledge”:
– first paragraph: second and third sentences re-written
– second paragraph: third sentence re-written
•
Section 10.1 “Bidirectional I/O expander applications”, second paragraph, second sentence changed
from “use the PCA9671” to “use the PCA9672”
•
•
Added Section 10.2 “How to read and write to I/O expander (example)”
Section 10.3 “High current-drive load applications”:
– first paragraph re-written
– Figure 20 “High current-drive load application” modified: added resistors on P6 and P7 signals
•
•
•
•
Added Section 10.4 “Migration path”
Table 6 “Limiting values”: added Tj(max) limits
Added Section 12 “Thermal characteristics”
Table 8 “Static characteristics”:
– sub-section “I/Os; P0 to P7”: added VIL characteristic
– sub-section “I/Os; P0 to P7”: added VIH characteristic
– sub-section “Input RESET” is corrected by removing IOH row
•
•
Figure 21 “I2C-bus timing diagram” updated: added 0.7  VDD and 0.3  VDD reference lines
Added Section 18 “Soldering: PCB footprints”
PCA9670 v.2
20070717
Product data sheet
-
PCA9670 v.1
PCA9670 v.1
20060620
Objective data sheet
-
-
PCA9670
Product data sheet
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Remote 8-bit I/O expander for Fm+ I2C-bus with reset
21. Legal information
21.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
21.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
21.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PCA9670
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 30 May 2013
© NXP B.V. 2013. All rights reserved.
33 of 35
PCA9670
NXP Semiconductors
Remote 8-bit I/O expander for Fm+ I2C-bus with reset
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
21.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
22. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PCA9670
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 30 May 2013
© NXP B.V. 2013. All rights reserved.
34 of 35
PCA9670
NXP Semiconductors
Remote 8-bit I/O expander for Fm+ I2C-bus with reset
23. Contents
1
2
3
4
4.1
5
6
6.1
6.2
7
7.1
7.1.1
7.2
7.2.1
7.2.2
8
8.1
8.2
8.3
8.4
8.5
9
9.1
9.1.1
9.2
9.3
10
10.1
10.2
10.3
10.4
11
12
13
14
15
16
17
17.1
17.2
17.3
17.4
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Device address . . . . . . . . . . . . . . . . . . . . . . . . . 5
Address maps. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Software Reset Call, and device ID addresses 8
Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . 8
Device ID (PCA9670 ID field) . . . . . . . . . . . . . . 9
I/O programming . . . . . . . . . . . . . . . . . . . . . . . 11
Quasi-bidirectional I/O architecture . . . . . . . . 11
Writing to the port (Output mode) . . . . . . . . . . 12
Reading from a port (Input mode) . . . . . . . . . 13
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 13
RESET input . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Characteristics of the I2C-bus . . . . . . . . . . . . 14
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
START and STOP conditions . . . . . . . . . . . . . 14
System configuration . . . . . . . . . . . . . . . . . . . 15
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 15
Application design-in information . . . . . . . . . 16
Bidirectional I/O expander applications . . . . . 16
How to read and write to I/O expander
(example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
High current-drive load applications . . . . . . . . 17
Migration path . . . . . . . . . . . . . . . . . . . . . . . . . 17
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 18
Thermal characteristics . . . . . . . . . . . . . . . . . 18
Static characteristics. . . . . . . . . . . . . . . . . . . . 19
Dynamic characteristics . . . . . . . . . . . . . . . . . 20
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 22
Handling information. . . . . . . . . . . . . . . . . . . . 25
Soldering of SMD packages . . . . . . . . . . . . . . 25
Introduction to soldering . . . . . . . . . . . . . . . . . 25
Wave and reflow soldering . . . . . . . . . . . . . . . 25
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 25
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 26
Soldering: PCB footprints. . . . . . . . . . . . . . . . 28
19
20
21
21.1
21.2
21.3
21.4
22
23
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
31
33
33
33
33
34
34
35
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 30 May 2013
Document identifier: PCA9670
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