Data Sheet

PCA9500
8-bit I2C-bus and SMBus I/O port with 2-kbit EEPROM
Rev. 04 — 15 April 2009
Product data sheet
1. General description
The PCA9500 is an 8-bit I/O expander with an on-board 2-kbit EEPROM.
The I/O expander's eight quasi-bidirectional data pins can be independently assigned as
inputs or outputs to monitor board level status or activate indicator devices such as LEDs.
The system master writes to the I/O configuration bits in the same way as for the
PCF8574. The data for each input or output is kept in the corresponding Input or Output
register. The system master can read all registers.
The EEPROM can be used to store error codes or board manufacturing data for
read-back by application software for diagnostic purposes and is included in the I/O
expander package.
The PCA9500 has 3 address pins with internal pull-up resistors allowing up to 8 devices to
share the common two-wire I2C software protocol serial data bus. The fixed GPIO I2C-bus
address is the same as the PCF8574 and the fixed EEPROM I2C-bus address is the same
as the PCF8582C-2, so the PCA9500 appears as two separate devices to the bus master.
The PCA9500 supports hot insertion to facilitate usage in removable cards on backplane
systems.
The PCA9501 is an alternative to the functionally similar PCA9500 for systems where a
higher number of devices are required to share the same I2C-bus or an interrupt output is
required.
2. Features
n
n
n
n
n
n
n
n
n
n
n
n
n
n
8 general purpose input/output expander/collector
Drop-in replacement for PCF8574 with integrated 2-kbit EEPROM
Internal 256 × 8 EEPROM
Self timed write cycle
4 byte page write operation
I2C-bus and SMBus interface logic
Internal power-on reset
Noise filter on SCL/SDA inputs
3 address pins allowing up to 8 devices on the I2C-bus/SMBus
No glitch on power-up
Supports hot insertion
Power-up with all channels configured as inputs
Low standby current
Operating power supply voltage range of 2.5 V to 3.6 V
PCA9500
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with 2-kbit EEPROM
n 5 V tolerant inputs/outputs
n 0 Hz to 400 kHz clock frequency
n ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115 and 1000 V CDM per JESD22-C101
n Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
n Packages offered: SO16, TSSOP16, HVQFN16
3. Applications
n Board version tracking and configuration
n Board health monitoring and status reporting
n Multi-card systems in telecommunications, networking, and base station infrastructure
equipment
n Field recall and troubleshooting functions for installed boards
n General-purpose integrated I/O with memory
n Drop-in replacement for PCF8574 with integrated 2-kbit EEPROM
n Bus master sees GPIO and EEPROM as two separate devices
n Three hardware address pins allow up to 8 PCA9500s to be located in the same
I2C-bus/SMBus
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
PCA9500D
SO16
plastic small outline package; 16 leads;
body width 7.5 mm
SOT162-1
PCA9500PW
TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
PCA9500BS
HVQFN16
plastic thermal enhanced very thin quad flat package; SOT629-1
no leads; 16 terminals; body 4 × 4 × 0.85 mm
4.1 Ordering options
Table 2.
Ordering options
Type number
Topside mark
Temperature range
PCA9500D
PCA9500D
−40 °C to +85 °C
PCA9500PW
PCA9500
−40 °C to +85 °C
PCA9500BS
9500
−40 °C to +85 °C
PCA9500_4
Product data sheet
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Rev. 04 — 15 April 2009
2 of 26
PCA9500
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with 2-kbit EEPROM
5. Block diagram
PCA9500
300 kΩ
A0
A1
A2
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
8-bit
SCL
write pulse
INPUT
FILTER
SDA
INPUT/
OUTPUT
PORTS
read pulse
I2C-BUS/SMBus
CONTROL
VDD
POWER-ON
RESET
VSS
EEPROM
256 × 8
WC
002aae585
Fig 1.
Block diagram of PCA9500
6. Pinning information
6.1 Pinning
A0
1
16 VDD
A0
1
16 VDD
A1
2
15 SDA
A1
2
15 SDA
A2
3
14 SCL
A2
3
14 SCL
IO0
4
13 WC
IO0
4
IO1
5
12 IO7
IO1
5
IO2
6
11 IO6
IO2
6
11 IO6
IO3
7
10 IO5
IO3
7
10 IO5
VSS
8
9
VSS
8
PCA9500D
IO4
002aae582
Fig 2.
Pin configuration for SO16
PCA9500_4
Product data sheet
PCA9500PW
13 WC
12 IO7
9
IO4
002aae583
Fig 3.
Pin configuration for TSSOP16
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 15 April 2009
3 of 26
PCA9500
NXP Semiconductors
A2
1
IO0
2
13 SDA
14 VDD
16 A1
terminal 1
index area
15 A2
8-bit I2C-bus and SMBus I/O port with 2-kbit EEPROM
12 SCL
11 WC
PCA9500BS
7
8
IO5
9
IO4
4
6
IO2
VSS
10 IO7
5
3
IO3
IO1
IO6
002aae584
Transparent top view
Fig 4.
Pin configuration for HVQFN16
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
Description
SO16, TSSOP16
HVQFN16
A0
1
15
A1
2
16
A2
3
1
IO0
4
2
IO1
5
3
IO2
6
4
IO3
7
5
IO4
9
7
IO5
10
8
IO6
11
9
IO7
12
10
VSS
8
6[1]
quasi-bidirectional I/O pins
supply ground
WC
13
11
active LOW write control pin
SCL
14
12
I2C-bus serial clock
SDA
15
13
I2C-bus serial data
VDD
16
14
supply voltage
[1]
HVQFN16 package supply ground is connected to both VSS pin and exposed center pad. VSS pin must be
connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level
performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the
board and for proper heat conduction through the board, thermal vias need to be incorporated in the
printed-circuit board in the thermal pad region.
PCA9500_4
Product data sheet
address lines (internal pull-up)
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 15 April 2009
4 of 26
PCA9500
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with 2-kbit EEPROM
7. Functional description
Refer also to Figure 1 “Block diagram of PCA9500”.
VDD
write pulse
100 µA
D
data from shift register
Q
FF
IO0 to IO7
CI
S
power-on reset
VSS
D
Q
FF
CI
read pulse
S
to interrupt logic
data to shift register
002aae588
Fig 5.
Simplified schematic diagram of each I/O
7.1 Device addressing
Following a START condition, the bus master must output the address of the slave it is
accessing. The address of the PCA9500 is shown in Figure 6. Internal pull-up resistors
are incorporated on the hardware selectable address pins.
The last bit of the address byte defines the operation to be performed. When set to logic 1
a read is selected, while a logic 0 selects a write operation.
slave address
0
1
0
0
fixed
A2
slave address
A1
A0 R/W
hardware
programmable
1
0
1
fixed
002aae589
a. I/O expander
Fig 6.
0
A2
A1
A0 R/W
hardware
programmable
002aae590
b. Memory
PCA9500 slave addresses
7.2 Control register
The PCA9500 contains a single 8-bit register called the Control register, which can be
written and read via the I2C-bus. This register is sent after a successful acknowledgment
of the slave address. It contains the I/O operation information.
PCA9500_4
Product data sheet
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Rev. 04 — 15 April 2009
5 of 26
PCA9500
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with 2-kbit EEPROM
7.3 I/O operations
(Refer also to Figure 5.)
Each of the PCA9500's eight I/Os can be independently used as an input or output.
Output data is transmitted to the port by the I/O Write mode (see Figure 7). Input I/O data
is transferred from the port to the microcontroller by the Read mode (see Figure 8).
SCL
1
2
3
4
5
6
7
8
9
slave address (I/O expander)
SDA S
0
1
0
data to port
0 A2 A1 A0 0
START condition
A
R/W
data to port
DATA 1
A
acknowledge
from slave
DATA 2
A
acknowledge
from slave
acknowledge
from slave
write to port
tv(Q)
tv(Q)
data out from port
DATA 1 VALID
DATA 2 VALID
002aae591
Fig 7.
I/O Write mode (output)
SCL
1
2
3
4
5
6
7
8
9
slave address (I/O expander)
SDA S
0
1
0
0 A2 A1 A0 1
START condition
R/W
data from port
A
DATA 1
data from port
A
DATA 4
acknowledge
from master
acknowledge
from slave
no acknowledge
from master
1
P
STOP
condition
read from
port
DATA 2
data into
port
DATA 1
DATA 3
th(D)
DATA 4
tsu(D)
002aae592
Fig 8.
I/O Read mode (input)
PCA9500_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 15 April 2009
6 of 26
PCA9500
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with 2-kbit EEPROM
7.3.1 Quasi-bidirectional I/Os
A quasi-bidirectional I/O can be used as an input or output without the use of a control
signal for data direction. At power-on the I/Os are HIGH. In this mode, only a current
source to VDD is active. An additional strong pull-up to VDD allows fast rising edges into
heavily loaded outputs. These devices turn on when an output is written HIGH, and are
switched off by the negative edge of SCL. The I/Os should be HIGH before being used as
inputs. See Figure 9.
SCL
1
2
3
4
5
6
7
8
9
slave address (I/O expander)
SDA S
0
1
0
0 A2 A1 A0 0
START condition
R/W
data to port
A
1
acknowledge
from slave
STOP
condition
data to port
A
IO3
acknowledge
from slave
0
A
P
acknowledge
from slave
IO3
IO3 output voltage
IO3 pull-up output current
IOHt
IOH
002aae593
Fig 9.
Transient pull-up current (IOHt) while IO3 changes from LOW to HIGH and back to LOW
7.4 Memory operations
7.4.1 Write operations
Write operations require an additional address field to indicate the memory address
location to be written. The address field is eight bits long, providing access to any one of
the 256 words of memory. There are two types of write operations, ‘byte write’ and
‘page write’.
Write operation is possible when the Write Control pin (WC) is put at a LOW logic level (0).
When this control signal is set at 1, write operation is not possible and data in the memory
is protected.
‘Byte write’ and ‘page write’ explained below assume that WC is set to 0.
7.4.1.1
Byte write
To perform a byte write the START condition is followed by the memory slave address and
the R/W bit set to 0. The PCA9500 will respond with an acknowledge and then consider
the next eight bits sent as the word address and the eight bits after the word address as
the data. The PCA9500 will issue an acknowledge after the receipt of both the word
address and the data. To terminate the data transfer the master issues the STOP
condition, initiating the internal write cycle to the non-volatile memory. Only write and read
operations to the quasi-bidirectional I/Os are allowed during the internal write cycle.
PCA9500_4
Product data sheet
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Rev. 04 — 15 April 2009
7 of 26
PCA9500
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with 2-kbit EEPROM
slave address (memory)
SDA S
1
0
1
word address
0 A2 A1 A0 0
START condition
R/W
data
A
A
A
acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
P
STOP condition.
Write to the memory
is performed.
002aae594
Fig 10. Byte write
7.4.1.2
Page write
A page write is initiated in the same way as the byte write. If after sending the first word of
data, the STOP condition is not received, the PCA9500 considers subsequent words as
data. After each data word the PCA9500 responds with an acknowledge and the two least
significant bits of the memory address field are incremented. Should the master not send
a STOP condition after four data words, the address counter will return to its initial value
and overwrite the data previously written. After the receipt of the STOP condition the
inputs will behave as with the byte write during the internal write cycle.
slave address (memory)
SDA S
1
0
1
word address
0 A2 A1 A0 0
START condition
R/W
data to memory
A
A
acknowledge
from slave
acknowledge
from slave
DATA n
data to memory
A
acknowledge
from slave
DATA n + 3
A
P
acknowledge
from slave
STOP condition.
Write to the memory is performed.
002aae595
Fig 11. Page write
7.4.2 Read operations
PCA9500 read operations are initiated in an identical manner to write operations with the
exception that the memory slave address R/W bit is set to ‘1’. There are three types of
read operations: current address read, random read and sequential read.
7.4.2.1
Current address read
The PCA9500 contains an internal address counter that increments after each read or
write access and as a result, if the last word accessed was at address ‘n’, then the
address counter contains the address ‘n + 1’.
When the PCA9500 receives its memory slave address with the R/W bit set to one it
issues an acknowledge and uses the next eight clocks to transmit the data contained at
the address stored in the address counter. The master ceases the transmission by issuing
the STOP condition after the eighth bit. There is no ninth clock cycle for the acknowledge.
See Figure 12.
PCA9500_4
Product data sheet
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Rev. 04 — 15 April 2009
8 of 26
PCA9500
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with 2-kbit EEPROM
slave address (memory)
SDA S
1
0
1
data from memory
0 A2 A1 A0 1
START condition
R/W
A
P
acknowledge
from slave
STOP condition
002aae596
Fig 12. Current address read
7.4.2.2
Random read
The PCA9500's random read mode allows the address to be read from to be specified by
the master. This is done by performing a dummy write to set the address counter to the
location to be read. The master must perform a byte write to the address location to be
read, but instead of transmitting the data after receiving the acknowledge from the
PCA9500, the master re-issues the START condition and memory slave address with the
R/W bit set to one. The PCA9500 will then transmit an acknowledge and use the next
eight clock cycles to transmit the data contained in the addressed location. The master
ceases the transmission by issuing the STOP condition after the eighth bit, omitting the
ninth clock cycle acknowledge.
slave address (memory)
SDA S
1
0
1
word address
0 A2 A1 A0 0
START condition
R/W
A
slave address (memory)
A
acknowledge
from slave
acknowledge
from slave
S
1
0
1
data from memory
0 A2 A1 A0 1
START condition
A
P
STOP
condition
R/W
acknowledge
from slave
002aae597
Fig 13. Random read
7.4.2.3
Sequential read
The PCA9500 sequential read is an extension of either the current address read or
random read. If the master does not issue a STOP condition after it has received the
eighth data bit, but instead issues an acknowledge, the PCA9500 will increment the
address counter and use the next eight cycles to transmit the data from that location. The
master can continue this process to read the contents of the entire memory. Upon
reaching address 255 the counter will return to address 0 and continue transmitting data
until a STOP condition is received. The master ceases the transmission by issuing the
STOP condition after the eighth bit, omitting the ninth clock cycle acknowledge.
slave address (memory)
SDA S
1
0
1
data from memory
0 A2 A1 A0 1
START condition
R/W
A
DATA n
acknowledge
from slave
data from memory
A
DATA n + 1
acknowledge
from master
data from memory
A
acknowledge
from master
DATA n + X
P
STOP
condition
002aae598
Fig 14. Sequential read
PCA9500_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 15 April 2009
9 of 26
PCA9500
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with 2-kbit EEPROM
8. Characteristics of the I2C-bus
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 15).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
mba607
Fig 15. Bit transfer
8.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 16).
SDA
SCL
S
P
START condition
STOP condition
mba608
Fig 16. Definition of START and STOP conditions
PCA9500_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 15 April 2009
10 of 26
PCA9500
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with 2-kbit EEPROM
8.2 System configuration
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 17).
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
002aaa381
Fig 17. System configuration
8.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up time and hold
time must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from master
1
S
START
condition
2
8
9
clock pulse for
acknowledgement
002aaa987
Fig 18. Acknowledgement on the I2C-bus
PCA9500_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 15 April 2009
11 of 26
PCA9500
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with 2-kbit EEPROM
9. Application design-in information
A central processor/controller typically located on the system main board can use the
400 kHz I2C-bus/SMBus to poll the PCA9500 devices located on the system cards for
status or version control type of information. The PCA9500 may be programmed at
manufacturing to store information regarding board build, firmware version, manufacturer
identification, configuration option data, and so on. Alternately, these devices can be used
as convenient interface for board configuration, thereby utilizing the I2C-bus/SMBus as an
intra-system communication bus.
up to
8 cards
I2C-bus
CPU
OR
µC
ASIC
I2C-bus
I2C-bus
BACKPLANE
configuration control
I2C-bus
PCA9500
I2C-bus
CONTROL
I2C-bus
GPIO
EEPROM
monitoring
and
control
INPUTS
ALARM
LEDs
card ID, subroutines, configuration data, or revision history
002aae586
Fig 19. PCA9500 used as interface for board configuration
PCA9500_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 15 April 2009
12 of 26
PCA9500
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with 2-kbit EEPROM
VDD
10 kΩ
10 kΩ
VDD
10 kΩ
(optional)
SUB-SYSTEM 1
(e.g., temp sensor)
2 kΩ
VDD
INT
MASTER
CONTROLLER
SCL
SCL
IO0
SDA
SDA
IO1
PCA9500
SUB-SYSTEM 2
(e.g., counter)
IO2
RESET
IO3
VSS
IO4
A
controlled
switch
(e.g., CBT device)
enable
IO5
A2
B
IO6
A1
IO7
A0
VSS
SUB-SYSTEM 3
(e.g., alarm system)
ALARM
VDD
002aae599
GPIO device address configured as 0100 100x for this example.
EEPROM device address configured as 1010 100x for this example.
IO0, IO2, IO3 configured as outputs.
IO1, IO4, IO5 configured as inputs.
IO6, IO7 are not used and must be configured as outputs.
Fig 20. Typical application
10. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD
Conditions
Min
Max
Unit
supply voltage
−0.5
+4.0
V
VI
input voltage
VSS − 0.5
5.5
V
II
input current
−20
+20
mA
IO
output current
−25
+25
mA
IDD
supply current
−100
+100
mA
ISS
ground supply current
−100
+100
mA
Ptot
total power dissipation
-
400
mW
P/out
power dissipation per output
-
100
mW
Tstg
storage temperature
−65
+150
°C
Tamb
ambient temperature
−40
+85
°C
operating
PCA9500_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 15 April 2009
13 of 26
PCA9500
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with 2-kbit EEPROM
11. Static characteristics
Table 5.
Static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2.5
3.3
3.6
V
Supply
VDD
supply voltage
IDDQ
standby current
-
-
60
µA
IDD1
supply current read
-
-
1
mA
IDD2
supply current write
-
-
2
mA
VPOR
power-on reset voltage
-
-
2.4
V
A0, A1, A2, WC = HIGH
Input SCL; input/output SDA
VIL
LOW-level input voltage
−0.5
-
+0.3VDD
V
VIH
HIGH-level input voltage
0.7VDD
-
5.5
V
IOL
LOW-level output current
VOL = 0.4 V
3
-
-
mA
ILI
input leakage current
VI = VDD or VSS
−1
-
+1
µA
Ci
input capacitance
VI = VSS
-
-
7
pF
-
+0.3VDD
V
I/O expander port
VIL
LOW-level input voltage
−0.5
VIH
HIGH-level input voltage
0.7VDD
-
5.5
V
IIHL(max)
input current through protection diodes
−400
-
+400
µA
IOL
LOW-level output current
VOL = 1 V
10
25
-
mA
IOH
HIGH-level output current
VOH = VSS
30
100
300
µA
[1]
IOHt
transient pull-up current
-
2
-
mA
Ci
input capacitance
-
-
10
pF
Co
output capacitance
-
-
10
pF
Address inputs A0, A1, A2; WC input
VIL
LOW-level input voltage
−0.5
-
+0.3VDD
V
VIH
HIGH-level input voltage
0.7VDD
-
5.5
V
ILI
input leakage current
VI = VDD
−1
-
+1
µA
pull-up; VI = VSS
10
25
100
µA
[1]
Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA.
PCA9500_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 15 April 2009
14 of 26
PCA9500
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with 2-kbit EEPROM
002aad307
20
IOH
(µA)
−40
002aad308
20
VDD = 2.5 V
2.7 V
3.0 V
3.3 V
3.6 V
VDD = 2.5 V
2.7 V
3.0 V
3.3 V
3.6 V
IOH
(µA)
−20
−60
−100
−100
−160
−140
0
1.2
2.4
3.6
0
1.2
VOH (V)
2.4
3.6
VOH (V)
a. Tamb = −40 °C
b. Tamb = 25 °C
002aad309
20
VDD = 2.5 V
2.7 V
3.0 V
3.3 V
3.6 V
IOH
(µA)
−20
−60
−100
−140
0
1.2
2.4
3.6
VOH (V)
c. Tamb = 85 °C
Fig 21. VOH versus IOH
Remark: Rapid fall-off in VOH at current inception is due to a diode that provides 5 V
overvoltage protection for the GPIO I/O pins. When the GPIO I/O are being used as
inputs, the internal current source VOH should be evaluated to determine if external pull-up
resistors are required to provide sufficient VIH threshold noise margin.
PCA9500_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 15 April 2009
15 of 26
PCA9500
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with 2-kbit EEPROM
12. Dynamic characteristics
Table 6.
Dynamic characteristics
Symbol
I2C-bus
Parameter
timing[1]
Conditions
Min
Typ
Max
Unit
(see Figure 22)
fSCL
SCL clock frequency
-
-
400
kHz
tSP
pulse width of spikes that must be
suppressed by the input filter
-
-
50
ns
tBUF
bus free time between a STOP and START
condition
1.3
-
-
µs
tSU;STA
set-up time for a repeated START condition
0.6
-
-
µs
tHD;STA
hold time (repeated) START condition
0.6
-
-
µs
tr
rise time of both SDA and SCL signals
-
-
0.3
µs
tf
fall time of both SDA and SCL signals
-
-
0.3
µs
tSU;DAT
data set-up time
250
-
-
ns
tHD;DAT
data hold time
0
-
-
ns
tVD;DAT
data valid time
-
-
1.0
µs
tSU;STO
set-up time for STOP condition
0.6
-
-
µs
SCL LOW to
data output
Port timing
tv(Q)
data output valid time
CL ≤ 100 pF
-
-
4
µs
tsu(D)
data input set-up time
CL ≤ 100 pF
0
-
-
µs
th(D)
data input hold time
CL ≤ 100 pF
4
-
-
µs
Power-up timing
tpu(R)
tpu(W)
read power-up time
[2]
-
-
1
ms
write power-up time
[2]
-
-
5
ms
[3]
-
5
10
ms
Write cycle limits (see Figure 23)
Tcy(W)
write cycle time
[1]
All the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and VIH with an input
voltage swing of VSS to VDD.
[2]
tpu(R) and tpu(W) are the delays required from the time VDD is stable until the specified operation can be initiated. These parameters are
guaranteed by design.
[3]
Tcy(W) is the maximum time that the device requires to perform the internal write operation.
Table 7.
Non-volatile storage specifications
Parameter
Specification
memory cell data retention
10 years minimum
number of memory cell write cycles
100,000 cycles minimum
PCA9500_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 15 April 2009
16 of 26
PCA9500
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with 2-kbit EEPROM
START
condition
(S)
protocol
bit 7
MSB
(A7)
tSU;STA
tLOW
bit 6
(A6)
tHIGH
bit 0
(R/W)
acknowledge
(A)
STOP
condition
(P)
1/f
SCL
SCL
tBUF
tr
tf
SDA
tHD;STA
tSU;DAT
tVD;DAT
tHD;DAT
tVD;ACK
tSU;STO
002aab175
Fig 22. I2C-bus timing
SCL
SDA
8th bit
ACK
word n
memory
address
Tcy(W)
STOP
condition
START
condition
002aad310
Fig 23. Write cycle timing
PCA9500_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 15 April 2009
17 of 26
PCA9500
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with 2-kbit EEPROM
13. Package outline
SO16: plastic small outline package; 16 leads; body width 7.5 mm
SOT162-1
D
E
A
X
c
HE
y
v M A
Z
16
9
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
8
1
e
detail X
w M
bp
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
mm
2.65
0.3
0.1
2.45
2.25
0.25
0.49
0.36
0.32
0.23
10.5
10.1
7.6
7.4
1.27
10.65
10.00
1.4
1.1
0.4
1.1
1.0
0.25
0.25
0.1
0.01
0.019 0.013
0.014 0.009
0.41
0.40
0.30
0.29
0.05
0.419
0.043
0.055
0.394
0.016
inches
0.1
0.012 0.096
0.004 0.089
0.043
0.039
0.01
0.01
Z
(1)
0.9
0.4
0.035
0.004
0.016
θ
8o
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT162-1
075E03
MS-013
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 24. Package outline SOT162-1 (SO16)
PCA9500_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 15 April 2009
18 of 26
PCA9500
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with 2-kbit EEPROM
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
E
D
A
X
c
y
HE
v M A
Z
9
16
Q
(A 3)
A2
A
A1
pin 1 index
θ
Lp
L
1
8
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.40
0.06
8
o
0
o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT403-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
MO-153
Fig 25. Package outline SOT403-1 (TSSOP16)
PCA9500_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 15 April 2009
19 of 26
PCA9500
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with 2-kbit EEPROM
HVQFN16: plastic thermal enhanced very thin quad flat package; no leads;
16 terminals; body 4 x 4 x 0.85 mm
A
B
D
SOT629-1
terminal 1
index area
A A
1
E
c
detail X
e1
C
1/2 e
e
8
y
y1 C
v M C A B
w M C
b
5
L
9
4
e
e2
Eh
1/2 e
1
12
terminal 1
index area
16
13
X
Dh
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A(1)
max.
A1
b
1
0.05
0.00
0.38
0.23
c
D (1)
Dh
E (1)
Eh
0.2
4.1
3.9
2.25
1.95
4.1
3.9
2.25
1.95
e
e1
0.65
1.95
e2
L
v
w
y
y1
1.95
0.75
0.50
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT629-1
---
MO-220
---
EUROPEAN
PROJECTION
ISSUE DATE
01-08-08
02-10-22
Fig 26. Package outline SOT629-1 (HVQFN16)
PCA9500_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 15 April 2009
20 of 26
PCA9500
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with 2-kbit EEPROM
14. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
PCA9500_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 15 April 2009
21 of 26
PCA9500
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with 2-kbit EEPROM
14.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 27) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 8 and 9
Table 8.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 9.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 27.
PCA9500_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 15 April 2009
22 of 26
PCA9500
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with 2-kbit EEPROM
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 27. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
15. Abbreviations
Table 10.
Abbreviations
Acronym
Description
ASIC
Application Specific Integrated Circuit
CBT
Cross-Bar Technology
CDM
Charged-Device Model
CPU
Central Processing Unit
EEPROM
Electrically Erasable Programmable Read-Only Memory
ESD
ElectroStatic Discharge
FF
Flip-Flop
GPIO
General Purpose Input/Output
I2C-bus
Inter-Integrated Circuit bus
I/O
Input/Output
HBM
Human Body Model
LED
Light-Emitting Diode
MM
Machine Model
SMBus
System Management Bus
PCA9500_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 15 April 2009
23 of 26
PCA9500
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with 2-kbit EEPROM
16. Revision history
Table 11.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCA9500_4
20090415
Product data sheet
-
PCA9500_3
Modifications:
•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•
•
Legal texts have been adapted to the new company name where appropriate.
Table 3 “Pin description”:
– added Table note [1] and its reference at HVQFN16 pin 6
– changed naming convention for pins I/On to “IOn”
•
•
Figure 7 “I/O Write mode (output)”: changed symbol “tpv” to “tv(Q)”
Figure 8 “I/O Read mode (input)”:
– changed symbol “tph” to “th(D)”
– changed symbol “tps” to “tsu(D)”
•
Table 4 “Limiting values”:
– changed symbol “VCC” to “VDD”
– changed parameter for ISS from “supply current” to “ground supply current”
– changed symbol “PO” to “P/out”
– changed parameter for Tamb from “operating temperature” to “ambient temperature”;
placed “operating” in Conditions column
•
Table 5 “Static characteristics”:
– added reference to Table note [1] at IOL in sub-section “I/O expander port”
•
Table 6 “Dynamic characteristics”:
– sub-section “I2C-bus timing”: changed symbol/parameter from “tSW, tolerable spike
width on bus” to “tSP, pulse width of spikes that must be suppressed by the input filter”
– sub-section “Port timing”: changed symbol “tpv” to “tv(Q)”
– sub-section “Port timing”: changed symbol “tps” to “tsu(D)”
– sub-section “Port timing”: changed symbol “tph” to “th(D)”
– sub-section “Power-up timing”: changed symbol “tPUR” to “tpu(R)”
– sub-section “Power-up timing”: changed symbol “tPUW” to “tpu(W)”
– sub-section “Write cycle limits”: changed symbol “tWR” to “Tcy(W)”
•
•
•
Figure 23 “Write cycle timing”: changed symbol “tWR” to “Tcy(W)”
added Section 15 “Abbreviations”
updated soldering information
PCA9500_3
(9397 750 14134)
20040930
Product data sheet
-
PCA9500_2
PCA9500_2
20030627
Product data
853-2369 30018
of 2003 Jun 11
PCA9500_1
PCA9500_1
20020927
Product data
853-2369 28875
of 2002 Sep 27
-
PCA9500_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 15 April 2009
24 of 26
PCA9500
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with 2-kbit EEPROM
17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
17.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PCA9500_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 15 April 2009
25 of 26
PCA9500
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with 2-kbit EEPROM
19. Contents
1
2
3
4
4.1
5
6
6.1
6.2
7
7.1
7.2
7.3
7.3.1
7.4
7.4.1
7.4.1.1
7.4.1.2
7.4.2
7.4.2.1
7.4.2.2
7.4.2.3
8
8.1
8.1.1
8.2
8.3
9
10
11
12
13
14
14.1
14.2
14.3
14.4
15
16
17
17.1
17.2
17.3
17.4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Device addressing . . . . . . . . . . . . . . . . . . . . . . 5
Control register . . . . . . . . . . . . . . . . . . . . . . . . . 5
I/O operations . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Quasi-bidirectional I/Os . . . . . . . . . . . . . . . . . . 7
Memory operations . . . . . . . . . . . . . . . . . . . . . . 7
Write operations . . . . . . . . . . . . . . . . . . . . . . . . 7
Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Page write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Read operations . . . . . . . . . . . . . . . . . . . . . . . . 8
Current address read . . . . . . . . . . . . . . . . . . . . 8
Random read . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Sequential read. . . . . . . . . . . . . . . . . . . . . . . . . 9
Characteristics of the I2C-bus. . . . . . . . . . . . . 10
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
START and STOP conditions . . . . . . . . . . . . . 10
System configuration . . . . . . . . . . . . . . . . . . . 11
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 11
Application design-in information . . . . . . . . . 12
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 13
Static characteristics. . . . . . . . . . . . . . . . . . . . 14
Dynamic characteristics . . . . . . . . . . . . . . . . . 16
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18
Soldering of SMD packages . . . . . . . . . . . . . . 21
Introduction to soldering . . . . . . . . . . . . . . . . . 21
Wave and reflow soldering . . . . . . . . . . . . . . . 21
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 21
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 22
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 24
Legal information. . . . . . . . . . . . . . . . . . . . . . . 25
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 25
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
18
19
Contact information . . . . . . . . . . . . . . . . . . . . 25
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 15 April 2009
Document identifier: PCA9500_4
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