Data Sheet

PCA9558
8-bit I2C-bus and SMBus I/O port with 5-bit multiplexed/1-bit
latched 6-bit I2C-bus EEPROM DIP switch and 2-kbit EEPROM
Rev. 5 — 25 June 2012
Product data sheet
1. General description
The PCA9558 is a highly integrated, multi-function device that is composed of a 5-bit
multiplexed/1-bit latched 6-bit I2C-bus/SMBus EEPROM DIP switch, an 8-bit I/O expander
and a 2-kbit serial EEPROM with write protect. The PCA9558 integrates these commonly
used components into a single chip to reduce component count and board space
requirements and is useful in computer, server and telecom/networking applications.
• Multiplexed/latched EEPROM DIP switch — used to select digital information
between a set of 5 bits of default hardware inputs and an alternative set of inputs
provided by the I2C-bus/SMBus interface and stored in the EEPROM. Examples of
this type of selection include processor voltage configuration or processor vendor
identification (VID). The multiplexed/latched EEPROM can also be used to replace
DIP switches or jumpers, since the settings can be easily changed via I2C-bus/SMBus
without having to power down the equipment to open the cabinet. The non-volatile
memory retains the most current setting selected before the power is turned off.
• 8-bit I/O expander — used to control, monitor or collect remote information or power
LEDs. Monitored or collected information can be read through the I2C-bus/SMBus or
can be stored in the internal EEPROM.
• 2-kbit serial EEPROM — used to store information such as card identification or
revision/maintenance history on every motherboard/line card and can be read or
written via I2C-bus/SMBus when required.
The PCA9558 has one address pin, allowing up to two devices to be placed on the same
I2C-bus or SMBus.
2. Features and benefits
 5-bit 2-to-1 multiplexer, 1-bit latch DIP switch
 6-bit MUX_OUTx and NON_MUXED_OUT EEPROM programmable and readable via
I2C-bus
 5 V tolerant open-drain MUX_OUTx and NON_MUXED_OUT outputs
 Active LOW override input forces all MUX_OUTx outputs to logic 0
 I2C-bus readable MUX_INx inputs
 5 V tolerant open-drain IOx pins, power-up default as outputs
 One address pin, allowing up to two devices on the I2C-bus
 Active LOW reset input with internal pull-up for the eight I/O pins
 2048-bit EEPROM programmable and readable via the I2C-bus or I/Os
 Operating power supply voltage range of 3.0 V to 3.6 V
 SMBus compliance with fixed 3.3 V levels
PCA9558
NXP Semiconductors
8-bit I2C-bus/SMBus I/O port
 2.5 V to 5 V tolerant inputs
 ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
3. Applications





Board version tracking and configuration
Board health monitoring and status reporting
Multi-card systems in telecom, networking and base station infrastructure equipment
Field recall and troubleshooting functions for installed boards
General-purpose integrated I/O with DIP switch and memory
4. Ordering information
Table 1.
Ordering information
Type number
PCA9558PW
PCA9558
Product data sheet
Topside mark
PCA9558DH
Temperature
range
Package
Name
Description
Version
0 °C to 70 °C
TSSOP28
plastic thin shrink small outline package;
28 leads; body width 4.4 mm
SOT361-1
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 25 June 2012
© NXP B.V. 2012. All rights reserved.
2 of 29
PCA9558
NXP Semiconductors
8-bit I2C-bus/SMBus I/O port
5. Block diagram
PCA9558
MUX_SELECT
MUX_OUT_LOW
6-bit EEPROM
LATCH
NMO
NON_MUXED_OUT
5
MUX_INA to
MUX_INE
1
MUX_OUTA
MUX_OUTB
5-BIT
2 TO 1
MUX
A0
SCL
SDA
I2C-BUS
INTERFACE
LOGIC
MUX_OUTD
INPUT
FILTER
MUX_OUTE
0
5
VDD
MUX_OUTC
I2C-BUS
CONTROL
LOGIC
POWER-ON
RESET
VSS
8
WP
256-BYTE
EEPROM
GPIO
IO0 to IO7
IO_OUT_LOW
002aad366
Fig 1.
Block diagram of PCA9558
PCA9558
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 25 June 2012
© NXP B.V. 2012. All rights reserved.
3 of 29
PCA9558
NXP Semiconductors
8-bit I2C-bus/SMBus I/O port
6. Pinning information
6.1 Pinning
SCL
1
28 VDD
SDA
2
27 WP
IO_OUT_LOW
3
26 MUX_OUT_LOW
A0
4
25 NON_MUXED_OUT
MUX_INA
5
24 MUX_OUTA
MUX_INB
6
23 MUX_OUTB
MUX_INC
7
MUX_IND
8
MUX_INE
9
PCA9558PW
22 MUX_OUTC
21 MUX_OUTD
20 MUX_OUTE
VSS 10
19 MUX_SELECT
IO0 11
18 IO7
IO1 12
17 IO6
IO2 13
16 IO5
IO3 14
15 IO4
002aad365
Fig 2.
Pin configuration for TSSOP28
6.2 Pin description
Table 2.
PCA9558
Product data sheet
Pin description
Symbol
Pin
Description
SCL
1
serial I2C-bus clock
SDA
2
serial bidirectional I2C-bus data
IO_OUT_LOW
3
active LOW control forces all GPIO to logic 0 outputs
A0
4
A0 address
MUX_INA
5
external input A to multiplexer
MUX_INB
6
external input B to multiplexer
MUX_INC
7
external input C to multiplexer
MUX_IND
8
external input D to multiplexer
MUX_INE
9
external input E to multiplexer
VSS
10
ground
IO0
11
general purpose input/output 0 (open-drain output)
IO1
12
general purpose input/output 1 (open-drain output)
IO2
13
general purpose input/output 2 (open-drain output)
IO3
14
general purpose input/output 3 (open-drain output)
IO4
15
general purpose input/output 4 (open-drain output)
IO5
16
general purpose input/output 5 (open-drain output)
IO6
17
general purpose input/output 6 (open-drain output)
IO7
18
general purpose input/output 7 (open-drain output)
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 25 June 2012
© NXP B.V. 2012. All rights reserved.
4 of 29
PCA9558
NXP Semiconductors
8-bit I2C-bus/SMBus I/O port
Table 2.
Pin description …continued
Symbol
Pin
Description
MUX_SELECT
19
active LOW select of MUX_INx inputs or EEPROM contents
for MUX_OUTx outputs
MUX_OUTE
20
open-drain multiplexed output E
MUX_OUTD
21
open-drain multiplexed output D
MUX_OUTC
22
open-drain multiplexed output C
MUX_OUTB
23
open-drain multiplexed output B
MUX_OUTA
24
open-drain multiplexed output A
NON_MUXED_OUT
25
open-drain outputs from non-volatile memory
MUX_OUT_LOW
26
active LOW control forces all MUX outputs to logic 0
WP
27
active HIGH EEPROM write protect
VDD
28
power supply (3.0 V to 3.6 V)
7. Functional description
Refer to Figure 1 “Block diagram of PCA9558”.
7.1 I2C-bus interface
Communicating with this device is initiated by sending a valid address on the I2C-bus. The
address format (see Figure 3) has 6 fixed bits and one user-programmable bit followed by
a 1-bit read/write value which determines the direction of the data transfer.
MSB
1
LSB
0
0
1
1
1
fixed
A0 R/W
hardware
selectable
002aad367
Fig 3.
I2C-bus address byte
Following the address and acknowledge bit are 8 data bits which, depending on the
read/write bit in the address, will read data from or write data to the EEPROM. Data will be
written to the register if the read/write bit is logic 0 and the WP input is logic 0. Data will be
read from the register if the bit is logic 1. The four high-order bits are latched outputs,
while the four low order bits are multiplexed outputs (Figure 5).
Remark: To ensure data integrity, the EEPROM must be internally write protected when
VDD to the I2C-bus is powered down or VDD to the component is dropped below normal
operating levels.
D7
D6
D5
D4
D3
D2
D1
D0
002aad368
Fig 4.
PCA9558
Product data sheet
Command byte
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 25 June 2012
© NXP B.V. 2012. All rights reserved.
5 of 29
PCA9558
NXP Semiconductors
8-bit I2C-bus/SMBus I/O port
Table 3.
Command byte
D7
D6
D5
D4
D3
D2
D1
D0
Command
0
0
0
0
0
0
0
1
write to 256-byte EEPROM via I2C-bus
0
0
0
0
0
0
1
1
read from 256-byte EEPROM via I2C-bus
0
0
0
0
0
1
0
0
write to 6-bit EEPROM via I2C-bus
0
0
0
0
0
1
1
0
read from 6-bit EEPROM via I2C-bus
0
0
0
0
0
1
1
1
read Input Port (IP) register via I2C-bus
0
0
0
0
1
0
0
0
read/write Output Port (OP) register via I2C-bus
0
0
0
0
1
0
0
1
read/write Polarity Inversion (PI) register via
I2C-bus
0
0
0
0
1
0
1
0
read/write Input/Output Configuration (IOC)
register via I2C-bus
0
0
0
0
1
0
1
1
read/write MUX Control (MUXCNTRL) register
via I2C-bus
0
0
0
0
1
1
0
0
read MUX_INx values via I2C-bus
0
0
0
0
1
1
0
1
reserved
0
0
0
0
1
1
1
0
reserved
0
0
0
0
1
1
1
1
read 256-byte EEPROM and write OP register
0
0
0
1
0
0
0
0
read 256-byte EEPROM and write PI register
0
0
0
1
0
0
0
1
read 256-byte EEPROM and write IOC register
0
0
0
1
0
0
1
0
read IP register and write to 256-byte EEPROM
0
0
0
1
0
0
1
1
reserved
:
:
:
:
:
:
:
:
1
1
1
1
1
1
1
1
reserved
7.1.1 Multiplexer
MSB
0
LSB
0
NONMUX
MUX
MUX
MUX
MUX
MUXED
DATA E DATA D DATA C DATA B DATA A
DATA
002aad369
Fig 5.
I2C-bus MUX_OUTx data byte
MSB
0
LSB
0
0
MUX_IN MUX_IN MUX_IN MUX_IN MUX_IN
D
B
A
E
C
002aad370
Fig 6.
PCA9558
Product data sheet
I2C-bus MUX_INx data byte
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 25 June 2012
© NXP B.V. 2012. All rights reserved.
6 of 29
PCA9558
NXP Semiconductors
8-bit I2C-bus/SMBus I/O port
The Multiplexer function controls the six open-drain outputs, MUX_OUTx and
NON_MUXED_OUT. This control is affected by the input pins MUX_SELECT (pin 19),
MUX_OUT_LOW (pin 26), and/or an internal register programmed via the I2C-bus.
Upon power-up, the multiplex function is controlled by the MUX_SELECT and
MUX_OUT_LOW pins. When the MUX_SELECT signal is a logic 0, the multiplexer will
select the data from the 6-bit EEPROM to drive on the MUX_OUTx and
NON_MUXED_OUT pins. When the MUX_SELECT signal is a logic 1, the multiplexer will
select the MUX_INx pins to drive on the MUX_OUTx pins.
The NON_MUXED_OUT output is latched from the 6-bit EEPROM on a rising edge of the
MUX_SELECT signal. This latch is transparent while the MUX_SELECT signal is a
logic 0. An internal control register, written via the I2C-bus, can also control the multiplexer
function. When this register is written, the MUX_SELECT function can change from the
external pin to an internal register. In this register a bit will act in a similar fashion to the
MUX_SELECT input, i.e., a logic 1 will cause the multiplexer to select data from the 6-bit
EEPROM to drive on the MUX_OUTx and NON_MUXED_OUT pins. In this configuration,
the NON_MUXED_OUT will latch data when the PCA9558 acknowledges the I2C-bus.
The MUX_SELECT pin will have no effect on the MUX_OUTx or NON_MUXED_OUT
while in this mode.
When the MUX_OUT_LOW signal is a logic 0 and the multiplexer is configured so that the
MUX_OUTx pins are being driven by the 6-bit EEPROM, the MUX_OUTx pins will be
driven to a logic 0. This information is summarized in Table 4.
Table 4.
Multiplexer function table
Register
Input
Output
B1[1]
B0[1]
MUX_OUT_LOW MUX_SELECT
MUX_OUTx
NON_MUXED_OUT
x
0
0
MUX_INx inputs
latched from EEPROM[2]
1
x
0
0
0
0
0
x
0
1
1
MUX_INx inputs
latched from EEPROM[2]
x
0
1
0
from EEPROM
from EEPROM
0
1
0
x
MUX_INx inputs
latched from EEPROM[3]
1
1
0
x
0
0
0
1
1
x
MUX_INx inputs
latched from EEPROM[3]
1
1
1
x
from EEPROM
from EEPROM
[1]
These are the 2 LSBs of the MUX Control (MUXCNTRL) register.
[2]
NON_MUXED_OUT value will be the value present in the 6-bit EEPROM at the time of the rising edge of
the MUX_SELECT input.
[3]
NON_MUXED_OUT value will be the value present in the 6-bit EEPROM at the time of the slave ACK when
bit 1 has changed from logic 0 to logic 1.
If the MUX_OUTx outputs are being driven by the 6-bit EEPROM and this EEPROM is
programmed, the outputs will remain stable and change to the new values after the
EEPROM program cycle completes.
Examples of read/write for MUX control can be found in Figure 7.
PCA9558
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 25 June 2012
© NXP B.V. 2012. All rights reserved.
7 of 29
PCA9558
NXP Semiconductors
8-bit I2C-bus/SMBus I/O port
slave address
S
1
0
0
1
1
command byte
1 A0 0
START condition
A
R/W
0
0
0
0
1
data byte
0
acknowledge
from slave
1
1
A
0
0
0
0
0
acknowledge
from slave
0 B1 B0 A
P
acknowledge
from slave
STOP
condition
002aad371
Fig 7.
I2C-bus write for MUXCNTRL register
slave address
S
1
0
0
1
1
command byte
1 A0 0
START condition
R/W
A
0
0
0
acknowledge
from slave
0
1
0
slave address
1
1
A
acknowledge
from slave
S
1
0
0
1
1
1 A0 1
(re)START
condition
R/W
A (cont.)
acknowledge
from slave
data from slave
(cont.)
0
0
0
0
0
0 B1 B0 NA P
no acknowledge
from master
STOP
condition
002aad372
Fig 8.
I2C-bus read for MUXCNTRL register
7.1.2 Registers
The GPIOs are controlled by a set of 4 internal registers: Input Port (IP) register; Output
Port (OP) register; Polarity Inversion (PI) register; and the Input/Output Configuration
(IOC) register. Each register is read/write via the I2C-bus or 256-byte EEPROM, with the
exception of the Input Port register, which is read only, one at a time. The read/write takes
place on the slave Acknowledge. The control of which register is currently available to the
I2C-bus is set by bits in the control register. See Section 7.1.2.1 through Section 7.1.2.4
for details.
7.1.2.1
IP - Input Port register
This register is an input-only port. It reflects the logic value present on the GPIO pins
regardless of whether they are configured as inputs or outputs (IOC register). Writes to
this register have no effect.
Table 5.
PCA9558
Product data sheet
IP - Input Port register description
Bit
7
6
5
4
3
2
1
0
Symbol
I7
I6
I5
I4
I3
I2
I1
I0
Default
0
0
0
0
0
0
0
0
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 25 June 2012
© NXP B.V. 2012. All rights reserved.
8 of 29
PCA9558
NXP Semiconductors
8-bit I2C-bus/SMBus I/O port
7.1.2.2
OP - Output Port register
This register is an output-only port. It reflects the outgoing logic levels of the GPIO defined
as outputs in the IOC register. Bit values in this register have no effect on GPIO defined as
inputs. In turn, reads from this register reflect the value stored in the flip-flop controlling
the output, not the actual output value.
Table 6.
Bit
7.1.2.3
OP - Output Port register description
7
6
5
4
3
2
1
0
Symbol
O7
O6
O5
O4
O3
O2
O1
O0
Default
0
0
0
0
0
0
0
0
PI - Polarity Inversion register
This register enables polarity inversion of GPIO defined as inputs by the IOC register. If a
bit in this register is set to a logic 1, the corresponding GPIO input port is inverted. If a bit
in this register is set to a logic 0, the corresponding GPIO input port is not inverted.
Table 7.
Bit
7.1.2.4
PI - Polarity Inversion register description
7
6
5
4
3
2
1
0
Symbol
P7
P6
P5
P4
P3
P2
P1
P0
Default
1
1
1
1
0
0
0
0
IOC - Input/Output Configuration register
This register configures the direction of the GPIO pins (IOx). If a bit is set to a logic 1, the
corresponding port pin is enabled as an input with a high-impedance output driver. If a bit
is set to a logic 0, the corresponding port pin is enabled as an output.
Table 8.
Bit
IOC - Input/Output Configuration register description
7
6
5
4
3
2
1
0
Symbol
C7
C6
C5
C4
C3
C2
C1
C0
Default
0
0
0
0
0
0
0
0
Examples of read/write to these registers can be found in Figure 9, Figure 10, Figure 15,
and Figure 16.
The IO_OUT_LOW input, when held LOW longer than the time Tcy(W), will reset the GPIO
registers to their default (power-up) values.
A read of the present value of the inputs MUX_INx can be done via the I2C-bus. This is
done by addressing the PCA9558 in a write mode and entering the correct command
code. The preset value on the MUX_INx inputs is latched at the command code
Acknowledge. A REPEATED START is then sent with the R/W bit set to a logic 1, read,
and this latched data is read out on the I2C-bus. See Figure 11.
PCA9558
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 25 June 2012
© NXP B.V. 2012. All rights reserved.
9 of 29
PCA9558
NXP Semiconductors
8-bit I2C-bus/SMBus I/O port
slave address
S
1
0
0
1
1
START condition
command byte
1 A0 0
A
R/W
0
0
0
0
x
data byte
x
acknowledge
from slave
x
x
A d7 d6 d5 d4 d3 d2 d1 d0 A
acknowledge
from slave
P
STOP
condition
acknowledge
from slave
002aad373
See Table 3 for the proper command byte.
Fig 9.
I2C-bus write for GPIO registers
slave address
S
1
0
0
1
1
START condition
command byte
1 A0 0
R/W
A
0
0
0
0
x
acknowledge
from slave
x
slave address
x
x
A
acknowledge
from slave
S
1
0
0
1
1
1 A0 1
(re)START
condition
R/W
A (cont.)
acknowledge
from slave
data from slave
(cont.) d7 d6 d5 d4 d3 d2 d1 d0 NA P
no acknowledge
from master
STOP
condition
002aad374
Fig 10. I2C-bus read for GPIO registers
slave address
S
1
0
0
1
START condition
1
command byte
1 A0 0
R/W
A
0
0
0
acknowledge
from slave
0
1
1
slave address
0
0
A
acknowledge
from slave
S
1
0
0
1
1
1 A0 1
(re)START
condition
R/W
A (cont.)
acknowledge
from slave
data from slave
(cont.)
0
0
0 d4 d3 d2 d1 d0 NA P
no acknowledge
from master
STOP
condition
002aad375
Fig 11. I2C-bus read of MUX_INx inputs
PCA9558
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 25 June 2012
© NXP B.V. 2012. All rights reserved.
10 of 29
PCA9558
NXP Semiconductors
8-bit I2C-bus/SMBus I/O port
7.1.3 EEPROM write operation
7.1.3.1
6-bit write operation
A write operation to the 6-bit EEPROM requires that an address byte be written after the
command byte. This address points to the 6-bit address space in the EEPROM array.
Upon receipt of this address, the PCA9558 waits for the next byte that will be written to the
EEPROM. The master then ends the transaction with a STOP condition on the I2C-bus.
See Figure 12.
After the STOP condition, the E/W cycle starts, and the parts will not respond to any
request to access the EEPROM array until the cycle finishes, approximately 4 ms.
slave address
S
1
0
0
1
1
EEPROM address
command byte
1 A0 0
START condition
R/W
A
0
0
0
0
0
acknowledge
from slave
1
0
0
A
1
1
1
1
1
1
1
1
acknowledge
from slave
A (cont.)
acknowledge
from slave
data for 6-bit EEPROM
(cont.)
X
X d5 d4 d3 d2 d1 d0 A
acknowledge
from slave
P
programming begins
after STOP
STOP
condition
002aad376
Fig 12. I2C-bus write of 6-bit EEPROM
7.1.3.2
6-bit read operation
A read operation is initiated in the same manner as a write operation, with the exception
that after the word address has been written a REPEATED START condition is placed on
the I2C-bus and the direction of communication is reversed (see Figure 13).
slave address
S
1
0
0
1
START condition
1
EEPROM address
command byte
1 A0 0
A
R/W
0
0
0
0
0
acknowledge
from slave
1
1
0
A
1
S
1
0
0
(re)START
condition
1
acknowledge
from slave
1
1
1
1
1
1
1
A (cont.)
acknowledge
from slave
slave address
(cont.)
1
data from 6-bit EEPROM
1 A0 1
R/W
A
0
0 d5 d4 d3 d2 d1 d0 NA P
acknowledge
from slave
no acknowledge
from master
STOP
condition
002aad377
Fig 13. I2C-bus read of 6-bit EEPROM
PCA9558
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 25 June 2012
© NXP B.V. 2012. All rights reserved.
11 of 29
PCA9558
NXP Semiconductors
8-bit I2C-bus/SMBus I/O port
7.1.3.3
256-byte write operation (I2C-bus)
A write operation to the 256-byte EEPROM requires that an address byte be written after
the command byte. This address points to the starting address in the EEPROM array. The
four LSBs of this address select a position on a 16-byte page register, the four MSBs
select which page register. The four LSBs will be auto-incremented after receipt of each
byte of data; in this manner, the entire page register can be written starting at any point.
Up to 16 bytes of data may be sent to the PCA9558, followed by a STOP condition on the
I2C-bus. If the master sends more than 16 bytes of data prior to generating a STOP
condition, data within the address page will be overwritten and unpredictable results may
occur. See Figure 14.
After the STOP condition, the E/W cycle starts, and the parts will not respond to any
request to access the EEPROM array until the cycle finishes, approximately 4 ms.
slave address
S
1
0
0
1
START condition
1
acknowledge
from slave
command code
1 A0 0
R/W
A
0
0
0
0
0
0
0
1
A
acknowledge
from slave
EEPROM address
A
acknowledge
from slave
acknowledge
from slave
A (cont.)
DATA N
Auto-Increment
word address
acknowledge
from slave
(cont.)
DATA N + 1
A
Auto-Increment
word address
acknowledge
from slave
DATA N + M
A
Auto-Increment
word address
P
STOP
condition
002aad378
M bytes where M ≤ 15.
Fig 14. I2C-bus page write operation to 256-byte EEPROM
PCA9558
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 25 June 2012
© NXP B.V. 2012. All rights reserved.
12 of 29
PCA9558
NXP Semiconductors
8-bit I2C-bus/SMBus I/O port
256-byte read operation (I2C-bus)
7.1.3.4
A read operation is initiated in the same manner as a write operation, with the exception
that after the word address has been written, a REPEATED START condition is placed on
the I2C-bus, and the direction of communication is reversed. For a read operation, the
entire address is incremented after the transmission of each byte, meaning that the entire
256-byte EEPROM array can be read at one time. See Figure 15.
slave address
S
1
0
0
1
1
1 A0 0
START condition
S
1
0
0
A
0
0
0
0
0
0
1
1
A
acknowledge
from slave
A (cont.)
EEPROM address
R/W
slave address
(cont.)
acknowledge
from slave
acknowledge
from slave
command code
1
1
acknowledge
from slave
1 A0 1
(re)START condition
acknowledge
from master
A
DATA N
A
DATA N + M
Auto-Increment
word address
R/W
no acknowledge
from master
NA P
STOP
condition
Auto-Increment
word address
002aad379
M bytes where M ≥ 1.
Fig 15. I2C-bus read operation from 256-byte EEPROM
7.1.3.5
256-byte EEPROM write to GPIO
A mode is available whereby a byte of data in the 256-byte EEPROM array can be written
to the GPIO (OP register). This is initiated by the I2C-bus. In this mode, a control word
indicating a read from the 256-byte EEPROM and write to the GPIO is sent, followed by
the word address of the data within the EEPROM array. Upon Acknowledge from the
slave, the data is sent to the GPIO. See Figure 16.
slave address
S
1
0
0
1
START condition
1
EEPROM address
command byte
1 A0 0
R/W
A
0
0
0
x
x
acknowledge
from slave
x
x
x
A a7 a6 a5 a4 a3 a2 a1 a0 A (cont.)
acknowledge
from slave
slave address
(cont.)
S
1
0
(re)START
condition
0
1
1
acknowledge
from slave
data from 256-byte EEPROM
1 A0 1
R/W
A d7 d6 d5 d4 d3 d2 d1 d0 NA P
acknowledge
from slave
no acknowledge
from master
STOP condition;
data latched into
GPIO register
002aad380
See Table 3 for the needed command code.
Fig 16. Read from 256-byte EEPROM and write to GPIO registers
PCA9558
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 25 June 2012
© NXP B.V. 2012. All rights reserved.
13 of 29
PCA9558
NXP Semiconductors
8-bit I2C-bus/SMBus I/O port
7.1.3.6
256-byte EEPROM write from GPIO
A mode is available whereby data in the GPIO (IP register) can be written to the 256-byte
EEPROM. This is initiated by the I2C-bus. In this mode, a control word indicating a read
from the GPIO and write to the 256-byte EEPROM is sent, followed by the word address
for the data to be written. Once the slave has sent an Acknowledge, the master must send
a STOP condition. See Figure 17.
After the STOP condition, the E/W cycle starts, and the parts will not respond to any
request to access the EEPROM array until the cycle finishes, approximately 4 ms.
When the Write Protect (WP) input is a logic 0 it allows writes to both EEPROM arrays.
When it is a logic 1, it prevents any writes to the EEPROM arrays.
GPIO input port data latched
slave address
S
1
0
0
1
1
START condition
EEPROM address
dummy byte
A a7 a6 a5 a4 a3 a2 a1 a0 A
x x x x x x x x
command byte
1 A0 0
R/W
A
0
0
0
1
acknowledge
from slave
0
0
1
0
acknowledge
from slave
acknowledge
from slave
A
P
acknowledge
from slave
STOP condition;
programming begins after STOP
002aad381
See Table 3 for the needed command code.
Fig 17. Read from GPIO Input Port register and write to 256-byte EEPROM
7.1.4 Reset
7.1.4.1
Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9558 in
a reset state until VDD has reached VPOR. At that point, the reset condition is released and
the PCA9558 volatile registers and SMBus state machine will initialize to their default
states.
The GPIO outputs (IOx) will be selected as outputs.
The DIP switch MUX_OUTx and NON_MUXED_OUT pin values depend on:
• The MUX_OUT_LOW and MUX_SELECT logic levels
• The previously stored values in the EEPROM register/current MUX_INx pin values as
shown in Table 4
7.1.4.2
External reset
A reset of the GPIO registers can be accomplished by holding the IO_OUT_LOW pin
LOW for a minimum of Tcy(W). These GPIO registers return to their default states until the
IO_OUT_LOW input is once again HIGH.
PCA9558
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 25 June 2012
© NXP B.V. 2012. All rights reserved.
14 of 29
PCA9558
NXP Semiconductors
8-bit I2C-bus/SMBus I/O port
7.2 Using the PCA9558 on the SMBus
It is possible to use Intel chip sets to communicate with the PCA9558. There are no
limitations when the SMBus controller is communicating with the MUX or the GPIO;
however, there are limitations with the 2-kbit serial EEPROM. Because of being able to
address any location in the EEPROM block using the second command byte, the designer
using the PCA9558 on the SMBus will have to program around it, an easy thing to do. The
device designers had to deal with the specifics of addressing the EEPROM and chose the
I2C-bus specification and use the second command byte to address any location in the
EEPROM block.
In order to write to the EEPROM, write the EEPROM address byte in the Data0 byte and
the data to be sent should be placed in the Data1 byte. The Intel chip set’s Word Data
instruction would then send the address, followed by the command register then Data0
(EEPROM address), and then the Data1 (data byte). A read from the EEPROM would be
a two-step process. The first step would be to do a ‘Write Byte’ with the EEPROM address
in the Data0 register. The second step would be to do a ‘Receive Byte’ where the data is
stored in the command register.
Other differences from the SMBus specification:
• Paragraph 5.5.5 – Read Byte/Word in figure 5-11: The PCA9558 follows this same
command code with one exception, the PCA9558 requires 2 bytes of command
before the repeated START.
• Paragraph 5.5.6 – Process call in figure 5-15: The PCA9558 read operation is very
similar to the SMBus process call. In the PCA9558 read operation you send a START
condition – slave address with a write bit – 2 bytes of command code –
repeated START – slave address with a read bit – then read data.
PCA9558
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 25 June 2012
© NXP B.V. 2012. All rights reserved.
15 of 29
PCA9558
NXP Semiconductors
8-bit I2C-bus/SMBus I/O port
8. Application design-in information
A central processor/controller typically located on the system main board can use the
400 kHz I2C-bus/SMBus to poll the PCA9558 devices located on the system cards for
status or version control type of information. The PCA9558 may be programmed at
manufacturing to store information regarding board build, firmware version, manufacturer
identification, configuration option data, etc. Alternately, these devices can be used as
convenient interface for board configuration, thereby utilizing the I2C-bus/SMBus as an
intra-system communication bus.
NXP
4-channel
I2C-bus multiplexer
ASIC
I2C-bus
configuration settings
DIP switch or jumper replacement
I2C-bus
CPU
OR
μC
I2C-bus
PCA9558
BACKPLANE
PCA9544A
MUXED EEPROM
I2C-bus
I2C-bus
CONTROL
GPIO
EEPROM
monitoring
and
control
INPUTS
ALARM
LEDs
card ID, subroutines, configuration data, or revision history
002aad392
Fig 18. Typical application
PCA9558
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 25 June 2012
© NXP B.V. 2012. All rights reserved.
16 of 29
PCA9558
NXP Semiconductors
8-bit I2C-bus/SMBus I/O port
9. Limiting values
Table 9.
Limiting values[1]
In accordance with the Absolute Maximum Rating System (IEC 60134).
Voltages are referenced to VSS (0 V).
Symbol
Parameter
Conditions
VDD
supply voltage
VI
input voltage
[2]
VO
output voltage
[2]
Tstg
storage temperature
Min
Max
Unit
2.5
4.6
V
−0.5
VDD + 0.5
V
−0.5
VDD + 0.5
V
−60
+150
°C
[1]
The performance capability of a high-performance integrated circuit in conjunction with its thermal
environment can create junction temperatures which are detrimental to reliability. The maximum junction
temperature of this integrated circuit should not exceed 150 °C.
[2]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
10. Recommended operating conditions
Table 10.
Operating conditions
Symbol
Parameter
VDD
supply voltage
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
VOL
LOW-level output voltage
Conditions
Min
3
SCL, SDA; IOL = 3 mA
−0.5
MUX_OUT_LOW, MUX_INx, MUX_SELECT
−0.5
SCL, SDA; IOL = 3 mA
2.7
Typ
Max
Unit
-
3.6
V
-
0.9
V
-
0.8
V
-
4.0
V
MUX_OUT_LOW, MUX_INx, MUX_SELECT
2.0
-
4.0
V
SCL, SDA; IOL = 3 mA
-
-
0.4
V
SCL, SDA; IOL = 6 mA
-
-
0.6
V
IOL
LOW-level output current
MUX_OUTx, NON_MUXED_OUT;
VOL = 0.4 V
-
-
4
mA
IOH
HIGH-level output current
MUX_OUTx, NON_MUXED_OUT
-
-
100
μA
Δt/ΔV
input transition rise and fall rate
0
-
10
ns/V
Tamb
ambient temperature
0
-
70
°C
PCA9558
Product data sheet
operating
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 25 June 2012
© NXP B.V. 2012. All rights reserved.
17 of 29
PCA9558
NXP Semiconductors
8-bit I2C-bus/SMBus I/O port
11. Static characteristics
Table 11.
Static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
3.0
-
3.6
V
Supply
VDD
supply voltage
ICCL
LOW-level supply current
operating mode; all inputs = 0 V
-
-
10
mA
ICCH
HIGH-level supply current
operating mode; all inputs = VDD
-
-
10
mA
VPOR
power-on reset voltage
no load; VI = VDD or VSS
-
2.3
2.6
V
Input SCL; input/output SDA
VIL
LOW-level input voltage
−0.5
-
+0.8
V
VIH
HIGH-level input voltage
2
-
VDD + 0.5
V
IOL
LOW-level output current
VOL = 0.4 V
3
-
-
mA
VOL = 0.6 V
6
-
-
mA
ILH
HIGH-level leakage current
VI = VDD
−1
-
+1
μA
ILL
LOW-level leakage current
VI = VSS
−1
-
+1
μA
Ci
input capacitance
-
-
10
pF
MUX_OUT_LOW, WP, MUX_SELECT
ILH
HIGH-level leakage current
VI = VDD
-
-
1
μA
ILL
LOW-level leakage current
VI = VSS
-
-
−100
μA
Ci
input capacitance
-
-
10
pF
MUX_INx
ILH
HIGH-level leakage current
VI = VDD
-
-
1
μA
ILL
LOW-level leakage current
VI = VSS
-
-
−100
μA
Ci
input capacitance
-
-
10
pF
A0 input
ILH
HIGH-level leakage current
VI = VDD
-
-
1
μA
ILL
LOW-level leakage current
VI = VSS
-
-
−100
μA
Ci
input capacitance
-
-
10
pF
MUX_OUTx
VOL
IOH
LOW-level output voltage
HIGH-level output current
IOL = 100 μA
-
-
0.4
V
IOL = 4 mA
-
-
0.7
V
VOH = VDD
-
-
100
μA
NON_MUXED_OUT
VOL
IOH
IOL = 100 μA
-
-
0.4
V
IOL = 4 mA
-
-
0.7
V
HIGH-level output current
VOH = VDD
-
-
100
μA
LOW-level output voltage
IOL = 100 μA
-
-
0.4
V
IOL = 4 mA
-
-
0.7
V
VOH = VDD
-
-
100
μA
LOW-level output voltage
GPIO (IOx)
VOL
IOH
HIGH-level output current
PCA9558
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 25 June 2012
© NXP B.V. 2012. All rights reserved.
18 of 29
PCA9558
NXP Semiconductors
8-bit I2C-bus/SMBus I/O port
12. Dynamic characteristics
Table 12.
Symbol
Dynamic characteristics
Parameter
Conditions
Min
Typ
Max
Unit
MUX_INx to MUX_OUTx
tPLH
LOW to HIGH propagation delay
-
21
28
ns
tPHL
HIGH to LOW propagation delay
-
7
10
ns
MUX_SELECT to MUX_OUTx
tPLH
LOW to HIGH propagation delay
-
20
28
ns
tPHL
HIGH to LOW propagation delay
-
8
12
ns
MUX_OUT_LOW to NON_MUXED_OUT
tPLH
LOW to HIGH propagation delay
-
20
26
ns
tPHL
HIGH to LOW propagation delay
-
8
15
ns
MUX_OUT_LOW to MUX_OUTx
tPLH
LOW to HIGH propagation delay
-
20
28
ns
tPHL
HIGH to LOW propagation delay
-
7.0
15
ns
tr
rise time
output
1.0
-
10
ns/V
tf
fall time
output
1.0
-
5
ns/V
CL
load capacitance
test load on outputs
-
-
10
pF
I2C-bus
fSCL
SCL clock frequency
10
-
400
kHz
tBUF
bus free time between a STOP and START
condition
1.3
-
-
μs
tHD;STA
hold time (repeated) START condition
600
-
-
ns
tLOW
LOW period of the SCL clock
1.3
-
-
μs
tHIGH
HIGH period of the SCL clock
600
-
−12
ns
[1]
tSU;STA
set-up time for a repeated START condition
600
-
−32
ns
tHD;DAT
data hold time
0
-
10
ns
tSU;DAT
data set-up time
100
-
−100
ns
tSP
pulse width of spikes that must be
suppressed by the input filter
0
-
50
ns
tSU;STO
set-up time for STOP condition
600
-
10
ns
tr
rise time of both SDA and SCL signals
10 pF to 400 pF bus
20
-
300
ns
tf
fall time of both SDA and SCL signals
10 pF to 400 pF bus
20
-
300
ns
Cb
capacitive load for each bus line
-
-
400
pF
Tcy(W)
write cycle time
-
15
-
ms
[2]
[1]
After this period, the first clock pulse is generated.
[2]
Write cycle time can only be measured indirectly during the write cycle. During this time, the device will not acknowledge its I2C-bus
address.
PCA9558
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 25 June 2012
© NXP B.V. 2012. All rights reserved.
19 of 29
PCA9558
NXP Semiconductors
8-bit I2C-bus/SMBus I/O port
0.7 × VDD
SDA
0.3 × VDD
tr
tBUF
tf
tHD;STA
tSP
tLOW
0.7 × VDD
SCL
0.3 × VDD
tHD;STA
P
tSU;STA
tHD;DAT
S
tHIGH
tSU;DAT
tSU;STO
Sr
P
002aaa986
Fig 19. Definition of timing
VI
MUX input
VM
VM
VSS
tPZL
tPLZ
VDD
MUX output
VM
VOL
VOL + 0.3 V
002aad416
Fig 20. Open-drain output enable and disable times
13. Non-volatile storage specifications
Table 13.
PCA9558
Product data sheet
Non-volatile storage specifications
Parameter
Specification
memory cell data retention
10 years (minimum)
number of memory cell write cycles
100,000 cycles (minimum)
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 25 June 2012
© NXP B.V. 2012. All rights reserved.
20 of 29
PCA9558
NXP Semiconductors
8-bit I2C-bus/SMBus I/O port
14. Test information
VDD
VDD
RL
PULSE
GENERATOR
VI
VO
DUT
CL
RT
002aac532
RL = load resistor (1 kΩ)
CL = load capacitance (includes jig and probe capacitance; 10 pF)
RT = termination resistance; should be equal to Zo of pulse generators
Fig 21. Test circuit for open-drain outputs
PCA9558
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 25 June 2012
© NXP B.V. 2012. All rights reserved.
21 of 29
PCA9558
NXP Semiconductors
8-bit I2C-bus/SMBus I/O port
15. Package outline
TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm
D
SOT361-1
E
A
X
c
HE
y
v M A
Z
15
28
Q
A2
(A 3)
A1
pin 1 index
A
θ
Lp
1
L
14
detail X
w M
bp
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
9.8
9.6
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.8
0.5
8o
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT361-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-153
Fig 22. Package outline SOT361-1 (TSSOP28)
PCA9558
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 25 June 2012
© NXP B.V. 2012. All rights reserved.
22 of 29
PCA9558
NXP Semiconductors
8-bit I2C-bus/SMBus I/O port
16. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
16.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
PCA9558
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 25 June 2012
© NXP B.V. 2012. All rights reserved.
23 of 29
PCA9558
NXP Semiconductors
8-bit I2C-bus/SMBus I/O port
16.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 23) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 14 and 15
Table 14.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 15.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 23.
PCA9558
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 25 June 2012
© NXP B.V. 2012. All rights reserved.
24 of 29
PCA9558
NXP Semiconductors
8-bit I2C-bus/SMBus I/O port
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 23. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
17. Abbreviations
Table 16.
PCA9558
Product data sheet
Abbreviations
Acronym
Description
ASIC
Application Specific Integrated Circuit
CDM
Charged Device Model
CPU
Central Processing Unit
DIP
Dual In-line Package
DUT
Device Under Test
EEPROM
Electrically-Erasable Programmable Read-Only Memory
ESD
ElectroStatic Discharge
GPIO
General Purpose Input/Output
HBM
Human Body Model
I/O
Input/Output
I2C-bus
Inter-Integrated Circuit bus
LED
Light Emitting Diode
LSB
Least Significant Bit
MSB
Most Significant Bit
POR
Power-On Reset
SMBus
System Management Bus
μC
microcontroller
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 25 June 2012
© NXP B.V. 2012. All rights reserved.
25 of 29
PCA9558
NXP Semiconductors
8-bit I2C-bus/SMBus I/O port
18. Revision history
Table 17.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCA9558 v.5
20120625
Product data sheet
-
PCA9558 v.4
Modifications:
•
•
•
Section 2 “Features and benefits”, 13th bullet: deleted “200 V MM per JESD22-A115”
Table 8 “IOC - Input/Output Configuration register description”: default corrected from “1111 1111”
to “0000 0000” (documentation correction only, there is no change in silicon)
Table 16 “Abbreviations”: deleted row “MM, Machine Model”
PCA9558 v.4
20090414
Product data sheet
-
PCA9558 v.3
PCA9558 v.3
(9397 750 11674)
20030627
Product data
ECN 853-2235 29936
of 19 May 2003
PCA9558 v.2
PCA9558 v.2
(9397 750 09889)
20020524
Product data
ECN 853-2235 28310
of 24 May 2002
PCA9558 v.1
PCA9558 v.1
20001204
Product specification
-
-
PCA9558
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 25 June 2012
© NXP B.V. 2012. All rights reserved.
26 of 29
PCA9558
NXP Semiconductors
8-bit I2C-bus/SMBus I/O port
19. Legal information
19.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
19.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PCA9558
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 25 June 2012
© NXP B.V. 2012. All rights reserved.
27 of 29
PCA9558
NXP Semiconductors
8-bit I2C-bus/SMBus I/O port
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
20. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PCA9558
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 25 June 2012
© NXP B.V. 2012. All rights reserved.
28 of 29
PCA9558
NXP Semiconductors
8-bit I2C-bus/SMBus I/O port
21. Contents
1
2
3
4
5
6
6.1
6.2
7
7.1
7.1.1
7.1.2
7.1.2.1
7.1.2.2
7.1.2.3
7.1.2.4
7.1.3
7.1.3.1
7.1.3.2
7.1.3.3
7.1.3.4
7.1.3.5
7.1.3.6
7.1.4
7.1.4.1
7.1.4.2
7.2
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
19
19.1
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
I2C-bus interface. . . . . . . . . . . . . . . . . . . . . . . . 5
Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
IP - Input Port register . . . . . . . . . . . . . . . . . . . 8
OP - Output Port register . . . . . . . . . . . . . . . . . 9
PI - Polarity Inversion register. . . . . . . . . . . . . . 9
IOC - Input/Output Configuration register . . . . . 9
EEPROM write operation . . . . . . . . . . . . . . . . 11
6-bit write operation . . . . . . . . . . . . . . . . . . . . 11
6-bit read operation . . . . . . . . . . . . . . . . . . . . 11
256-byte write operation (I2C-bus) . . . . . . . . . 12
256-byte read operation (I2C-bus) . . . . . . . . . 13
256-byte EEPROM write to GPIO. . . . . . . . . . 13
256-byte EEPROM write from GPIO . . . . . . . 14
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 14
External reset . . . . . . . . . . . . . . . . . . . . . . . . . 14
Using the PCA9558 on the SMBus . . . . . . . . 15
Application design-in information . . . . . . . . . 16
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 17
Recommended operating conditions. . . . . . . 17
Static characteristics. . . . . . . . . . . . . . . . . . . . 18
Dynamic characteristics . . . . . . . . . . . . . . . . . 19
Non-volatile storage specifications . . . . . . . . 20
Test information . . . . . . . . . . . . . . . . . . . . . . . . 21
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 22
Soldering of SMD packages . . . . . . . . . . . . . . 23
Introduction to soldering . . . . . . . . . . . . . . . . . 23
Wave and reflow soldering . . . . . . . . . . . . . . . 23
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 23
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 24
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 26
Legal information. . . . . . . . . . . . . . . . . . . . . . . 27
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 27
19.2
19.3
19.4
20
21
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
27
28
28
29
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 25 June 2012
Document identifier: PCA9558
Similar pages