Data Sheet

PCA6416A
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
with interrupt output, reset, and configuration registers
Rev. 2. — 10 January 2013
Product data sheet
1. General description
The PCA6416A is a 16-bit general purpose I/O expander that provides remote I/O
expansion for most microcontroller families via the I2C-bus interface.
NXP I/O expanders provide a simple solution when additional I/Os are needed while
keeping interconnections to a minimum, for example, in battery-powered mobile
applications for interfacing to sensors, push buttons, keypad, etc. In addition to providing
a flexible set of GPIOs, it simplifies interconnection of a processor running at one voltage
level to I/O devices operating at a different (usually higher) voltage level. The PCA6416A
has built-in level shifting feature that makes these devices extremely flexible in mixed
signal environments where communication between incompatible I/O voltages is required.
Its wide VDD range of 1.65 V to 5.5 V on the dual power rail allows seamless
communications with next-generation low voltage microprocessors and microcontrollers
on the interface side (SDA/SCL) and peripherals at a higher voltage on the port side.
There are two supply voltages for PCA6416A: VDD(I2C-bus) and VDD(P). VDD(I2C-bus)
provides the supply voltage for the interface at the master side (for example, a
microcontroller) and the VDD(P) provides the supply for core circuits and Port P. The
bidirectional voltage level translation in the PCA6416A is provided through VDD(I2C-bus).
VDD(I2C-bus) should be connected to the VDD of the external SCL/SDA lines. This indicates
the VDD level of the I2C-bus to the PCA6416A. The voltage level on Port P of the
PCA6416A is determined by the VDD(P).
The PCA6416A register set consists of four pairs of 8-bit Configuration, Input, Output, and
Polarity Inversion registers.
At power-on, the I/Os are configured as inputs. However, the system master can enable
the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for
each input or output is kept in the corresponding input or output register. The polarity of
the Input Port register can be inverted with the Polarity Inversion register, saving external
logic gates.
The system master can reset the PCA6416A in the event of a time-out or other improper
operation by asserting a LOW in the RESET input. The power-on reset puts the registers
in their default state and initializes the I2C-bus/SMBus state machine. The RESET pin
causes the same reset/initialization to occur without depowering the part.
The PCA6416A open-drain interrupt (INT) output is activated when any input state differs
from its corresponding Input Port register state and is used to indicate to the system
master that an input state has changed.
PCA6416A
NXP Semiconductors
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt
signal on this line, the remote I/O can inform the microcontroller if there is incoming data
on its ports without having to communicate via the I2C-bus. Thus, the PCA6416A can
remain a simple slave device.
The device Port P outputs have 25 mA sink capabilities for directly driving LEDs while
consuming low device current.
One hardware pin (ADDR) can be used to program and vary the fixed I2C-bus address
and allow up to two devices to share the same I2C-bus or SMBus.
2. Features and benefits
 I2C-bus to parallel port expander
 Operating power supply voltage range of 1.65 V to 5.5 V
 Allows bidirectional voltage-level translation and GPIO expansion between:
 1.8 V SCL/SDA and 1.8 V, 2.5 V, 3.3 V or 5 V Port P
 2.5 V SCL/SDA and 1.8 V, 2.5 V, 3.3 V or 5 V Port P
 3.3 V SCL/SDA and 1.8 V, 2.5 V, 3.3 V or 5 V Port P
 5 V SCL/SDA and 1.8 V, 2.5 V, 3.3 V or 5 V Port P
 Low standby current consumption:
 1.5 A typical at 5 V VDD
 1.0 A typical at 3.3 V VDD
 Schmitt-trigger action allows slow input transition and better switching noise immunity
at the SCL and SDA inputs
 Vhys = 0.18 V (typical) at 1.8 V
 Vhys = 0.25 V (typical) at 2.5 V
 Vhys = 0.33 V (typical) at 3.3 V
 Vhys = 0.5 V (typical) at 5 V
 5 V tolerant I/O ports
 Active LOW reset input (RESET)
 Open-drain active LOW interrupt output (INT)
 400 kHz Fast-mode I2C-bus
 Input/Output Configuration register
 Polarity Inversion register
 Internal power-on reset
 Power-up with all channels configured as inputs
 No glitch on power-up
 Noise filter on SCL/SDA inputs
 Latched outputs with 25 mA drive maximum capability for directly driving LEDs
 Latch-up performance exceeds 100 mA per JESD 78, Class II
 ESD protection exceeds JESD 22
 2000 V Human-Body Model (A114-A)
 1000 V Charged-Device Model (C101)
 Packages offered: TSSOP24, HWQFN24, VFBGA24
PCA6416A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 January 2013
© NXP B.V. 2013. All rights reserved.
2 of 42
PCA6416A
NXP Semiconductors
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
3. Ordering information
Table 1.
Ordering information
Type number
Topside
marking
Package
Name
Description
Version
PCA6416AEV
416A
VFBGA24
plastic very thin fine-pitch ball grid array package; 24 balls;
body 3  3  0.85 mm
SOT1199-1
PCA6416AHF
416A
HWQFN24 plastic thermal enhanced very very thin quad flat package;
no leads; 24 terminals; body 4  4  0.75 mm
PCA6416APW
PCA6416A TSSOP24
SOT994-1
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
SOT355-1
3.1 Ordering options
Table 2.
Ordering options
Type number
Orderable
part number
Package
Packing method
Minimum
order quantity
Temperature
PCA6416AEV
PCA6416AEVJ
VFBGA24
Reel pack, SMD,
13-inch
6000
Tamb = 40 C to +85 C
PCA6416AHF
PCA6416AHF,128
HWQFN24
Reel pack, SMD,
13-inch, turned
6000
Tamb = 40 C to +85 C
PCA6416APW
PCA6416APW,118
TSSOP24
Reel pack, SMD,
13-inch
2500
Tamb = 40 C to +85 C
4. Block diagram
PCA6416A
INT
INTERRUPT
LOGIC
LP FILTER
ADDR
SCL
SDA
INPUT
FILTER
I2C-BUS
CONTROL
RESET
16 BITS
P0_0 to P0_7
I/O
PORT
P1_0 to P1_7
VDD(I2C-bus)
VDD(P)
SHIFT
REGISTER
write pulse
read pulse
POWER-ON
RESET
VSS
002aaf537
All I/Os are set to inputs at reset.
Fig 1.
PCA6416A
Product data sheet
Block diagram (positive logic)
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 January 2013
© NXP B.V. 2013. All rights reserved.
3 of 42
PCA6416A
NXP Semiconductors
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
5. Pinning information
21 VDD(P)
24 RESET
23 VDD(I2C-bus)
5.1 Pinning
23 SDA
RESET
3
22 SCL
P0_0
4
21 ADDR
P0_0
1
18 ADDR
P0_1
5
20 P1_7
P0_1
2
17 P1_7
P0_2
6
19 P1_6
P0_2
3
P0_3
7
18 P1_5
P0_3
4
P0_4
8
17 P1_4
P0_4
5
14 P1_4
P0_5
9
16 P1_3
P0_5
6
13 P1_3
P0_6 10
15 P1_2
P0_7 11
14 P1_1
VSS 12
13 P1_0
16 P1_6
15 P1_5
P1_2 12
9
VSS
P1_1 11
8
P1_0 10
7
P0_7
PCA6416AHF
P0_6
PCA6416APW
terminal 1
index area
19 SCL
24 VDD(P)
2
20 SDA
1
22 INT
INT
VDD(I2C-bus)
002aaf536
Transparent top view
002aaf535
The exposed center pad, if used, must be
connected only as a secondary ground or
must be left electrically open.
Fig 2.
Pin configuration for TSSOP24
ball A1
index area
Fig 3.
Pin configuration for HWQFN24
PCA6416AEV
1
2
3
4
5
A
B
C
1
2
3
4
5
A
P0_0
RESET
INT
SDA
SCL
B
P0_2
C
P0_3
P0_4
P0_1
P1_7
P1_6
D
P0_5
P0_7
P1_2
P1_4
P1_5
E
P0_6
VSS
P1_0
P1_1
P1_3
VDD(I2C-bus) VDD(P)
ADDR
D
E
002aaf786
Transparent top view
002aah370
An empty cell indicates no ball
is populated at that grid point.
Fig 4.
PCA6416A
Product data sheet
Pin configuration for VFBGA24
Fig 5.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 January 2013
Ball mapping for VFBGA24
(transparent top view)
© NXP B.V. 2013. All rights reserved.
4 of 42
PCA6416A
NXP Semiconductors
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
5.2 Pin description
Table 3.
Symbol
Pin description
Pin
Description
TSSOP24 HWQFN24 VFBGA24
INT
1
22
A3
Interrupt output. Connect to VDD(I2C-bus) or VDD(P) through a pull-up
resistor.
VDD(I2C-bus)
2
23
B3
Supply voltage of I2C-bus. Connect directly to the VDD of the external
I2C master. Provides voltage-level translation.
RESET
3
24
A2
Active LOW reset input. Connect to VDD(I2C-bus) through a pull-up
resistor if no active connection is used.
P0_0[1]
4
1
A1
Port 0 input/output 0.
P0_1[1]
5
2
C3
Port 0 input/output 1.
P0_2[1]
6
3
B1
Port 0 input/output 2.
P0_3[1]
7
4
C1
Port 0 input/output 3.
P0_4[1]
8
5
C2
Port 0 input/output 4.
P0_5[1]
9
6
D1
Port 0 input/output 5.
P0_6[1]
10
7
E1
Port 0 input/output 6.
P0_7[1]
11
8
D2
Port 0 input/output 7.
VSS
12
9
E2
Ground.
P1_0[2]
13
10
E3
Port 1 input/output 0.
P1_1[2]
14
11
E4
Port 1 input/output 1.
P1_2[2]
15
12
D3
Port 1 input/output 2.
P1_3[2]
16
13
E5
Port 1 input/output 3.
P1_4[2]
17
14
D4
Port 1 input/output 4.
P1_5[2]
18
15
D5
Port 1 input/output 5.
P1_6[2]
19
16
C5
Port 1 input/output 6.
P1_7[2]
20
17
C4
Port 1 input/output 7.
ADDR
21
18
B5
Address input. Connect directly to VDD(P) or ground.
SCL
22
19
A5
Serial clock bus. Connect to VDD(I2C-bus) through a pull-up resistor.
SDA
23
20
A4
Serial data bus. Connect to VDD(I2C-bus) through a pull-up resistor.
VDD(P)
24
21
B4
Supply voltage of PCA6416A for Port P.
[1]
Pins P0_0 to P0_7 correspond to bits P0.0 to P0.7. At power-on, all I/O are configured as input.
[2]
Pins P1_0 to P1_7 correspond to bits P1.0 to P1.7. At power-on, all I/O are configured as input.
PCA6416A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 January 2013
© NXP B.V. 2013. All rights reserved.
5 of 42
PCA6416A
NXP Semiconductors
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
6. Voltage translation
Table 4 shows how to set up VDD levels for the necessary voltage translation between the
I2C-bus and the PCA6416A.
Table 4.
Voltage translation
VDD(I2C-bus) (SDA and SCL of I2C master)
VDD(P) (Port P)
1.8 V
1.8 V
1.8 V
2.5 V
1.8 V
3.3 V
1.8 V
5V
2.5 V
1.8 V
2.5 V
2.5 V
2.5 V
3.3 V
2.5 V
5V
3.3 V
1.8 V
3.3 V
2.5 V
3.3 V
3.3 V
3.3 V
5V
5V
1.8 V
5V
2.5 V
5V
3.3 V
5V
5V
7. Functional description
Refer to Figure 1 “Block diagram (positive logic)”.
7.1 Device address
The address of the PCA6416A is shown in Figure 6.
slave address
0
1
0
0
0
fixed
0
AD
R/W
DR
hardware selectable
002aah045
Fig 6.
PCA6416A address
ADDR is the hardware address package pin and is held to either HIGH (logic 1) or LOW
(logic 0) to assign one of the two possible slave addresses. The last bit of the slave
address (R/W) defines the operation (read or write) to be performed. A HIGH (logic 1)
selects a read operation, while a LOW (logic 0) selects a write operation.
PCA6416A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 January 2013
© NXP B.V. 2013. All rights reserved.
6 of 42
PCA6416A
NXP Semiconductors
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
7.2 Interface definition
Table 5.
Interface definition
Byte
Bit
I2C-bus
slave address
I/O data bus
7 (MSB)
6
5
4
3
2
1
0 (LSB)
L
H
L
L
L
L
ADDR
R/W
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
7.3 Pointer register and command byte
Following the successful acknowledgement of the address byte, the bus master sends a
command byte, which is stored in the Pointer register in the PCA6416A. The lower three
bits of this data byte state the operation (read or write) and the internal registers (Input,
Output, Polarity Inversion, or Configuration) that will be affected. This register is write only.
Once a new command has been sent, the register that was last addressed continues to
be accessed by reads until a new command byte is sent.
B7
B6
B5
B4
B3
B2
B1
B0
002aaf540
Fig 7.
Table 6.
Pointer register bits
Command byte
Pointer register bits
B7
B6
B5
B4
B3
B2
B1
B0
Command
byte
0
0
0
0
0
0
0
0
00h
Input port 0
0
0
0
0
0
0
0
1
01h
Input port 1
read byte
xxxx xxxx
0
0
0
0
0
0
1
0
02h
Output port 0
read/write byte
1111 1111
0
0
0
0
0
0
1
1
03h
Output port 1
read/write byte
1111 1111
0
0
0
0
0
1
0
0
04h
Polarity Inversion port 0
read/write byte
0000 0000
0
0
0
0
0
1
0
1
05h
Polarity Inversion port 1
read/write byte
0000 0000
0
0
0
0
0
1
1
0
06h
Configuration port 0
read/write byte
1111 1111
0
0
0
0
0
1
1
1
07h
Configuration port 1
read/write byte
1111 1111
[1]
Register
Protocol
Power-up
default
read byte
xxxx xxxx[1]
Undefined.
PCA6416A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 January 2013
© NXP B.V. 2013. All rights reserved.
7 of 42
PCA6416A
NXP Semiconductors
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
7.4 Register descriptions
7.4.1 Input port registers (00h, 01h)
The Input port registers (registers 0 and 1) reflect the incoming logic levels of the pins,
regardless of whether the pin is defined as an input or an output by the Configuration
register. The Input port registers are read only; writes to these registers have no effect.
The default value ‘X’ is determined by the externally applied logic level. An Input port
register read operation is performed as described in Section 8.2.
Table 7.
Bit
Input port 0 register (address 00h)
7
6
5
4
3
2
1
0
Symbol
I0.7
I0.6
I0.5
I0.4
I0.3
I0.2
I0.1
I0.0
Default
X
X
X
X
X
X
X
X
Table 8.
Bit
Input port 1 register (address 01h)
7
6
5
4
3
2
1
0
Symbol
I1.7
I1.6
I1.5
I1.4
I1.3
I1.2
I1.1
I1.0
Default
X
X
X
X
X
X
X
X
7.4.2 Output port registers (02h, 03h)
The Output port registers (registers 2 and 3) shows the outgoing logic levels of the pins
defined as outputs by the Configuration register. Bit values in these registers have no
effect on pins defined as inputs. In turn, reads from these registers reflect the value that
was written to these registers, not the actual pin value. A register pair write is described in
Section 8.1 and a register pair read is described in Section 8.2.
Table 9.
Bit
7
6
5
4
3
2
1
0
Symbol
O0.7
O0.6
O0.5
O0.4
O0.3
O0.2
O0.1
O0.0
Default
1
1
1
1
1
1
1
1
Table 10.
Bit
PCA6416A
Product data sheet
Output port 0 register (address 02h)
Output port 1 register (address 03h)
7
6
5
4
3
2
1
0
Symbol
O1.7
O1.6
O1.5
O1.4
O1.3
O1.2
O1.1
O1.0
Default
1
1
1
1
1
1
1
1
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 January 2013
© NXP B.V. 2013. All rights reserved.
8 of 42
PCA6416A
NXP Semiconductors
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
7.4.3 Polarity inversion registers (04h, 05h)
The Polarity inversion registers (registers 4 and 5) allow polarity inversion of pins defined
as inputs by the Configuration register. If a bit in these registers is set (written with ‘1’), the
corresponding port pin’s polarity is inverted in the input register. If a bit in this register is
cleared (written with a ‘0’), the corresponding port pin’s polarity is retained. A register pair
write is described in Section 8.1 and a register pair read is described in Section 8.2.
Table 11.
Bit
Polarity inversion port 0 register (address 04h)
7
6
5
4
3
2
1
0
Symbol
N0.7
N0.6
N0.5
N0.4
N0.3
N0.2
N0.1
N0.0
Default
0
0
0
0
0
0
0
0
Table 12.
Bit
Polarity inversion port 1 register (address 05h)
7
6
5
4
3
2
1
0
Symbol
N1.7
N1.6
N1.5
N1.4
N1.3
N1.2
N1.1
N1.0
Default
0
0
0
0
0
0
0
0
7.4.4 Configuration registers (06h, 07h)
The Configuration registers (registers 6 and 7) configure the direction of the I/O pins. If a
bit in these registers is set to 1, the corresponding port pin is enabled as a
high-impedance input. If a bit in these registers is cleared to 0, the corresponding port pin
is enabled as an output. A register pair write is described in Section 8.1 and a register pair
read is described in Section 8.2.
Table 13.
Bit
7
6
5
4
3
2
1
0
Symbol
C0.7
C0.6
C0.5
C0.4
C0.3
C0.2
C0.1
C0.0
Default
1
1
1
1
1
1
1
1
Table 14.
Bit
PCA6416A
Product data sheet
Configuration port 0 register (address 06h)
Configuration port 1 register (address 07h)
7
6
5
4
3
2
1
0
Symbol
C1.7
C1.6
C1.5
C1.4
C1.3
C1.2
C1.1
C1.0
Default
1
1
1
1
1
1
1
1
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 January 2013
© NXP B.V. 2013. All rights reserved.
9 of 42
PCA6416A
NXP Semiconductors
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
7.5 I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a
high-impedance input. The input voltage may be raised above VDD(P) to a maximum of
5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the
Output port register. In this case, there are low-impedance paths between the I/O pin and
either VDD(P) or VSS. The external voltage applied to this I/O pin should not exceed the
recommended levels for proper operation.
data from
shift register
data from
shift register
output port
register data
configuration
register
D
VDD(P)
Q1
Q
FF
write
configuration
pulse
CK
Q
D
Q
FF
write pulse
Q2
CK
output port
register
input port
register
D
Q
FF
read pulse
ESD
protection
diode
P0_0 to P0_7
P1_0 to P1_7
VSS
input port
register data
CK
to INT
polarity
inversion
register
data from
shift register
D
Q
FF
write polarity
pulse
polarity
inversion
register data
CK
002aaf538
On power-up or reset, all registers return to default values.
Fig 8.
Simplified schematic of P0_0 to P1_7
7.6 Power-on reset
When power (from 0 V) is applied to VDD(P), an internal power-on reset holds the
PCA6416A in a reset condition until VDD(P) has reached VPOR. At that time, the reset
condition is released and the PCA6416A registers and I2C-bus/SMBus state machine
initializes to their default states. After that, VDD(P) must be lowered to below VPOR and
back up to the operating voltage for a power-reset cycle. See Section 9.2 “Power-on reset
requirements”.
PCA6416A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 January 2013
© NXP B.V. 2013. All rights reserved.
10 of 42
PCA6416A
NXP Semiconductors
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
7.7 Reset input (RESET)
The RESET input can be asserted to initialize the system while keeping the VDD(P) at its
operating level. A reset can be accomplished by holding the RESET pin LOW for a
minimum of tw(rst). The PCA6416A registers and I2C-bus/SMBus state machine are
changed to their default state once RESET is LOW (0). When RESET is HIGH (1), the I/O
levels at the P port can be changed externally or through the master. This input requires a
pull-up resistor to VDD(I2C-bus) if no active connection is used.
7.8 Interrupt output (INT)
An interrupt is generated by any rising or falling edge of the port inputs in the Input mode.
After time tv(INT), the signal INT is valid. The interrupt is reset when data on the port
changes back to the original value or when data is read from the port that generated the
interrupt (see Figure 12). Resetting occurs in the Read mode at the acknowledge (ACK)
or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that
occur during the ACK or NACK clock pulse can be lost (or be very short) due to the
resetting of the interrupt during this pulse. Any change of the I/Os after resetting is
detected and is transmitted as INT.
A pin configured as an output cannot cause an interrupt. Changing an I/O from an output
to an input may cause a false interrupt to occur, if the state of the pin does not match the
contents of the Input Port register.
The INT output has an open-drain structure and requires pull-up resistor to VDD(P) or
VDD(I2C-bus) depending on the application. INT should be connected to the voltage source
of the device that requires the interrupt information.
8. Bus transactions
The PCA6416A is an I2C-bus slave device. Data is exchanged between the master and
PCA6416A through write and read commands using I2C-bus. The two communication
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Write commands
Data is transmitted to the PCA6416A by sending the device address and setting the Least
Significant Bit (LSB) to a logic 0 (see Figure 6 for device address). The command byte is
sent after the address and determines which register receives the data that follows the
command byte.
The eight registers within the PCA6416A are configured to operate as four register pairs.
The four pairs are input ports, output ports, polarity inversion and configuration registers.
After sending data to one register, the next data byte is sent to the other register in the pair
(see Figure 9 and Figure 10). For example, if the first byte is sent to Output Port 1
(register 3), the next byte is stored in Output Port 0 (register 2).
There is no limit on the number of data bytes sent in one write transmission. In this way,
the host can continuously update a register pair independently of the other registers or the
host can simply update a single register.
PCA6416A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 January 2013
© NXP B.V. 2013. All rights reserved.
11 of 42
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
1
2
3
4
5
6
7
8
9
slave address
0
SDA S
1
0
0
START condition
R/W
A
0
0
0
0
0
0
acknowledge
from slave
1
0
A 0.7
STOP
condition
data to port 1
data to port 0
command byte
AD
0 DR 0
0
NXP Semiconductors
PCA6416A
Product data sheet
SCL
DATA 0
0.0 A 1.7
acknowledge
from slave
DATA 1
1.0 A
P
acknowledge
from slave
acknowledge
from slave
write to port
tv(Q)
DATA 0 VALID
tv(Q)
DATA 1 VALID
data out from port 1
002aaf556
Fig 9.
Write to Output port register
SCL
1
2
3
4
5
6
7
8
9
slave address
SDA S
0
1
0
0
0
0 AD 0
DR
R/W
A
0
0
0
12 of 42
© NXP B.V. 2013. All rights reserved.
acknowledge
from slave
0
0 1/0 1/0 1/0 A
MSB
acknowledge
from slave
STOP
condition
data to register
DATA 0
A
LSB
MSB
acknowledge
from slave
DATA 1
A
P
LSB
acknowledge
from slave
002aaf557
Fig 10. Write to device registers
PCA6416A
START condition
data to register
command byte
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
Rev. 2 — 10 January 2013
All information provided in this document is subject to legal disclaimers.
data out from port 0
PCA6416A
NXP Semiconductors
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
8.2 Read commands
To read data from the PCA6416A, the bus master must first send the PCA6416A address
with the least significant bit set to a logic 0 (see Figure 6 for device address).
The command byte is sent after the address and determines which register is to be
accessed.
After a restart, the device address is sent again, but this time the least significant bit is set
to a logic 1. Data from the register defined by the command byte is sent by the PCA6416A
(see Figure 11 and Figure 12). Data is clocked into the register on the rising edge of the
ACK clock pulse. After the first byte is read, additional bytes may be read, but the data
now reflects the information in the other register in the pair. For example, if Input Port 1 is
read, the next byte read is Input Port 0.There is no limit on the number of data bytes
received in one read transmission, but on the final byte received the bus master must not
acknowledge the data.
After a subsequent restart, the command byte contains the value of the next register to be
read in the pair. For example, if Input Port 1 was read last before the restart, the register
that is read after the restart is the Input Port 0.
command byte
slave address
SDA S
0
1
0
0
0 AD 0
DR
0
START condition
0
A
0
0
R/W
0
(cont.)
0 1/0 1/0 1/0 A
acknowledge
from slave
acknowledge
from slave
data from lower or
upper byte of register
slave address
(cont.) S
0
1
0
0
(repeated)
START condition
0
MSB
0 AD 1
DR
A
R/W
acknowledge
from slave
data from upper or
lower byte of register
LSB
DATA (first byte)
MSB
A
acknowledge
from master
LSB
DATA (last byte)
NA
no acknowledge
from master
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
P
STOP
condition
002aaf558
Fig 11. Read from device registers
PCA6416A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 January 2013
© NXP B.V. 2013. All rights reserved.
13 of 42
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
NXP Semiconductors
PCA6416A
Product data sheet
data into port 0
data into port 1
tv(INT)
SCL
1
2
3
4
trst(INT)
5
6
slave address
SDA S
0
1
0
0
START condition
0
7
8
9
R/W
0 AD 1
DR
I0.x
A
7
6
5
acknowledge
from slave
4
3
I1.x
2
1
0
A
acknowledge
from master
7
6
5
4
3
I0.x
2
1
0
A
acknowledge
from master
7
6
5
4
3
STOP condition
I1.x
2
1
0
A
acknowledge
from master
7
6
5
4
3
2
1
0
1
P
non acknowledge
from master
read from port 0
read from port 1
002aah131
This figure eliminates the command byte transfer and a restart between the initial slave address call and actual data transfer from P port (see Figure 11).
Fig 12. Read input port register, scenario 1
PCA6416A
14 of 42
© NXP B.V. 2013. All rights reserved.
Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode).
It is assumed that the command byte has previously been set to ‘00’ (read input port register).
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
Rev. 2 — 10 January 2013
All information provided in this document is subject to legal disclaimers.
INT
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
DATA 00
DATA 01
DATA 02
DATA 03
tsu(D)
th(D)
data into port 1
NXP Semiconductors
PCA6416A
Product data sheet
data into port 0
DATA 10
DATA 11
DATA 12
tsu(D)
th(D)
tv(INT)
SCL
1
2
3
4
trst(INT)
5
6
slave address
SDA S
0
1
0
0
START condition
0
7
8
9
R/W
0 AD 1
DR
I0.x
A
acknowledge
from slave
DATA 00
I1.x
A
acknowledge
from master
DATA 10
I0.x
A
acknowledge
from master
DATA 03
I1.x
A
acknowledge
from master
STOP condition
DATA 12
1
P
non acknowledge
from master
read from port 0
read from port 1
002aah132
This figure eliminates the command byte transfer and a restart between the initial slave address call and actual data transfer from P port (see Figure 11).
Fig 13. Read input port register, scenario 2
PCA6416A
15 of 42
© NXP B.V. 2013. All rights reserved.
Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode).
It is assumed that the command byte has previously been set to ‘00’ (read input port register).
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
Rev. 2 — 10 January 2013
All information provided in this document is subject to legal disclaimers.
INT
PCA6416A
NXP Semiconductors
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
9. Application design-in information
VDD(I2C-bus)
VDD(P)
10 kΩ (× 7)
VDD(I2C-bus) = 1.8 V
10 kΩ
VDD
10 kΩ
10 kΩ
SUBSYSTEM 1
(e.g., alarm system)
10 kΩ
VDD(I2C-bus)
MASTER
CONTROLLER
SCL
SDA
INT
RESET
ALARM(1)
VDD(P)
P0_0
P0_1
SCL
SDA
A
controlled
switch
enable
PCA9614A
B
INT
RESET
P0_2
P0_3
VSS
P0_4
P0_5
P0_6
P0_7
P1_0
KEYPAD
P1_1
P1_2
P1_3
ADDR
P1_4
P1_5
P1_6
VSS
P1_7
002aaf594
Device address configured as 0100 000x for this example.
P0_0 and P0_2 through P1_0 are configured as inputs.
P0_1 and P1_1 through P1_7 are configured as outputs.
(1) External resistors are required for inputs (on P port) that may float. If a driver to an input will never let the input float, a resistor
is not needed. If an output in the P port is configured as a push-pull output there is no need for external pull-up resistors. If an
output in the P port is configured as an open-drain output, external pull-up resistors are required.
Fig 14. Typical application
9.1 Minimizing IDD when the I/Os are used to control LEDs
When the I/Os are used to control LEDs, they are normally connected to VDD(P) through a
resistor as shown in Figure 14. Since the LED acts as a diode, when the LED is off the I/O
VI is about 1.2 V less than VDD(P). The supply current, IDD(P), increases as VI becomes
lower than VDD(P).
Designs needing to minimize current consumption, such as battery power applications,
should consider maintaining the I/O pins greater than or equal to VDD(P) when the LED is
off. Figure 15 shows a high value resistor in parallel with the LED. Figure 16 shows VDD(P)
less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O
VI at or above VDD(P) and prevents additional supply current consumption when the LED is
off.
PCA6416A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 January 2013
© NXP B.V. 2013. All rights reserved.
16 of 42
PCA6416A
NXP Semiconductors
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
3.3 V
VDD
VDD(P)
LED
5V
VDD(P)
100 kΩ
LED
Pn
Pn
002aah278
002aah279
Fig 15. High value resistor in parallel with
the LED
Fig 16. Device supplied by a lower voltage
9.2 Power-on reset requirements
In the event of a glitch or data corruption, PCA6416A can be reset to its default conditions
by using the power-on reset feature. Power-on reset requires that the device go through a
power cycle to be completely reset. This reset also happens when the device is
powered on for the first time in an application.
The two types of power-on reset are shown in Figure 17 and Figure 18.
VDD(P)
ramp-up
ramp-down
re-ramp-up
td(rst)
time
(dV/dt)r
(dV/dt)f
time to re-ramp
when VDD(P) drops
below 0.2 V or to VSS
(dV/dt)r
002aag960
Fig 17. VDD(P) is lowered below 0.2 V or to 0 V and then ramped up to VDD(P)
VDD(P)
ramp-down
ramp-up
td(rst)
VI drops below POR levels
(dV/dt)f
time to re-ramp
when VDD(P) drops
to VPOR(min) − 50 mV
time
(dV/dt)r
002aag961
Fig 18. VDD(P) is lowered below the POR threshold, then ramped back up to VDD(P)
Table 15 specifies the performance of the power-on reset feature for PCA6416A for both
types of power-on reset.
PCA6416A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 January 2013
© NXP B.V. 2013. All rights reserved.
17 of 42
PCA6416A
NXP Semiconductors
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
Table 15. Recommended supply sequencing and ramp rates
Tamb = 25 C (unless otherwise noted). Not tested; specified by design.
Symbol
Parameter
Condition
Min
Typ
Max
Unit
(dV/dt)f
fall rate of change of voltage
Figure 17
0.1
-
2000
ms
(dV/dt)r
rise rate of change of voltage
Figure 17
0.1
-
2000
ms
td(rst)
reset delay time
Figure 17; re-ramp time when
VDD(P) drops below 0.2 V or to VSS
1
-
-
s
Figure 18; re-ramp time when
VDD(P) drops to VPOR(min)  50 mV
1
-
-
s
VDD(gl)
glitch supply voltage difference
Figure 19
[1]
-
-
1.0
V
[2]
-
-
10
s
tw(gl)VDD
supply voltage glitch pulse width
Figure 19
VPOR(trip)
power-on reset trip voltage
falling VDD(P)
0.7
-
-
V
rising VDD(P)
-
-
1.4
V
[1]
Level that VDD(P) can glitch down to with a ramp rate at 0.4 s/V, but not cause a functional disruption when tw(gl)VDD < 1 s.
[2]
Glitch width that will not cause a functional disruption when VDD(gl) = 0.5  VDD(P).
Glitches in the power supply can also affect the power-on reset performance of this
device. The glitch width (tw(gl)VDD) and glitch height (VDD(gl)) are dependent on each
other. The bypass capacitance, source impedance, and device impedance are factors that
affect power-on reset performance. Figure 19 and Table 15 provide more information on
how to measure these specifications.
VDD(P)
∆VDD(gl)
tw(gl)VDD
time
002aag962
Fig 19. Glitch width and glitch height
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition
is released and all the registers and the I2C-bus/SMBus state machine are initialized to
their default states. The value of VPOR differs based on the VDD being lowered to or from
0 V. Figure 20 and Table 15 provide more details on this specification.
VDD(P)
VPOR (rising VDD(P))
VPOR (falling VDD(P))
time
POR
time
002aag963
Fig 20. Power-on reset voltage (VPOR)
PCA6416A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 January 2013
© NXP B.V. 2013. All rights reserved.
18 of 42
PCA6416A
NXP Semiconductors
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
10. Limiting values
Table 16. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD(I2C-bus)
I2C-bus
Conditions
Min
Max
Unit
0.5
+6.5
V
VDD(P)
supply voltage port P
VI
input voltage
[1]
0.5
+6.5
V
0.5
+6.5
VO
output voltage
[1]
V
0.5
+6.5
V
IIK
input clamping current
ADDR, RESET, SCL; VI < 0 V
-
20
mA
IOK
IIOK
output clamping current
INT; VO < 0 V
-
20
mA
input/output clamping current
P port; VO < 0 V or VO > VDD(P)
-
20
mA
SDA; VO < 0 V or VO > VDD(I2C-bus)
-
20
mA
continuous; P port; VO = 0 V to VDD(P)
-
50
mA
continuous; SDA, INT; VO = 0 V to
VDD(I2C-bus)
-
25
mA
supply voltage
LOW-level output current
IOL
IOH
HIGH-level output current
continuous; P port; VO = 0 V to VDD(P)
-
25
mA
IDD
supply current
continuous through VSS
-
200
mA
IDD(P)
supply current port P
continuous through VDD(P)
-
160
mA
IDD(I2C-bus)
I2C-bus supply current
continuous through VDD(I2C-bus)
-
10
mA
Tstg
storage temperature
65
+150
C
Tj(max)
maximum junction temperature
-
125
C
[1]
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
11. Recommended operating conditions
Table 17.
Operating conditions
Symbol
Parameter
VDD(I2C-bus)
I2C-bus
VDD(P)
supply voltage port P
VIH
HIGH-level input voltage
VIL
Conditions
Min
Max
1.65
5.5
V
1.65
5.5
V
SCL, SDA, RESET
0.7  VDD(I2C-bus) 5.5
V
ADDR, P1_7 to P0_0
0.7  VDD(P)
5.5
V
SCL, SDA, RESET
0.5
0.3  VDD(I2C-bus) V
ADDR, P1_7 to P0_0
0.5
0.3  VDD(P)
V
supply voltage
LOW-level input voltage
Unit
IOH
HIGH-level output current
P1_7 to P0_0
-
10
mA
IOL
LOW-level output current
P1_7 to P0_0
-
25
mA
Tamb
ambient temperature
operating in free air
40
+85
C
PCA6416A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 January 2013
© NXP B.V. 2013. All rights reserved.
19 of 42
PCA6416A
NXP Semiconductors
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
12. Thermal characteristics
Table 18.
Symbol
Zth(j-a)
[1]
Thermal characteristics
Parameter
Conditions
transient thermal impedance from junction to ambient
Max
Unit
TSSOP24 package
[1]
88
K/W
HWQFN24 package
[1]
66
K/W
VFBGA24 package
[1]
171
K/W
The package thermal impedance is calculated in accordance with JESD 51-7.
13. Static characteristics
Table 19. Static characteristics
Tamb = 40 C to +85 C; VDD(I2C-bus) = 1.65 V to 5.5 V; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1] Max
Unit
VIK
input clamping voltage
II = 18 mA
1.2
-
-
V
VPOR
power-on reset voltage
VI = VDD(P) or VSS; IO = 0 mA
-
1.1
1.4
V
VOH
HIGH-level output voltage
P port
VOL
IOL
LOW-level output voltage
LOW-level output current
IOH = 8 mA; VDD(P) = 1.65 V
[2]
1.2
-
-
V
IOH = 10 mA; VDD(P) = 1.65 V
[2]
1.1
-
-
V
IOH = 8 mA; VDD(P) = 2.3 V
[2]
1.8
-
-
V
IOH = 10 mA; VDD(P) = 2.3 V
[2]
1.7
-
-
V
IOH = 8 mA; VDD(P) = 3.0 V
[2]
2.6
-
-
V
IOH = 10 mA; VDD(P) = 3.0 V
[2]
2.5
-
-
V
IOH = 8 mA; VDD(P) = 4.5 V
[2]
4.1
-
-
V
IOH = 10 mA; VDD(P) = 4.5 V
[2]
4.0
-
-
V
VDD(P) = 1.65 V
[2]
-
-
0.45
V
VDD(P) = 2.3 V
[2]
-
-
0.25
V
VDD(P) = 3 V
[2]
-
-
0.25
V
VDD(P) = 4.5 V
[2]
-
-
0.2
V
SDA
[3]
3
-
-
mA
INT
[3]
3
15[4]
-
mA
VOL = 0.5 V; VDD(P) = 1.65 V
[3]
8
10
-
mA
VOL = 0.7 V; VDD(P) = 1.65 V
[3]
10
13
-
mA
VOL = 0.5 V; VDD(P) = 2.3 V
[3]
8
10
-
mA
VOL = 0.7 V; VDD(P) = 2.3 V
[3]
10
13
-
mA
VOL = 0.5 V; VDD(P) = 3.0 V
[3]
8
14
-
mA
VOL = 0.7 V; VDD(P) = 3.0 V
[3]
10
19
-
mA
VOL = 0.5 V; VDD(P) = 4.5 V
[3]
8
17
-
mA
VOL = 0.7 V; VDD(P) = 4.5 V
[3]
10
24
-
mA
P port; IOL = 8 mA
VOL = 0.4 V; VDD(P) = 1.65 V to 5.5 V
P port
PCA6416A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 January 2013
© NXP B.V. 2013. All rights reserved.
20 of 42
PCA6416A
NXP Semiconductors
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
Table 19. Static characteristics …continued
Tamb = 40 C to +85 C; VDD(I2C-bus) = 1.65 V to 5.5 V; unless otherwise specified.
Min
Typ[1] Max
SCL, SDA, RESET; VI = VDD(I2C-bus) or VSS
-
-
1
A
ADDR; VI = VDD(P) or VSS
Symbol
Parameter
Conditions
II
input current
VDD(P) = 1.65 V to 5.5 V
Unit
-
-
1
A
IIH
HIGH-level input current
P port; VI = VDD(P); VDD(P) = 1.65 V to 5.5 V
-
-
1
A
IIL
LOW-level input current
P port; VI = VSS; VDD(P) = 1.65 V to 5.5 V
-
-
1
A
IDD
supply current
IDD(I2C-bus) + IDD(P);
SDA, P port, ADDR, RESET;
VI on SDA and RESET = VDD(I2C-bus) or VSS;
VI on P port and ADDR = VDD(P);
IO = 0 mA; I/O = inputs; fSCL = 400 kHz
VDD(P) = 3.6 V to 5.5 V
-
10
25
A
VDD(P) = 2.3 V to 3.6 V
-
6.5
15
A
VDD(P) = 1.65 V to 2.3 V
-
4
9
A
IDD(I2C-bus) + IDD(P);
SCL, SDA, P port, ADDR, RESET;
VI on SCL, SDA and RESET = VDD(I2C-bus) or VSS;
VI on P port and ADDR = VDD(P);
IO = 0 mA; I/O = inputs; fSCL = 0 kHz
VDD(P) = 3.6 V to 5.5 V
-
1.5
7
A
VDD(P) = 2.3 V to 3.6 V
-
1
3.2
A
VDD(P) = 1.65 V to 2.3 V
-
0.5
1.7
A
VDD(P) = 3.6 V to 5.5 V
-
60
125
A
VDD(P) = 2.3 V to 3.6 V
-
40
75
A
VDD(P) = 1.65 V to 2.3 V
-
20
45
A
SCL, SDA, RESET;
one input at VDD(I2C-bus)  0.6 V,
other inputs at VDD(I2C-bus) or VSS;
VDD(P) = 1.65 V to 5.5 V
-
-
25
A
P port, ADDR; one input at VDD(P)  0.6 V,
other inputs at VDD(P) or VSS;
VDD(P) = 1.65 V to 5.5 V
-
-
80
A
Active mode; IDD(I2C-bus) + IDD(P);
P port, ADDR, RESET;
VI on RESET = VDD(I2C-bus);
VI on P port and ADDR = VDD(P);
IO = 0 mA; I/O = inputs;
fSCL = 400 kHz, continuous register read
IDD
additional quiescent
supply current
Ci
input capacitance
VI = VDD(I2C-bus) or VSS; VDD(P) = 1.65 V to 5.5 V
-
6
7
pF
Cio
input/output capacitance
VI/O = VDD(I2C-bus) or VSS; VDD(P) = 1.65 V to 5.5 V
-
7
8
pF
VI/O = VDD(P) or VSS; VDD(P) = 1.65 V to 5.5 V
-
7.5
8.5
pF
[1]
For IDD, all typical values are at nominal supply voltage (1.8 V, 2.5 V, 3.3 V, 3.6 V or 5 V VDD) and Tamb = 25 C. Except for IDD, the
typical values are at VDD(P) = VDD(I2C-bus) = 3.3 V and Tamb = 25 C.
[2]
The total current sourced by all I/Os must be limited to 160 mA.
[3]
Each I/O must be externally limited to a maximum of 25 mA, for a device total of 200 mA.
[4]
Typical value for Tamb = 25 C. VOL = 0.4 V and VDD = 3.3 V. Typical value for VDD < 2.5 V, VOL = 0.6 V.
PCA6416A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 January 2013
© NXP B.V. 2013. All rights reserved.
21 of 42
PCA6416A
NXP Semiconductors
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
13.1 Typical characteristics
002aag973
20
002aag974
1400
IDD
(μA)
IDD(stb)
(nA)
16
VDD(P) = 5.5 V
5.0 V
3.6 V
12
3.3 V
2.5 V
2.3 V
8
VDD(P) = 5.5 V
5.0 V
3.6 V
3.3 V
1000
800
600
400
2.5 V
2.3 V
1.8 V
1.65 V
4
0
−40
200
VDD(P) = 1.8 V
1.65 V
−15
10
35
0
−40
60
85
Tamb (°C)
−15
10
35
60
85
Tamb (°C)
IDD = IDD(I2C-bus) + IDD(P)
Fig 21. Supply current versus ambient temperature
Fig 22. Standby supply current versus
ambient temperature
002aag975
20
IDD
(μA)
16
12
8
4
0
1.5
2.5
3.5
4.5
5.5
VDD(P) (V)
Tamb = 25 C
IDD = IDD(I2C-bus) + IDD(P)
Fig 23. Supply current versus supply voltage
PCA6416A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 January 2013
© NXP B.V. 2013. All rights reserved.
22 of 42
PCA6416A
NXP Semiconductors
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
Isink
(mA)
002aaf578
35
Isink
(mA)
30
Tamb = −40 °C
25 °C
85 °C
25
002aaf579
35
30
Tamb = −40 °C
25 °C
85 °C
25
20
20
15
15
10
10
5
5
0
0
0
0.1
0.2
0.3
0
0.1
0.2
VOL (V)
a. VDD(P) = 1.65 V
Isink
(mA)
b. VDD(P) = 1.8 V
002aaf580
50
002aaf581
60
Isink
(mA)
40
Tamb = −40 °C
25 °C
85 °C
30
0.3
VOL (V)
Tamb = −40 °C
25 °C
85 °C
40
20
20
10
0
0
0
0.1
0.2
0.3
0
0.1
0.2
VOL (V)
c. VDD(P) = 2.5 V
Isink
(mA)
d. VDD(P) = 3.3 V
002aaf582
70
Isink
(mA)
Tamb = −40 °C
25 °C
85 °C
60
50
0.3
VOL (V)
002aaf583
70
Tamb = −40 °C
25 °C
85 °C
60
50
40
40
30
30
20
20
10
10
0
0
0
0.1
0.2
0.3
0
0.1
VOL (V)
0.2
0.3
VOL (V)
e. VDD(P) = 5.0 V
f. VDD(P) = 5.5 V
Fig 24. I/O sink current versus LOW-level output voltage
PCA6416A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 January 2013
© NXP B.V. 2013. All rights reserved.
23 of 42
PCA6416A
NXP Semiconductors
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
002aaf561
30
Isource
(mA)
Isource
(mA)
Tamb = −40 °C
25 °C
85 °C
20
002aaf562
35
Tamb = −40 °C
25 °C
85 °C
30
25
20
15
10
10
5
0
0
0
0.2
0.4
0.6
VDD(P) − VOH (V)
0
a. VDD(P) = 1.65 V
002aaf563
Isource
(mA)
Tamb = −40 °C
25 °C
85 °C
40
0.4
0.6
VDD(P) − VOH (V)
b. VDD(P) = 1.8 V
60
Isource
(mA)
0.2
002aaf564
70
Tamb = −40 °C
25 °C
85 °C
60
50
40
30
20
20
10
0
0
0
0.2
0.4
0.6
VDD(P) − VOH (V)
c. VDD(P) = 2.5 V
002aaf565
0.4
0.6
VDD(P) − VOH (V)
002aaf566
90
Isource
(mA)
Tamb = −40 °C
25 °C
85 °C
60
0.2
d. VDD(P) = 3.3 V
90
Isource
(mA)
0
Tamb = −40 °C
25 °C
85 °C
60
30
30
0
0
0
0.2
0.4
0.6
VDD(P) − VOH (V)
e. VDD(P) = 5.0 V
0
0.2
0.4
0.6
VDD(P) − VOH (V)
f. VDD(P) = 5.5 V
Fig 25. I/O source current versus HIGH-level output voltage
PCA6416A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 January 2013
© NXP B.V. 2013. All rights reserved.
24 of 42
PCA6416A
NXP Semiconductors
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
VOL
(mV)
002aah056
120
100
002aah057
200
VDD(P) − VOH (mV)
160
(1)
80
120
VDD(P) = 1.8 V
5V
60
(2)
80
40
(4)
20
0
−40
40
(3)
−15
10
35
60
85
Tamb (°C)
0
−40
−15
10
35
60
85
Tamb (°C)
Isource = 10 mA
(1) VDD(P) = 1.8 V; Isink = 10 mA
(2) VDD(P) = 5 V; Isink = 10 mA
(3) VDD(P) = 1.8 V; Isink = 1 mA
(4) VDD(P) = 5 V; Isink = 1 mA
Fig 26. LOW-level output voltage versus temperature
PCA6416A
Product data sheet
Fig 27. I/O high voltage versus temperature
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 January 2013
© NXP B.V. 2013. All rights reserved.
25 of 42
PCA6416A
NXP Semiconductors
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
14. Dynamic characteristics
Table 20. I2C-bus interface timing requirements
Over recommended operating free air temperature range, unless otherwise specified. See Figure 29.
Conditions
Standard-mode
I2C-bus
Fast-mode I2C-bus
Symbol
Parameter
Unit
Min
Max
Min
Max
fSCL
SCL clock frequency
0
100
0
400
tHIGH
HIGH period of the SCL clock
4
-
0.6
-
s
tLOW
LOW period of the SCL clock
4.7
-
1.3
-
s
tSP
pulse width of spikes that must
be suppressed by the input filter
0
50
0
50
ns
tSU;DAT
data set-up time
250
-
100
-
ns
tHD;DAT
data hold time
0
-
0
-
ns
kHz
tr
rise time of both SDA and SCL signals
-
1000
20
300
ns
tf
fall time of both SDA and SCL signals
-
300
20 
(VDD / 5.5 V)
300
ns
tBUF
bus free time between a STOP and
START condition
4.7
-
1.3
-
s
tSU;STA
set-up time for a repeated START
condition
4.7
-
0.6
-
s
tHD;STA
hold time (repeated) START condition
4
-
0.6
-
s
tSU;STO
set-up time for STOP condition
4
-
0.6
-
s
tVD;DAT
data valid time
SCL LOW to
SDA output valid
-
3.45
-
0.9
s
tVD;ACK
data valid acknowledge time
ACK signal from
SCL LOW to
SDA (out) LOW
-
3.45
-
0.9
s
Table 21. Reset timing requirements
Over recommended operating free air temperature range, unless otherwise specified. See Figure 31.
Symbol
Parameter
tw(rst)
reset pulse width
trec(rst)
reset recovery time
trst
reset time
[1]
Conditions
Standard-mode
I2C-bus
[1]
Fast-mode
I2C-bus
Unit
Min
Max
Min
Max
30
-
30
-
ns
200
-
200
-
ns
600
-
600
-
ns
Minimum time for SDA to become HIGH or minimum time to wait before doing a START.
PCA6416A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 January 2013
© NXP B.V. 2013. All rights reserved.
26 of 42
PCA6416A
NXP Semiconductors
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
Table 22. Switching characteristics
Over recommended operating free air temperature range; CL  100 pF; unless otherwise specified. See Figure 30.
Symbol
Parameter
Conditions
Standard-mode
I2C-bus
Fast-mode
I2C-bus
Min
Max
Min
Max
Unit
tv(INT)
valid time on pin INT
from P port to INT
-
1
-
1
s
trst(INT)
reset time on pin INT
from SCL to INT
-
1
-
1
s
tv(Q)
data output valid time
from SCL to P port
-
400
-
400
ns
tsu(D)
data input set-up time
from P port to SCL
0
-
0
-
ns
th(D)
data input hold time
from P port to SCL
300
-
300
-
ns
15. Parameter measurement information
VDD(I2C-bus)
RL = 1 kΩ
DUT
SDA
CL = 50 pF
002aag977
a. SDA load configuration
two bytes for read Input port register(1)
STOP
START
condition condition
(P)
(S)
Address
Bit 7
(MSB)
Address
Bit 1
R/W
Bit 0
(LSB)
ACK
(A)
Data
Bit 7
(MSB)
Data
Bit 0
(LSB)
STOP
condition
(P)
002aag952
b. Transaction format
tHIGH
tLOW
tSP
0.7 × VDD(I2C-bus)
0.3 × VDD(I2C-bus)
SCL
tBUF
tVD;DAT
tr
tf
tf(o)
tVD;ACK
tSU;STA
0.7 × VDD(I2C-bus)
SDA
tf
tHD;STA
tr
0.3 × VDD(I2C-bus)
tVD;ACK
tSU;DAT
tSU;STO
tHD;DAT
repeat START condition
STOP condition
002aag978
c. Voltage waveforms
CL includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR  10 MHz; Zo = 50 ; tr/tf  30 ns.
All parameters and waveforms are not applicable to all devices.
Byte 1 = I2C-bus address; Byte 2, byte 3 = P port data.
(1) See Figure 12.
Fig 28. I2C-bus interface load circuit and voltage waveforms
PCA6416A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 January 2013
© NXP B.V. 2013. All rights reserved.
27 of 42
PCA6416A
NXP Semiconductors
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
VDD(I2C-bus)
RL = 4.7 kΩ
INT
DUT
CL = 100 pF
002aag979
a. Interrupt load configuration
acknowledge
from slave
START condition
R/W
8 bits (one data byte)
from port
slave address
SDA S
SCL
0
1
0
1
2
3
0
4
0
5
0 AD 1
DR
6
7
8
acknowledge
from slave
DATA 1
A
no acknowledge
from master
STOP
condition
data from port
A
DATA 2
1
P
9
B
trst(INT) B
trst(INT)
INT
tv(INT)
data into
port
A
A
tsu(D)
ADDRESS
INT
DATA 1
0.5 × VDD(I2C-bus)
SCL
DATA 2
R/W
0.3 × VDD(I2C-bus)
tv(INT)
trst(INT)
0.5 × VDD(P)
Pn
0.7 × VDD(I2C-bus)
A
0.5 × VDD(I2C-bus)
INT
View A - A
View B - B
002aag980
b. Voltage waveforms
CL includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR  10 MHz; Zo = 50 ; tr/tf  30 ns.
All parameters and waveforms are not applicable to all devices.
Fig 29. Interrupt load circuit and voltage waveforms
PCA6416A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 January 2013
© NXP B.V. 2013. All rights reserved.
28 of 42
PCA6416A
NXP Semiconductors
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
500 Ω
Pn
DUT
2 × VDD(P)
CL = 50 pF
500 Ω
002aag981
a. P port load configuration
SCL
P0
A
P7
0.7 × VDD(I2C-bus)
0.3 × VDD(I2C-bus)
SDA
tv(Q)
Pn
unstable
data
last stable bit
A
P7
002aag982
b. Write mode (R/W = 0)
SCL
P0
0.7 × VDD(I2C-bus)
0.3 × VDD(I2C-bus)
tsu(D)
th(D)
Pn
0.5 × VDD(P)
002aag983
c. Read mode (R/W = 1)
CL includes probe and jig capacitance.
tv(Q) is measured from 0.7  VDD(I2C-bus) on SCL to 50 % I/O (Pn) output.
All inputs are supplied by generators having the following characteristics: PRR  10 MHz; Zo = 50 ; tr/tf  30 ns.
The outputs are measured one at a time, with one transition per measurement.
All parameters and waveforms are not applicable to all devices.
Fig 30. P port load circuit and voltage waveforms
PCA6416A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 January 2013
© NXP B.V. 2013. All rights reserved.
29 of 42
PCA6416A
NXP Semiconductors
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
VDD(I2C-bus)
RL = 1 kΩ
SDA
DUT
500 Ω
Pn
DUT
CL = 50 pF
2 × VDD(P)
CL = 50 pF
500 Ω
002aag977
002aag981
a. SDA load configuration
b. P port load configuration
START
SCL
ACK or read cycle
SDA
0.3 × VDD(I2C-bus)
trst
RESET
0.5 × VDD(I2C-bus)
trec(rst)
tw(rst)
trec(rst)
trst
Pn
0.5 × VDD(P)
002aag984
c. RESET timing
CL includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR  10 MHz; Zo = 50 ; tr/tf  30 ns.
The outputs are measured one at a time, with one transition per measurement.
I/Os are configured as inputs.
All parameters and waveforms are not applicable to all devices.
Fig 31. Reset load circuits and voltage waveforms
PCA6416A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 January 2013
© NXP B.V. 2013. All rights reserved.
30 of 42
PCA6416A
NXP Semiconductors
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
16. Package outline
HWQFN24: plastic thermal enhanced very very thin quad flat package; no leads;
24 terminals; body 4 x 4 x 0.75 mm
B
D
SOT994-1
A
terminal 1
index area
E
A
A1
c
detail X
e1
1/2 e
∅v
∅w
b
e
7
12
M
M
C
C A B
C
y1 C
y
L
13
6
e
e2
Eh
1/2 e
1
18
terminal 1
index area
24
19
X
Dh
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max
A1
b
c
D(1)
Dh
E (1)
Eh
e
e1
e2
L
v
w
y
y1
mm
0.8
0.05
0.00
0.30
0.18
0.2
4.1
3.9
2.25
1.95
4.1
3.9
2.25
1.95
0.5
2.5
2.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT994-1
---
MO-220
---
EUROPEAN
PROJECTION
ISSUE DATE
07-02-07
07-03-03
Fig 32. Package outline SOT994-1 (HWQFN24)
PCA6416A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 January 2013
© NXP B.V. 2013. All rights reserved.
31 of 42
PCA6416A
NXP Semiconductors
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
D
SOT355-1
E
A
X
c
HE
y
v M A
Z
13
24
Q
A2
(A 3)
A1
pin 1 index
A
θ
Lp
L
1
12
bp
e
detail X
w M
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
7.9
7.7
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.5
0.2
8o
0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT355-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-153
Fig 33. Package outline SOT355-1 (TSSOP24)
PCA6416A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 January 2013
© NXP B.V. 2013. All rights reserved.
32 of 42
PCA6416A
NXP Semiconductors
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
VFBGA24: plastic very thin fine-pitch ball grid array package;
24 balls; body 3 x 3 x 0.85 mm
B
D
SOT1199-1
A
ball A1
index area
A2
A
E
A1
detail X
e1
e
C
C A B
C
Øv
Øw
b
y
y1 C
E
e
D
e2
C
B
A
ball A1
index area
1
2
3
4
X
5
0
1
Dimensions
Unit
mm
2 mm
scale
A
A1
A2
b
max 1.00 0.25 0.75 0.35
nom 0.85 0.20 0.65 0.30
min 0.75 0.15 0.60 0.25
D
E
e
e1
e2
3.1
3.0
2.9
3.1
3.0
2.9
0.5
2
2
v
w
y
0.15 0.05 0.08
y1
0.1
sot1199-1_po
Outline
version
SOT1199-1
References
IEC
JEDEC
JEITA
European
projection
Issue date
11-02-16
12-03-13
---
Fig 34. Package outline SOT1199-1 (VFBGA24)
PCA6416A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 January 2013
© NXP B.V. 2013. All rights reserved.
33 of 42
PCA6416A
NXP Semiconductors
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
17. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
17.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
17.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
17.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
PCA6416A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 January 2013
© NXP B.V. 2013. All rights reserved.
34 of 42
PCA6416A
NXP Semiconductors
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
17.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 35) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 23 and 24
Table 23.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
 350
< 2.5
235
220
 2.5
220
220
Table 24.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 35.
PCA6416A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 January 2013
© NXP B.V. 2013. All rights reserved.
35 of 42
PCA6416A
NXP Semiconductors
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 35. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
PCA6416A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 January 2013
© NXP B.V. 2013. All rights reserved.
36 of 42
PCA6416A
NXP Semiconductors
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
18. Soldering: PCB footprints
Footprint information for reflow soldering of TSSOP24 package
SOT355-1
Hx
Gx
P2
(0.125)
Hy
Gy
(0.125)
By
Ay
C
D2 (4x)
D1
P1
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1
P2
Ay
By
C
D1
D2
Gx
Gy
Hx
Hy
0.650
0.750
7.200
4.500
1.350
0.400
0.600
8.200
5.300
8.600
7.450
sot355-1_fr
Fig 36. PCB footprint for SOT355-1 (TSSOP24); reflow soldering
PCA6416A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 January 2013
© NXP B.V. 2013. All rights reserved.
37 of 42
PCA6416A
NXP Semiconductors
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
Footprint information for reflow soldering of HVQFN24 package
SOT994-1
Hx
Gx
D
P
0.025
0.025
C
(0.105)
SPx
nSPx
Hy
SPy tot
SPy
Gy
SLy
nSPy
By
Ay
SPx tot
SLx
Bx
Ax
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
solder paste deposit
solder land plus solder paste
occupied area
nSPx
nSPy
2
2
Dimensions in mm
P
Ax
Ay
Bx
By
C
D
SLx
SLy
SPx tot
SPy tot
SPx
SPy
Gx
Gy
Hx
Hy
0.500
5.000
5.000
3.200
3.200
0.900
0.240
2.100
2.100
1.200
1.200
0.450
0.450
4.300
4.300
5.250
5.250
Issue date
07-09-24
09-06-15
sot994-1_fr
Fig 37. PCB footprint for SOT994-1 (HWQFN24); reflow soldering
PCA6416A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 January 2013
© NXP B.V. 2013. All rights reserved.
38 of 42
PCA6416A
NXP Semiconductors
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
19. Abbreviations
Table 25.
Abbreviations
Acronym
Description
ESD
ElectroStatic Discharge
FET
Field-Effect Transistor
GPIO
General Purpose Input/Output
I2C-bus
Inter-Integrated Circuit bus
I/O
Input/Output
LED
Light-Emitting Diode
LSB
Least Significant Bit
MSB
Most Significant Bit
NACK
Not ACKnowledge
PCB
Printed-Circuit Board
POR
Power-On Reset
PRR
Pulse Repetition Rate
SMBus
System Management Bus
20. Revision history
Table 26.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCA6416A v.2
20130110
Product data sheet
-
PCA6416A v.1
Modifications:
PCA6416A v.1
PCA6416A
Product data sheet
•
•
Updated Table 1 “Ordering information”: added “Topside marking” column
•
Figure 3 “Pin configuration for HWQFN24”: corrected type number from “PCA9416AHF”
to “PCA6416AHF”
Updated Table 2 “Ordering options”: added columns “Orderable part number”, “Packing method”
and “Minimum order quantity”; topside marking column is moved to Table 1
20120911
Product data sheet
-
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 January 2013
-
© NXP B.V. 2013. All rights reserved.
39 of 42
PCA6416A
NXP Semiconductors
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
21. Legal information
21.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
21.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
21.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PCA6416A
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 January 2013
© NXP B.V. 2013. All rights reserved.
40 of 42
PCA6416A
NXP Semiconductors
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
21.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
22. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PCA6416A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 January 2013
© NXP B.V. 2013. All rights reserved.
41 of 42
PCA6416A
NXP Semiconductors
Low-voltage translating 16-bit I2C-bus/SMBus I/O expander
23. Contents
1
2
3
3.1
4
5
5.1
5.2
6
7
7.1
7.2
7.3
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.5
7.6
7.7
7.8
8
8.1
8.2
9
9.1
9.2
10
11
12
13
13.1
14
15
16
17
17.1
17.2
17.3
17.4
18
19
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
Voltage translation . . . . . . . . . . . . . . . . . . . . . . . 6
Functional description . . . . . . . . . . . . . . . . . . . 6
Device address . . . . . . . . . . . . . . . . . . . . . . . . . 6
Interface definition . . . . . . . . . . . . . . . . . . . . . . 7
Pointer register and command byte . . . . . . . . . 7
Register descriptions . . . . . . . . . . . . . . . . . . . . 8
Input port registers (00h, 01h) . . . . . . . . . . . . . 8
Output port registers (02h, 03h) . . . . . . . . . . . . 8
Polarity inversion registers (04h, 05h) . . . . . . . 9
Configuration registers (06h, 07h) . . . . . . . . . . 9
I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 10
Reset input (RESET) . . . . . . . . . . . . . . . . . . . 11
Interrupt output (INT) . . . . . . . . . . . . . . . . . . . 11
Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 11
Write commands. . . . . . . . . . . . . . . . . . . . . . . 11
Read commands . . . . . . . . . . . . . . . . . . . . . . 13
Application design-in information . . . . . . . . . 16
Minimizing IDD when the I/Os are used
to control LEDs . . . . . . . . . . . . . . . . . . . . . . . . 16
Power-on reset requirements . . . . . . . . . . . . . 17
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 19
Recommended operating conditions. . . . . . . 19
Thermal characteristics . . . . . . . . . . . . . . . . . 20
Static characteristics. . . . . . . . . . . . . . . . . . . . 20
Typical characteristics . . . . . . . . . . . . . . . . . . 22
Dynamic characteristics . . . . . . . . . . . . . . . . . 26
Parameter measurement information . . . . . . 27
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 31
Soldering of SMD packages . . . . . . . . . . . . . . 34
Introduction to soldering . . . . . . . . . . . . . . . . . 34
Wave and reflow soldering . . . . . . . . . . . . . . . 34
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 34
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 35
Soldering: PCB footprints. . . . . . . . . . . . . . . . 37
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 39
20
21
21.1
21.2
21.3
21.4
22
23
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
40
40
40
40
41
41
42
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 10 January 2013
Document identifier: PCA6416A
Similar pages