Data Sheet

PCA9571
Remote 8-bit general purpose outputs for 1 MHz I2C-bus
Rev. 1 — 22 December 2014
Product data sheet
1. General description
The PCA9571 is a CMOS device that provide 8 bits of General Purpose parallel Output
(GPO) expansion in low voltage processor and handheld battery powered mobile
applications. They operate at 1 MHz I2C-bus speeds on a lightly loaded bus (<100 pF)
while maintaining backward compatibility to Fast-mode (400 kHz) and Standard-mode
(100 kHz).
The PCA9571 is a streamlined GPO that consists of 8-bit push-pull outputs that offer low
current consumption, small packaging options and a low operating voltage range of 1.1 V
to 3.6 V. The latched outputs are symmetrical 4 mA current drive capability at 3.3 V to
drive various control logic. The PCA9571 output expanders provide a simple solution
when additional outputs are needed while keeping interconnections and floor space to a
minimum, for example, in battery powered mobile applications where PCBs are crowded
for interfacing to sensors, push buttons, etc.
The PCA9571 contains an internal Power-On Reset (POR) and a Software Reset feature
that initializes the device to its default state.
2. Features and benefits
 1 MHz I2C-bus interface with 6 mA SDA sink capability for lightly loaded buses
(<100 pF) and improved power consumption
 Compliant with the I2C-bus Fast and Standard modes
 1.1 V to 3.6 V operation
 Latched outputs with a sink/source capability of 4 mA at 3.3 V
 Readable device ID (manufacturer, device type, and revision)
 Software Reset
 Power-On Reset
 Low standby current
 40 C to +85 C operation
 ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
 Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA
 Packages offered: XQFN12, TSSOP14 and DHVQFN14
3. Applications
 Smartphones and tablets
 Portable medical equipment
 Portable instrumentation and test measurement
PCA9571
NXP Semiconductors
Remote 8-bit general purpose outputs for 1 MHz I2C-bus
4. Ordering information
Table 1.
Ordering information
Type number
Topside
mark
Package
Name
Description
Version
PCA9571GU
71
XQFN12
plastic, extremely thin quad flat package; no leads;
12 terminals; body 1.70  2.00  0.50 mm
SOT1174-1
PCA9571BQ[1]
P9571
DHVQFN14
plastic dual in-line compatible thermal enhanced very thin
quad flat package; no leads; 14 terminals; body
2.5  3  0.85 mm
SOT762-1
TSSOP14
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
PCA9571PW[1] PCA9571
[1]
In development. Contact your NXP sales office for availability.
4.1 Ordering options
Table 2.
Ordering options
Type number
Orderable
part number
Package
Packing method
Minimum
order quantity
Temperature
PCA9571GU
PCA9571GUX
XQFN12
Reel 7” Q1/T1
*standard mark SMD
4000
Tamb = 40 C to +85 C
PCA9571BQ[1]
PCA9571BQX
DHVQFN14
Reel 7” Q1/T1
*standard mark SMD
3000
Tamb = 40 C to +85 C
PCA9571PW[1]
PCA9571PWJ
TSSOP14
Reel 13” Q1/T1
*standard mark SMD
2500
Tamb = 40 C to +85 C
[1]
In development. Contact your NXP sales office for availability.
5. Block diagram
PCA9571
SCL
SDA
INPUT
FILTER
I2C-BUS
CONTROL
SHIFT
REGISTER
8 bits
OUTPUT
PORT
P0 to P7
write pulse
read pulse
VDD
VSS
POWER-ON
RESET
002aag670
Fig 1.
PCA9571
Product data sheet
Block diagram of PCA9571
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
2 of 34
PCA9571
NXP Semiconductors
Remote 8-bit general purpose outputs for 1 MHz I2C-bus
VDD
IOH
write pulse
D
data from Shift Register
Q
FF
P0 to P7
IOL
CI
S
power-on reset
VSS
D
Q
FF
read pulse
CI
S
data to Shift Register
Fig 2.
002aag789
Simplified schematic of the I/Os (P0 to P7)
6. Pinning information
6.1 Pinning
8 P6
VSS 5
7 P5
P4 6
P3 4
14 VDD
2
P1
3
P2
4
11 P7
P3
5
10 P6
n.c.
6
9
002aag674
13 SDA
PCA9571BQ
8
9 P7
P0
P4
10 SCL
P2 3
12 SCL
P5
002aag942
Transparent top view
Transparent top view
Fig 3.
n.c.
1
11 SDA
7
P1 2
terminal 1
index area
VSS
P0 1
12 VDD
PCA9571GU
terminal 1
index area
Pin configuration for XQFN12
Fig 4.
Pin configuration for DHVQFN14
n.c.
1
14 VDD
P0
2
13 SDA
P1
3
P2
4
P3
5
10 P6
n.c.
6
9
P5
VSS
7
8
P4
12 SCL
PCA9571PW
11 P7
002aag830
Fig 5.
PCA9571
Product data sheet
Pin configuration for TSSOP14
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
3 of 34
PCA9571
NXP Semiconductors
Remote 8-bit general purpose outputs for 1 MHz I2C-bus
6.2 Pin description
Table 3.
Pin
Description
P0
1
output 0
P1
2
output 1
P2
3
output 2
P3
4
output 3
VSS
5
supply ground
P4
6
output 4
P5
7
output 5
P6
8
output 6
P7
9
output 7
SCL
10
serial clock line
SDA
11
serial data line
VDD
12
supply voltage
Table 4.
PCA9571
Product data sheet
Pin description for XQFN12
Symbol
Pin description for TSSOP14, DHVQFN14
Symbol
Pin
Description
n.c.
1
not connected
P0
2
output 0
P1
3
output 1
P2
4
output 2
P3
5
output 3
n.c.
6
not connected
VSS
7
supply ground
P4
8
output 4
P5
9
output 5
P6
10
output 6
P7
11
output 7
SCL
12
serial clock line
SDA
13
serial data line
VDD
14
supply voltage
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
4 of 34
PCA9571
NXP Semiconductors
Remote 8-bit general purpose outputs for 1 MHz I2C-bus
7. Functional description
Refer to Figure 1 “Block diagram of PCA9571”.
7.1 Device address
Following a START condition, the bus master must send the address of the slave it is
accessing and the operation it wants to perform (read or write). The address of the
PCA9571 is 4Ah as shown in Figure 6.
slave address
0
1
0
0
1
0
fixed
Fig 6.
1
R/W
aaa-015054
PCA9571 device address
7.2 Software Reset Call, and device ID addresses
Two other different addresses can be sent to the device.
• General Call address: allows to reset the device through the I2C-bus upon reception
of the right I2C-bus sequence. See Section 7.2.1 “Software Reset” for more
information.
• Device ID address: allows to read ID information from the device (manufacturer, part
identification, revision). See Section 7.2.2 “Device ID (PCA9571 ID field)” for more
information.
R/W
0
0
0
0
0
0
0
0
1
1
1
1
1
002aac115
Fig 7.
General Call address
0
0
R/W
002aac116
Fig 8.
Device ID address
7.2.1 Software Reset
The Software Reset Call allows all the devices in the I2C-bus to be reset to the power-up
state value through a specific formatted I2C-bus command. To be performed correctly, it
implies that the I2C-bus is functional and that there is no device hanging the bus.
The Software Reset sequence is defined as following:
1. A START command is sent by the I2C-bus master.
2. The reserved General Call I2C-bus address ‘0000 000’ with the R/W bit set to 0 (write)
is sent by the I2C-bus master.
3. The device acknowledges after seeing the General Call address ‘0000 0000’ (00h)
only. If the R/W bit is set to 1 (read), no acknowledge is returned to the I2C-bus
master.
PCA9571
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
5 of 34
PCA9571
NXP Semiconductors
Remote 8-bit general purpose outputs for 1 MHz I2C-bus
4. Once the General Call address has been sent and acknowledged, the master sends
1 byte. The value of the byte must be equal to 06h.
a. The device acknowledges this value only. If the byte is not equal to 06h, the device
does not acknowledge it.
If more than 1 byte of data is sent, the device does not acknowledge any more.
5. Once the right byte has been sent and correctly acknowledged, the master sends a
STOP command to end the Software Reset sequence: the device then resets to the
default value (power-up value) and is ready to be addressed again within the specified
bus free time. If the master sends a Repeated START instead, no reset is performed.
The I2C-bus master must interpret a non-acknowledge from the device (at any time) as a
‘Software Reset Abort’. The device does not initiate a reset of its registers.
The unique sequence that initiates a Software Reset is described in Figure 9.
SWRST Call I2C-bus address
S
0
0
0
0
0
START condition
0
0
SWRST data = 06h
0
A
0
0
R/W
acknowledge
from slave(s)
0
0
0
1
1
0
A
P
acknowledge
from slave(s)
PCA9571 is reset.
Registers are set to default power-up values.
002aah233
Fig 9.
PCA9571
Product data sheet
Software Reset sequence
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
6 of 34
PCA9571
NXP Semiconductors
Remote 8-bit general purpose outputs for 1 MHz I2C-bus
7.2.2 Device ID (PCA9571 ID field)
The Device ID field is a 3-byte read-only (24 bits) word giving the following information:
• 12 bits with the manufacturer name, unique per manufacturer (for example, NXP).
• 9 bits with the part identification, assigned by manufacturer, the 7 MSBs with the
category ID and the 6 LSBs with the feature ID (for example PCA9571 8-bit I/O
expander).
• 3 bits with the die revision, assigned by manufacturer (for example, Rev X).
The Device ID is read-only, hardwired in the device and can be accessed as follows:
1. START command
2. The master sends the Reserved Device ID I2C-bus address followed by the R/W bit
set to 0 (write): ‘1111 1000’.
3. The master sends the I2C-bus slave address of the slave device it needs to identify.
The LSB is a ‘Don’t care’ value. Only one device must acknowledge this byte (the one
that has the I2C-bus slave address).
4. The master sends a Re-START command.
Remark: A STOP command followed by a START command will reset the slave state
machine and the Device ID read cannot be performed. Also, a STOP command or a
Re-START command followed by an access to another slave device will reset the
slave state machine and the Device ID Read cannot be performed.
5. The master sends the Reserved Device ID I2C-bus address followed by the R/W bit
set to 1 (read): ‘1111 1001’.
6. The Device ID Read can be done, starting with the 12 manufacturer bits (first byte +
4 MSB of the second byte), followed by the 9 part identification bits (4 LSBs of the
second byte + 5 MSBs of the third byte), and then the 3 die revision bits (3 LSBs of
the third byte).
7. The master ends the reading sequence by NACKing the last byte, thus resetting the
slave device state machine and allowing the master to send the STOP command.
Remark: The reading of the Device ID can be stopped anytime by sending a NACK
command.
If the master continues to ACK the bytes after the third byte, the slave rolls back to the
first byte and keeps sending the Device ID sequence until a NACK has been
detected.
PCA9571 Device ID is shown in Figure 10.
manufacturer
0
0
part identification
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
revision
002aag792
Fig 10. PCA9571 Device ID field
PCA9571
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
7 of 34
PCA9571
NXP Semiconductors
Remote 8-bit general purpose outputs for 1 MHz I2C-bus
acknowledge from
one or several slaves
Device ID address
S 1
1
1
1
1
0
START condition
0
I2C-bus slave address
of the device to be identified
acknowledge from
slave to be identified
Device ID address
0 A A6 A5 A4 A3 A2 A1 A0 x A Sr 1
R/W
don’t care
acknowledge
from master
acknowledge from
slave to be identified
1
1
1
repeated START
condition
acknowledge
from master
1
0
0
1 A
R/W
no acknowledge
from master
M M M9 M8 M7 M6 M5 M4 A M3 M2 M1 M0 P8 P7 P6 P5 A P4 P3 P2 P1 P0 R2 R1 R0 A P
11 10
STOP condition
manufacturer name = 000000000000
part identification = 100000001
revision = 000
aaa-015053
If more than 3 bytes are read, the slave device loops back to the first byte (manufacturer byte) and keeps sending data until the
master generates a ‘no acknowledge’.
Fig 11. Device ID field reading
8. I/O programming
8.1 I/O architecture
The device’s ports (see Figure 2) are entirely independent and are output ports. The state
of the ports at the pin is transferred from the ports to the microcontroller in the Read mode
(see Figure 13). Output data is transmitted to the ports in the Write mode (see Figure 12).
At power-on all ports are HIGH. The state of the Output Port register determines if either
Q1 or Q2 is on, driving the line either HIGH or LOW. A bit set to 1 in the data byte will drive
the line HIGH at the corresponding port. A bit set to 0 in the data byte will drive the line
LOW at the corresponding port.
If an external voltage is applied to an output, care should be exercised because of the
low-impedance path that exists between the pin and either VDD or VSS.
8.2 Writing to the port (Output mode)
To write, the master (microcontroller) first addresses the slave device. By setting the last
bit of the byte containing the slave address to logic 0 the Write mode is entered. The
device acknowledges and the master sends the data byte for P7 to P0 and is
acknowledged by the device. The 8-bit data is presented on the port lines after it has been
acknowledged by the device. The number of data bytes that can be sent successively is
not limited. The previous data is overwritten every time a data byte has been sent.
PCA9571
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
8 of 34
PCA9571
NXP Semiconductors
Remote 8-bit general purpose outputs for 1 MHz I2C-bus
SCL
1
2
3
4
5
6
7
8
9
slave address
data 1
SDA S A6 A5 A4 A3 A2 A1 A0 0
START condition
data 2
A P7 P6 P5 P4 P3 1 P1 P0 A P7 P6 P5 P4 P3 0 P1 P0 A
P2
R/W
P2
acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
write to port
tv(Q)
data output from port
tv(Q)
DATA 1 VALID
DATA 2 VALID
P2 output voltage
002aag833
Fig 12. Write mode (output)
8.3 Reading from a port (Input mode)
All ports are outputs and cannot be used as inputs. When reading the device, the data
returned is the port state at the pin. To read, the master (microcontroller) first addresses
the slave device by setting the last bit of the byte containing the slave address to logic 1.
The data byte that follows on the SDA is the value of the ports pins. There is no limit to the
number of bytes read, and the state of the output port pins is updated at each
acknowledge cycle. Logic 1 means that the port is HIGH. Logic 0 means that the port is
LOW.
slave address
data from port
SDA S A6 A5 A4 A3 A2 A1 A0 1
START condition
R/W
DATA 1
A
acknowledge
from slave
data from port
A
acknowledge
from master
DATA 4
no acknowledge
from master
1
P
STOP
condition
read from
port
002aag846
Fig 13. Read input port register
8.4 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the device in a
reset condition until VDD has reached VPOR. At that point, the reset condition is released
and the device registers and I2C-bus/SMBus state machine will initialize to their default
states. See Section 13 for DC and AC characteristics of the POR function.
PCA9571
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
9 of 34
PCA9571
NXP Semiconductors
Remote 8-bit general purpose outputs for 1 MHz I2C-bus
9. Application design-in information
9.1 I/O expander applications
Figure 14 shows an 8-bit output expander application. The desired HIGH or LOW logic
levels are controlled by the master with speeds of up to 1 MHz on a lightly loaded bus
(<100 pF). This allows the host processor to control various functions quickly and with
very low overhead. The port read function of the device enables the host processor to poll
the status of the output port pins. This is useful for system recovery operations or
debugging.
1.8 V
CORE
PROCESSOR
1.8 V
SDA
SCL
P0
P1
P2
P3
P4
P5
P6
P7
GPS enable
vibrator control
latch control
switch control
audio control
camera control
MP3 control
FM control
002aag680
Fig 14. I/O expander application
PCA9571
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
10 of 34
PCA9571
NXP Semiconductors
Remote 8-bit general purpose outputs for 1 MHz I2C-bus
10. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD
supply voltage
Conditions
Min
Max
Unit
0.5
+4
V
VI
input voltage
SCL; SDA
0.5
+4
V
IIK
input clamping current
SCL; VI < 0 V
-
18
mA
IOK
output clamping current
P port; VO < 0 V or VO > VDD
-
18
mA
SDA; VO < 0 V or VO > VDD
-
18
mA
[1]
IO
output current
continuous; P port
-
25
mA
IOL
LOW-level output current
continuous; SDA; VO = 0 V to VDD
-
25
mA
IDD
supply current
continuous through VSS
-
100
mA
Tstg
storage temperature
65
+150
C
Tj
junction temperature
-
125
C
[1]
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
PCA9571
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
11 of 34
PCA9571
NXP Semiconductors
Remote 8-bit general purpose outputs for 1 MHz I2C-bus
11. Static characteristics
Table 6.
Static characteristics
Tamb = 40 C to +85 C; VDD = 1.1 V to 3.6 V; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1] Max
Unit
VIK
input clamping voltage
II = 18 mA
1.2
-
V
-
VDD
supply voltage
1.1
-
3.6
V
VPOR
power-on reset voltage
VI = VDD or VSS; IO = 0 mA
-
0.7
1.0
V
VOL
LOW-level output voltage
P port; IOL = 2 mA; VDD = 1.65 V
-
-
0.25
V
P port; IOL = 3 mA; VDD = 2.3 V
-
-
0.25
V
P port; IOL = 4 mA; VDD = 3 V
-
-
0.25
V
P port; IOL = 2 mA; VDD = 1.65 V
1.35
-
-
V
P port; IOL = 3 mA; VDD = 2.3 V
2.0
-
-
V
P port; IOL = 4 mA; VDD = 3 V
2.7
-
-
V
VOH
HIGH-level output voltage
LOW-level output current
IOL
HIGH-level input voltage
VIH
LOW-level input voltage
VIL
SDA; VOL = 0.4 V; VDD = 2.1 V to 3.6 V
3
-
-
mA
SDA; VOL = 0.2  VDD; VDD = 1.1 V to 2.0 V
1
-
-
mA
SCL, SDA; VDD = 1.1 V to 1.2 V
0.8  VDD -
1.2
V
SCL, SDA; VDD = 1.2 V to 3.6 V
0.7  VDD -
3.6
V
SCL, SDA; VDD = 1.1 V to 1.2 V
0.5
-
0.2  VDD V
SCL, SDA; VDD = 1.2 V to 3.6 V
0.5
-
0.3  VDD V
-
-
1
A
VDD = 2.3 V to 3.6 V
-
6.5
15
A
VDD = 1.1 V to 2.3 V
-
4
9
A
VDD = 2.3 V to 3.6 V
-
1
3.2
A
VDD = 1.1 V to 2.3 V
-
0.6
1.7
A
-
50
75
A
II
input current
SCL, SDA; VDD = 1.1 V to 3.6 V;
VI = VDD or VSS
IDD
supply current
SDA, P port; VI on SDA = VDD or VSS;
IO = 0 mA; fSCL = 400 kHz
SCL, SDA, P port;
VI on SCL, SDA = VDD or VSS;
IO = 0 mA; fSCL = 0 kHz
Active mode: SCL, SDA, P port; IO = 0 mA;
fSCL = 400 kHz; continuous register read
VDD = 1.1 V to 3.6 V
Ci
input capacitance
VI = VDD or VSS
-
6
7
pF
Co
output capacitance
VO = VDD or VSS
-
3
5
pF
Tamb
ambient temperature
operating in free air
40
-
+85
C
[1]
The typical values are at VDD = 2.2 V and Tamb = 25 C.
PCA9571
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
12 of 34
PCA9571
NXP Semiconductors
Remote 8-bit general purpose outputs for 1 MHz I2C-bus
11.1 Typical characteristics
aaa-011393
12
IDD
(μA)
IDD(stb)
(nA)
VDD = 3.6 V
3.3 V
2.5 V
1.8 V
1.1 V
8
aaa-011394
120
VDD = 3.6 V
3.3 V
2.5 V
1.8 V
1.1 V
80
4
40
0
−40
−15
10
35
0
−40
60
85
Tamb (°C)
Fig 15. Supply current versus ambient temperature
−15
10
35
60
85
Tamb (°C)
Fig 16. Standby supply current versus
ambient temperature
aaa-011395
10
IDD
(μA)
8
6
4
2
1
1.1
1.8
2.5
3.3
3.6
VDD (V)
Tamb = 25 C
Fig 17. Supply current versus supply voltage
PCA9571
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
13 of 34
PCA9571
NXP Semiconductors
Remote 8-bit general purpose outputs for 1 MHz I2C-bus
aaa-011487
8
Isink
(mA)
Tamb = −40 °C
25 °C
85 °C
Isink
(mA)
6
aaa-011488
18
Tamb = −40 °C
25 °C
85 °C
12
4
6
2
0
0
0
0.2
0.4
0.6
0
0.2
0.4
VOL (V)
a. VDD = 1.2 V
b. VDD = 1.8 V
aaa-011489
30
Isink
(mA)
Tamb = −40 °C
25 °C
85 °C
Isink
(mA)
0.6
VOL (V)
aaa-011490
36
20
24
10
12
Tamb = -40 °C
25 °C
85 °C
0
0
0
0.2
0.4
0.6
0
VOL (V)
0.2
0.4
0.6
VOL (V)
c. VDD = 2.5 V
d. VDD = 3.3 V
Fig 18. I/O sink current versus LOW-level output voltage
PCA9571
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
14 of 34
PCA9571
NXP Semiconductors
Remote 8-bit general purpose outputs for 1 MHz I2C-bus
aaa-011563
6
Isource
(mA)
Tamb = −40 °C
25 °C
85 °C
4
aaa-011564
14
Isource
(mA)
12
Tamb = −40 °C
25 °C
85 °C
10
8
6
2
4
2
0
0
0
0.2
0.4
0.6
VDD − VOH (V)
0
a. VDD = 1.2 V
aaa-011566
36
Isource
(mA)
Tamb = −40 °C
25 °C
85 °C
15
0.4
0.6
VDD − VOH (V)
b. VDD = 1.8 V
aaa-011565
25
Isource
(mA)
20
0.2
Tamb = −40 °C
25 °C
85 °C
24
10
12
5
0
0
0
0.2
0.4
0.6
VDD − VOH (V)
0
c. VDD = 2.5 V
0.2
0.4
0.6
VDD − VOH (V)
d. VDD = 3.3 V
Fig 19. I/O source current versus HIGH-level output voltage
aaa-011567
60
VOL
(mV)
(1)
40
20
(2)
0
−40
−15
10
35
60
85
Tamb (°C)
(1) VDD = 1.8 V; Isink = 2 mA
(2) VDD = 1.8 V; Isink = 100 A
Fig 20. LOW-level output voltage versus temperature
PCA9571
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
15 of 34
PCA9571
NXP Semiconductors
Remote 8-bit general purpose outputs for 1 MHz I2C-bus
12. Dynamic characteristics
Table 7.
Dynamic characteristics
VDD = 1.1 V to 3.6 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol Parameter
Conditions
Standard mode
I2C-bus
Fast mode
I2C-bus
1 MHz
I2C-bus[1]
Unit
Min
Max
Min
Max
Min
0
100
0
400
0
bus free time between a
STOP and START
condition
4.7
-
1.3
-
0.5
-
s
tHD;STA
hold time (repeated)
START condition
4.0
-
0.6
-
0.26
-
s
tSU;STA
set-up time for a repeated
START condition
4.7
-
0.6
-
0.26
-
s
tSU;STO
set-up time for STOP
condition
4.0
-
0.6
-
0.26
-
s
tHD;DAT
data hold time
fSCL
SCL clock frequency
tBUF
Max
1000 kHz
0
-
0
-
0
-
ns
-
3.45
-
0.9
-
0.45
s
-
3.45
-
0.9
-
0.45
s
tVD;ACK
data valid acknowledge
time
[2]
tVD;DAT
data valid time
[3]
tSU;DAT
data set-up time
250
-
100
-
50
-
ns
tLOW
LOW period of the SCL
clock
4.7
-
1.3
-
0.5
-
s
tHIGH
HIGH period of the SCL
clock
4.0
-
0.6
-
0.26
-
s
tf
fall time of both SDA and
SCL signals
-
300
20 
(VDD / 5.5 V)
300
20 
(VDD / 5.5 V)
120
ns
tr
rise time of both SDA and
SCL signals
-
1000
20
300
-
120
ns
tSP
pulse width of spikes that
must be suppressed by the
input filter
-
50
-
50
-
50
ns
-
200
-
200
-
200
ns
[4]
Port timing
tv(Q)
data output valid time
[1]
Fm+ mode on a non-standard, lightly loaded bus (<100 pF).
[2]
tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
[3]
tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.
[4]
Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
PCA9571
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
16 of 34
PCA9571
NXP Semiconductors
Remote 8-bit general purpose outputs for 1 MHz I2C-bus
13. Power-on reset requirements
In the event of a glitch or data corruption, the device can be reset to its default conditions
by using the power-on reset feature. Power-on reset requires that the device go through a
power cycle to be completely reset. This reset also happens when the device is
powered on for the first time in an application.
VDD
ramp-up
ramp-down
re-ramp-up
td(rst)
time
(dV/dt)r
(dV/dt)f
(dV/dt)r
time to re-ramp
when VDD drops to VSS
002aah307
Fig 21. VDD is lowered below 0.6 V and then ramped up to VDD
Table 8.
Recommended supply sequencing and ramp rates
Tamb = 25 C (unless otherwise noted). Not tested; specified by design.
Symbol
Parameter
Condition
Min
Typ
Max
Unit
(dV/dt)f
fall rate of change of voltage
Figure 21
0.1
-
2000
ms
(dV/dt)r
rise rate of change of voltage
Figure 21
0.1
-
2000
ms
td(rst)
reset delay time
Figure 21; when VDD drops to VSS
1
-
-
s
-
-
1.2
V
VDD(gl)
glitch supply voltage difference
[1]
Figure 22
VDD = 2.1 V to 3.6 V
VDD = 1.1 V to 2.1 V
tw(gl)VDD
supply voltage glitch pulse width
Figure 22
VPOR(trip)
power-on reset trip voltage
rising VDD
[2]
-
-
VDD  0.9
V
-
-
10
s
-
0.7
1.0
V
[1]
Level that VDD can glitch down to with a ramp rate of 0.4 s/V, but not cause a functional disruption when tw(gl)VDD = 1 s.
[2]
Glitch width that will not cause a functional disruption when VDD = 1.8 V to 3.6 V, VDD(gl) = 0.5  VDD;
VDD = 1.1 V to 1.8 V, VDD(gl) = VDD  0.9 V.
Glitches in the power supply can also affect the power-on reset performance of this
device. The glitch width (tw(gl)VDD) and glitch height (VDD(gl)) are dependent on each
other. The bypass capacitance, source impedance, and device impedance are factors that
affect power-on reset performance. Figure 22 and Table 8 provide more information on
how to measure these specifications.
VDD
∆VDD(gl)
tw(gl)VDD
time
002aah309
Fig 22. Glitch width and glitch height
PCA9571
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
17 of 34
PCA9571
NXP Semiconductors
Remote 8-bit general purpose outputs for 1 MHz I2C-bus
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition
is released and all the registers and the I2C-bus/SMBus state machine are initialized to
their default states. Figure 23 and Table 8 provide more details on this specification.
VDD
VPOR (rising VDD)
time
POR
time
002aah096
Fig 23. Power-on reset voltage (VPOR)
PCA9571
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
18 of 34
PCA9571
NXP Semiconductors
Remote 8-bit general purpose outputs for 1 MHz I2C-bus
14. Parameter measurement information
VDD
RL = 1 kΩ
DUT
SDA
CL = 50 pF
002aag803
a. SDA load configuration
two bytes for read Input port register(1)
STOP
START
condition condition
(P)
(S)
Address
Bit 7
(MSB)
Address
Bit 1
R/W
Bit 0
(LSB)
Data
Bit 7
(MSB)
ACK
(A)
Data
Bit 0
(LSB)
STOP
condition
(P)
002aag952
b. Transaction format
tHIGH
tLOW
tSP
0.7 × VDD
0.3 × VDD
SCL
tBUF
tVD;DAT
tr
tf
tf(o)
tVD;ACK
tSU;STA
0.7 × VDD
SDA
tf
tHD;STA
tr
0.3 × VDD
tVD;ACK
tSU;DAT
tSU;STO
tHD;DAT
repeat START condition
STOP condition
002aag804
c. Voltage waveforms
CL includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR  10 MHz; Zo = 50 ; tr/tf  30 ns.
All parameters and waveforms are not applicable to all devices.
Byte 1 = I2C-bus address; Byte 2, byte 3 = P port data.
(1) See Figure 13.
Fig 24. I2C-bus interface load circuit and voltage waveforms
PCA9571
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
19 of 34
PCA9571
NXP Semiconductors
Remote 8-bit general purpose outputs for 1 MHz I2C-bus
500 Ω
Pn
DUT
2 × VDD
CL = 50 pF
500 Ω
002aag805
a. P port load configuration
SCL
P0
A
P7
0.7 × VDD
0.3 × VDD
SDA
tv(Q)
Pn
unstable
data
last stable bit
A
P7
002aag806
b. Write mode (R/W = 0)
SCL
P0
0.7 × VDD
0.3 × VDD
tsu(D)
th(D)
Pn
002aag807
c. Read mode (R/W = 1)
CL includes probe and jig capacitance.
tv(Q) is measured from 0.7  VDD on SCL to 50 % I/O (Pn) output.
All inputs are supplied by generators having the following characteristics: PRR  10 MHz; Zo = 50 ; tr/tf  30 ns.
The outputs are measured one at a time, with one transition per measurement.
All parameters and waveforms are not applicable to all devices.
Fig 25. P port load circuit and voltage waveforms
PCA9571
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
20 of 34
PCA9571
NXP Semiconductors
Remote 8-bit general purpose outputs for 1 MHz I2C-bus
15. Package outline
XQFN12: plastic, extremely thin quad flat package; no leads;
12 terminals; body 1.70 x 2.00 x 0.50 mm
SOT1174-1
X
A
B
D
terminal 1
index area
A
E
A1
A3
detail X
∅v
∅w
b
5
C
C A B
C
y1 C
y
7
e1
e
1
11
terminal 1
index area
L1
L
0
1
2 mm
scale
Dimensions
Unit(1)
mm
max
nom
min
A
A1
0.5
0.05
A3
b
0.25
0.127 0.20
0.15
0.00
D
E
1.8
1.7
1.6
2.1
2.0
1.9
e
e1
0.4
1.6
L
L1
0.55
0.50 0.15
0.45
v
0.1
w
y
y1
0.05 0.05 0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
References
Outline
version
IEC
JEDEC
JEITA
SOT1174-1
---
MO-288
---
sot1174-1_po
European
projection
Issue date
10-04-07
10-04-21
Fig 26. Package outline SOT1174-1 (XQFN12)
PCA9571
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
21 of 34
PCA9571
NXP Semiconductors
Remote 8-bit general purpose outputs for 1 MHz I2C-bus
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
SOT762-1
14 terminals; body 2.5 x 3 x 0.85 mm
A
B
D
A
A1
E
c
detail X
terminal 1
index area
terminal 1
index area
C
e1
e
2
6
y
y1 C
v M C A B
w M C
b
L
1
7
Eh
e
14
8
13
9
Dh
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
c
D (1)
Dh
E (1)
Eh
e
e1
L
v
w
y
y1
mm
1
0.05
0.00
0.30
0.18
0.2
3.1
2.9
1.65
1.35
2.6
2.4
1.15
0.85
0.5
2
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT762-1
---
MO-241
---
EUROPEAN
PROJECTION
ISSUE DATE
02-10-17
03-01-27
Fig 27. Package outline SOT762-1 (DHVQFN14)
PCA9571
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
22 of 34
PCA9571
NXP Semiconductors
Remote 8-bit general purpose outputs for 1 MHz I2C-bus
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
E
D
A
X
c
y
HE
v M A
Z
8
14
Q
(A 3)
A2
A
A1
pin 1 index
θ
Lp
L
1
7
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.72
0.38
8o
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT402-1
REFERENCES
IEC
JEDEC
JEITA
MO-153
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
Fig 28. Package outline SOT402-1 (TSSOP14)
PCA9571
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
23 of 34
PCA9571
NXP Semiconductors
Remote 8-bit general purpose outputs for 1 MHz I2C-bus
16. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling ensure that the appropriate precautions are taken as
described in JESD625-A or equivalent standards.
17. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
17.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
17.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
17.3 Wave soldering
Key characteristics in wave soldering are:
PCA9571
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
24 of 34
PCA9571
NXP Semiconductors
Remote 8-bit general purpose outputs for 1 MHz I2C-bus
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
17.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 29) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 9 and 10
Table 9.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
 350
< 2.5
235
220
 2.5
220
220
Table 10.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 29.
PCA9571
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
25 of 34
PCA9571
NXP Semiconductors
Remote 8-bit general purpose outputs for 1 MHz I2C-bus
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 29. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
PCA9571
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
26 of 34
PCA9571
NXP Semiconductors
Remote 8-bit general purpose outputs for 1 MHz I2C-bus
18. Soldering: PCB footprints
Footprint information for reflow soldering of XQFN12 package
SOT1174-1
2.25
2
0.45
0.22
CU
(11×)
0.32
CU
(1×)
0.45
(1×)
2.55
1
CU
2.05
2.3
CU
0.4
(7×)
1
CU
placement area
solder land plus solder paste
solder land
solder resist, 0.0625 around copper
solder paste deposit, −0.025 around copper,
stencil thickness 0.1
occupied area
clearance, 0.125 around occupied area
Dimensions in mm
sot1174-1_fr
Fig 30. PCB footprint for SOT1174-1 (XQFN12); reflow soldering
PCA9571
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
27 of 34
PCA9571
NXP Semiconductors
Remote 8-bit general purpose outputs for 1 MHz I2C-bus
Footprint information for reflow soldering of DHVQFN14 package
SOT762-1
4.250
3.300
0.240
0.500
0.025
0.025
0.105
3.750
2.800
0.400
0.900
1.700
3.500
0.600
1.400
2.200
4.000
Refer to the package outline drawing for actual layout
solder land
solder paste deposit
solder land plus solder paste
occupied area
sot762-1_fr
Fig 31. PCB footprint for SOT762-1 (DHVQFN14); reflow soldering
PCA9571
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
28 of 34
PCA9571
NXP Semiconductors
Remote 8-bit general purpose outputs for 1 MHz I2C-bus
Footprint information for reflow soldering of TSSOP14 package
SOT402-1
Hx
Gx
P2
(0.125)
(0.125)
Hy
By
Gy
Ay
C
D2 (4x)
D1
P1
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1
P2
Ay
By
C
D1
D2
Gx
Gy
Hx
Hy
0.650
0.750
7.200
4.500
1.350
0.400
0.600
4.950
5.300
5.800
7.450
sot402-1_fr
Fig 32. PCB footprint for SOT402-1 (TSSOP14); reflow soldering
PCA9571
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
29 of 34
PCA9571
NXP Semiconductors
Remote 8-bit general purpose outputs for 1 MHz I2C-bus
19. Abbreviations
Table 11.
PCA9571
Product data sheet
Abbreviations
Acronym
Description
CDM
Charged-Device Model
ESD
ElectroStatic Discharge
FM
Frequency Modulation
GPIO
General Purpose Input/Output
GPS
Global Positioning Satellite
HBM
Human Body Model
I2C-bus
Inter-Integrated Circuit bus
I/O
Input/Output
IC
Integrated Circuit
ID
Identification
LED
Light Emitting Diode
LSB
Least Significant Bit
MP3
MPEG audio layer 3
MSB
Most Significant Bit
SMBus
System Management Bus
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
30 of 34
PCA9571
NXP Semiconductors
Remote 8-bit general purpose outputs for 1 MHz I2C-bus
20. Revision history
Table 12.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCA9571 v.1
20141222
Product data sheet
-
-
PCA9571
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
31 of 34
PCA9571
NXP Semiconductors
Remote 8-bit general purpose outputs for 1 MHz I2C-bus
21. Legal information
21.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
21.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
21.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PCA9571
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
32 of 34
PCA9571
NXP Semiconductors
Remote 8-bit general purpose outputs for 1 MHz I2C-bus
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
21.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP Semiconductors N.V.
22. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PCA9571
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
33 of 34
PCA9571
NXP Semiconductors
Remote 8-bit general purpose outputs for 1 MHz I2C-bus
23. Contents
1
2
3
4
4.1
5
6
6.1
6.2
7
7.1
7.2
7.2.1
7.2.2
8
8.1
8.2
8.3
8.4
9
9.1
10
11
11.1
12
13
14
15
16
17
17.1
17.2
17.3
17.4
18
19
20
21
21.1
21.2
21.3
21.4
22
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Device address . . . . . . . . . . . . . . . . . . . . . . . . . 5
Software Reset Call, and device ID addresses 5
Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . 5
Device ID (PCA9571 ID field) . . . . . . . . . . . . . . 7
I/O programming . . . . . . . . . . . . . . . . . . . . . . . . 8
I/O architecture . . . . . . . . . . . . . . . . . . . . . . . . . 8
Writing to the port (Output mode) . . . . . . . . . . . 8
Reading from a port (Input mode) . . . . . . . . . . 9
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 9
Application design-in information . . . . . . . . . 10
I/O expander applications . . . . . . . . . . . . . . . . 10
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 11
Static characteristics. . . . . . . . . . . . . . . . . . . . 12
Typical characteristics . . . . . . . . . . . . . . . . . . 13
Dynamic characteristics . . . . . . . . . . . . . . . . . 16
Power-on reset requirements . . . . . . . . . . . . . 17
Parameter measurement information . . . . . . 19
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 21
Handling information. . . . . . . . . . . . . . . . . . . . 24
Soldering of SMD packages . . . . . . . . . . . . . . 24
Introduction to soldering . . . . . . . . . . . . . . . . . 24
Wave and reflow soldering . . . . . . . . . . . . . . . 24
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 24
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 25
Soldering: PCB footprints. . . . . . . . . . . . . . . . 27
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 31
Legal information. . . . . . . . . . . . . . . . . . . . . . . 32
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 32
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Contact information. . . . . . . . . . . . . . . . . . . . . 33
23
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 22 December 2014
Document identifier: PCA9571
Similar pages