AN439 Application note Snubberless™ and logic level TRIAC behavior at turn-off Introduction The use of TRIACs is limited by their switching behavior. Indeed, there is a risk of spurious triggering after conduction if the slope of the decreasing current is too high, and/or if the slope of the reapplied voltage is too high. The designer must then take some precautions: device over-rating, switching aid network (snubber), and junction temperature margin, and so on. This generally involves additional costs. After a brief discussion of commutation when a TRIAC is turned off, this article will describe the behavior of the logic level and Snubberless TRIACs, which present high commutation capabilities. Contents 1 TRIAC turn-off description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.1 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2 (dI/dt)c versus (dV/dt)c characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 Application requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 2 1.3.1 TRIAC with resistive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3.2 TRIAC with inductive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 TRIAC without snubber network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Logic level and Snubberless TRIACs . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Operation in Q1-Q2-Q3 quadrants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Performances and specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 2.2.1 Logic level TRIACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2.2 Snubberless TRIACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3.1 Logic level TRIACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3.2 Snubberless TRIACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 March 2008 Rev 3 1/16 www.st.com TRIAC turn-off description AN439 1 TRIAC turn-off description 1.1 Definition The TRIAC can be compared to two thyristors mounted in back-to-back and coupled with a control area which allows the triggering of this Alternating Current Switch with only one gate (see Figure 1). Looking at the TRIAC silicon structure (see Figure 2), it can be noted that the conduction areas, corresponding to these two thyristors, narrowly overlap each other on the control area. Figure 1. Simplified equivalent schematic of TRIAC circuit Example of TRIAC silicon structure Figure 2. A1 A2 G I- G I+ VT N1 P1 P1 Gates Ctrl. N2 I- A1 N4 Gates Ctrl P2 P2 I+ N2 N3 A2 During the conduction time, a certain quantity of charge is injected into the structure. The biggest part of this charge disappears by recombination during the current decrease, while another part is extracted after the turn-off by the reverse recovery current. Nonetheless, an excess charge remains, particularly in the neighboring regions of the gate, which can induce the triggering of the other conduction area when the mains voltage is reapplied across the TRIAC. This is the problem of commutation. For a given structure at a determined junction temperature, the turn-off behavior depends on: 2/16 1. The quantity of charge which remains when the current drops to zero. The quantity of the charge is linked to the value of the current which was circulating in the TRIAC approximately 100 µs, about two or three times the minority carriers’ life time, before the turn-off. Thus, the parameter to consider is the slope of the decreasing current, called the turn-off dI/dt or dI/dtOFF. (see Figure 3) 2. The slope of the reapplied voltage during turn-off. This parameter is the commutation dV/dt, called the turn-off dV/dt or dV/dtOFF (see Figure 3). A capacitive current, proportional to the dV/dtOFF, flows into the structure, and therefore charges are injected and added to those coming from the previous conduction. AN439 TRIAC turn-off description Figure 3. dI/dt and dV/dt at turn-off IT VMains OUT dI/dtOFF IT t IG VT VT dV/dtOFF t G COM IG t 1.2 (dI/dt)c versus (dV/dt)c characterization To characterize the turn-off TRIAC behavior, we consider a circuit in which the slope of the decreasing current can be adjusted. In addition, the slope of the reapplied voltage can be controlled by using, a circuit of resistors and capacitors connected across the TRIAC. For a determined dV/dtOFF ((dV/dt)c), we progressively increase the dI/dtOFF until a certain level which induces the spontaneous triggering of the TRIAC. This is the critical dI/dtOFF, called the (dI/dt)c in TRIAC datasheets. This is also the way to trace the curve of the TRIAC commutation behavior (see TRIAC datasheet curve “Relative variation of critical rate of decrease of main current (dI/dt)c versus reapplied (dV/dt)c”). In TRIAC datasheets, the commutation behavior is specified in different way according to the TRIAC technologies. For standard TRIAC, a minimum (dV/dt)c is specified for a given (dI/dt)c. For logic level TRIACs, a minimum (dI/dt)c is specified for two given (dV/dt)c (0.1 V/µs and 10 V/µs). For Snubberless TRIACs, a minimum (dI/dt)c is specified without (dV/dt)c limitation. Figure 4 represents the curve of the commutation behavior obtained with a standard 4 A TRIAC. This TRIAC is available with different sensitivities: ● Z0402: IGT = 3 mA; ● Z0405: IGT = 5 mA; ● Z0409: IGT = 10 mA; ● Z0410: IGT = 25 mA. For lower sensitive gate TRIACs (Z0409 and Z0410), the (dI/dt)c is slightly modified according to the (dV/dt)c. For sensitive gate TRIACs (Z0402 and Z0405), this parameter noticeably decreases when the slope of the reapplied voltage increases. 3/16 TRIAC turn-off description Figure 4. AN439 Relative variation of (dI/dt)c versus (dV/dt)c for a 4 A standard TRIAC (typical values) Area of spurious firing at commutation Safe area In practice, the current waveform, and thus the dI/dtOFF, is imposed by the load. Generally we cannot change it. So, in TRIAC applications, it is always necessary to know the dI/dtOFF of the load to choose a TRIAC with a suitable (dI/dt)c. This is the most important parameter. Suppose a circuit in which the dI/dtOFF reaches 2 times the specified (dI/dt)c. The standard 4 A TRIACs, characterized by the curves in Figure 4, will be not suitable even if the dV/dtOFF is equal to 0.1 V/µs. 1.3 Application requirements 1.3.1 TRIAC with resistive load In this case, the TRIAC current and the mains voltage are in phase (see Figure 5). When the TRIAC switches off (i.e. when the current drops to zero), the mains voltage is equal to zero at this instant and will increase across the TRIAC according to the sinusoidal law: Equation 1 VMains = VMax · sin( ω·t ) For the European mains, i.e. VRMS = 220 V at 50 Hz, the slope will be: Equation 2 dV / dt OFF ( V / µ s ) = VRMS ( V ) · 2 ·2 π·f( Hz ) ·10 - 6 ≈ 0.1 V / µ s For 110 V, 60 Hz mains, the slope will be: dV/dtOFF ≈ 0.06 V/µs. These relatively low dV/dtOFF correspond to the left points on the curves in Figure 4. The dI/dtOFF only depends on the load rms current and the mains frequency. For resistive loads, as for most other loads, we will have: Equation 3 dI / dt OFF ( A / ms ) = IRMS ( A ) · 2 ·2 π·f( Hz ) ·10 -3 ≈ 0.5 ·IRMS ( A ) 4/16 AN439 TRIAC turn-off description Figure 5. Current and voltage waveforms for resistive loads (phase control) IG t IT dI/dtOFF t VMains VT dV/dtOFF 1.3.2 t TRIAC with inductive load An inductive load induces a phase lag between the TRIAC current and the mains voltage (see Figure 6). When the current drops to zero, the TRIAC turns off and the voltage is abruptly applied across its terminals. To limit the speed of the reapplied voltage, a resistive / capacitive network mounted in parallel with the TRIAC is generally used (see Figure 13). This “snubber” is calculated to limit the dV/dtOFF at a value for which the dI/dtOFF is lower than the (dI/dt)c specified in the datasheet. The dI/dtOFF is also determined in this case by the load impedance (Z) and the mains rms voltage. (see. AN437 for RC snubber circuit design) Figure 6. Current and voltage waveforms for inductive loads (phase control) IG t IT dI/dtOFF t VMains VT t dV/dtOFF 5/16 TRIAC turn-off description 1.4 AN439 TRIAC without snubber network Without snubber circuit, the dV/dtOFF is limited by the capacitance between anode cathode junction of the TRIAC. When the current drops to zero, the TRIAC is considered as a switch which turns off. The dampened oscillating circuit is constituted by the loads, L and R, and the internal capacitance, CT, of the TRIAC (see Figure 7). The final value E depends on the peak mains voltage and the phase difference (φ) between voltage and current. Figure 7. TRIAC commutation on an inductive load without a snubber network Load L Load R L VT(t) IT R E IT VMains G IG VT ≈E CT VT dV/dtOFF t For a second order linear differential equation with a step function input, the voltage variation across the TRIAC (VT(t)) is given by: Equation 4 2 1 ω0 2 · d VT ( t ) dt 2 + 2 .ξ dV T ( t ) · + VT ( t ) = E ω0 dt With damping factor: Equation 5 ξ= R (Ω ) 2 · C T (F ) L (H ) Undamped natural resonance: Equation 6 ω 0 ( rad / s) 1 = L ( H ) ·C T ( F ) Final voltage value: Equation 7 E = VRMS · 2 · sin( φ ) For example, the typical internal capacitances of 1 A, 12 A and 24 A TRIACs are respectively 12 pF, 90 pF and 180 pF (without direct voltage junction polarisation, worst case). Without snubber, and for most part of inductive loads, the damping factor (ξ) is generally lower than 1. 6/16 AN439 TRIAC turn-off description For an underdamped oscillating circuit (0 ≤ ξ ≤ 1), the voltage variation (VT(t)) across the TRIAC is defined by: Equation 8 ⎞ - ξ·ω ·t ⎛ ξ·ω 0 VT ( t ) = E - E·⎜ cos( ωp ·t ) + · sin( ωp ·t ) ⎟ ·e 0 ⎟ ⎜ ωp ⎠ ⎝ With damped natural resonance: Equation 9 ωp = ω0 · 1 - ξ 2 In the case of pure inductive load (R = 0, worst case), the circuit is undamped. The maximum reapplied dV/dtOFF across the TRIAC is: Equation 10 dV / dt OFF ( V / µ s ) = VRMS (V ). 2 L ( H ) .C T ( F ) .10 -6 at t = π 2 .ω 0 Without snubber, according to the characteristics of inductive loads, the maximum dV/dtOFF without snubber will be limited to about 60 V/µs for 100 – 220 V applications. Thus, it is not necessary to get the (dI/dt)c values for (dV/dt)c above 100 V/µs . 7/16 Logic level and Snubberless TRIACs AN439 2 Logic level and Snubberless TRIACs 2.1 Operation in Q1-Q2-Q3 quadrants To make significant progress in the TRIAC technology is to essentially improve the turn-off behaviour. In other words, the critical (dI/dt)c has to be improved. To reach this aim, a different structure has been developed. In this structure, the different active areas have been decoupled to separate the elementary thyristors and the gate area. This improvement provides the gate triggering in the fourth quadrant. In practice this modification does not lead to a problem because the gate drive circuits generally work in Q1/Q3 or Q2/Q3. (see Figure 8) Figure 8. Basic gate drive circuits in Q1/Q3 or Q2/Q3 operations +Vcc R Diac C µC Opto-triac +Vcc Q1/Q3 operation Q2/Q3 operation For a given technology, the TRIACs commutation behaviour depends on the gate sensitivity. The correlation between the critical (dI/dt)c and the triggering gate current for 12 A TRIACs is represented in Figure 9. For a same current rating and gate sensitivity, Snubberless TRIACs present a (dI/dt)c at least 2 times higher than for standard TRIACs. Figure 9. Correlation between commutation behavior and sensitivity (measurement performed on several lots of 12 A TRIACs) Critical (dI/dt)c (A/ms) Snubberless TRIACs Triacs Standard Triacs TRIACs 30 25 20 15 10 5 IGT (mA) 3rd quadrant 0 10 8/16 20 30 40 50 60 AN439 Logic level and Snubberless TRIACs Logic level TRIACs use the breakthrough of the Snubberless technology to improve the trade-off between sensitivity and commutation. Nevertheless, a snubber can still be necessary with these TRIACs. 2.2 Performances and specifications 2.2.1 Logic level TRIACs In this category, sensitive TRIACs are defined by a maximum gate current (IGT) of 5 mA for the TW type and 10 mA for the SW one. In the datasheets of logic level TRIACs, a minimum (dI/dt)c is specified for the following cases: ● Resistive load with a (dV/dt)c of 0.1 V/µs. ● Inductive load with a (dV/dt)c of 10 V/µs. For example, a 6 A logic level TRIAC is specified as follows: Table 1. (dI/dt)c and (dV/dt)c specifications for a 6 A logic level TRIAC BTA06 / BTB06 Symbol IGT(1) VGT (dI/dt)c (2) Test Conditions Quadrant VD = 12 V RL = 30 Ω Unit TW SW 10 I - II - III MAX. 5 I - II - III MAX. 1.3 (dV/dt)c = 0.1 V/µs Tj = 125 °C (dV/dt)c = 10 V/µs Tj = 125 °C Without snubber Tj = 125 °C MIN. mA V 2.7 3.5 1.2 2.4 - - A/ms 1. Minimum IGT is guaranted at 5% of IGT max 2. For both polarities of A2 referenced to A1 2.2.2 Snubberless TRIACs This series covers the range of 6 to 25 A with gate currents of 35 mA (CW type) and 50 mA (BW type). This series has been specially designed so that the TRIACs turn-off without external snubber circuit. For a same size and gate sensitivity, the (dI/dt)c improvement is at least equal to 2 between Snubberless and standard TRIACs (see Figure 10). 9/16 Logic level and Snubberless TRIACs AN439 Figure 10. Comparison between standard and Snubberless 12 A TRIACs 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (dI/dt)c (A/ms) BTA/BTB12 xBW - ≈ 2 times BTA/BTB12 xB(dV/dt)c (V/µs) 0.1 1 10 100 Whatever the nature of the load, there is absolutely no risk of spurious turn-off triggering if the dI/dtOFF is lower than the specified (dI/dt)c value. The specified (dI/dt)c for a Snubberless TRIAC is higher than the decreasing slope of its rms on-state current specified (IT(RMS)). Equation 11 dI / dt OFF ( A / ms ) = IRMS ( A ) · 2 ·2 π·f( Hz ) ·10 -3 ≈ 0.5 ·IRMS ( A ) dI / dt OFF ( A / ms ) = 0.44 ·IRMS ( A ) for 50 Hz dI / dt OFF ( A / ms ) = 0.53 ·IRMS ( A ) for 60 Hz For example, the slope of the decreasing current in a TRIAC conducting 6 A, 8 A, 10 A, 12 A, 16 A or 25 A when the current drops to zero is given in the Table 2. Table 2 summarizes also the characteristics of the available BW and CW Snubberless TRIACs. Table 2. Type BTA / BTB BTA / BTB BTA / BTB BTA / BTB BTA / BTB 10/16 (dI/dt)c specification for available BW and CW Snubberless TRIACs and slope of the different decreasing rms on-state currents (IT(RMS)) IT(RMS) (A) 6 8 10 12 16 IGT Voltage (VDRM / VRRM) Suffix (V) Max. (mA) Static (dV/dt) Min. (V/µs) (dI/dt)c Min. (1) (A/ms) CW 35 400 3.5 BW 50 1 000 5.3 CW 35 400 4.5 BW 50 1 000 7 CW 35 500 5.5 BW 50 1 000 9 CW 35 500 6.5 BW 50 1 000 12 CW 35 500 8.5 BW 50 1 000 14 600 IT(RMS) x 0.5 (A/ms) 3 600 or 800 4 600 or 800 5 600 or 800 6 600 or 800 8 AN439 Logic level and Snubberless TRIACs Table 2. BTA / BTB (dI/dt)c specification for available BW and CW Snubberless TRIACs and slope of the different decreasing rms on-state currents (IT(RMS)) 25 CW 35 500 13 BW 50 1 000 22 600 or 800 12.5 1. (dI/dt)c specified without snubber 11/16 Logic level and Snubberless TRIACs AN439 2.3 Typical applications 2.3.1 Logic level TRIACs These TRIACs can be directly controlled by logic circuits and microcontrollers like the ST6 or ST7 series. Outputs of ST6/ST7 can sink currents up to 20 mA per I/O line, and therefore drive TW and SW. These TRIACs are ideal interface for power components supplied by 110 V or 220 V, such as valves, heating resistances, and small motors. The specification of the critical (dI/dt)c on both resistive and inductive loads offers: ● Knowledge of the security margin of the circuit in relation to the risk of the spurious triggering ● Optimization of the performance of the TRIAC used, which results in a cost reduction Figure 11. Light dimmer circuit with ST6/ST7 (SW TRIACs type is recommended) +5V LINE 19 18 G 100 A1 MODE +5V SW TRIACs type 1 7 VDD RESET PA0 PA1 PB2 PB1 11 10 220k 14 PB3 NMI 0V 15 ST6/ST7 13 12 100k A2 TOUCH SENSOR 3x 4.7M PB0 TEST PB4 5 0V 6 20 VSS PB5 100k OSCOUT 4 +5V OSCIN 3 220k 8MHz 220k 10p 10p 22k +5V 0V 0V 0V 0V 0V 5.6V zener diode 820 1/2W NEUTRAL 2.3.2 100u 6.3V 220n 400V 1N4148 0V Snubberless TRIACs The commutation of Snubberless TRIACs is specified without a (dV/dt)c limitation. The external snubber circuit can be suppressed for TRIAC turn-off and leads to a noticeable cost reduction. Nevertheless, a snubber circuit is sometimes used to eliminate spurious triggering due to fast line transients (see Figure 13). Thanks to their significant improvement in the trade-off between gate sensitivity (IGT) and critical (dI/dt)c value and also static dV/dt, Snubberless TRIACs are used in circuits which need high safety margin, such as: ● 12/16 Static relays in which the load is not well defined. With standard TRIACs, it is difficult to adapt the snubber to all possible cases. Snubberless TRIACs resolve this problem (see Figure 12). AN439 Logic level and Snubberless TRIACs Figure 12. Solid state relay diagram, using Zero Voltage Switching with opto-TRIAC Solid Solid State State Relay Relay SSR LOAD R1 R2 VMains INPUT C1 T ● Motor drive circuits. The circuit Figure 12 shows an asynchronous motor controlled in both direction by turning on each TRIAC alternately. Figure 13. Motor control circuit using Snubberless TRIACs (Ls + r = network for series protection) M r VMains L C X2 Start Run R2 R1 C2 VDR C1 Gate drive circuit Note: Series impedance (r + L) is needed to protect the blocked TRIAC in case of unwanted triggering (when the other is already on). Only one clamping device (VDR) provides overvoltage protection for both TRIACs (IEC 61000-4-5). Snubber networks (R1C1 and R2C2) eliminate spurious triggering due to fast line transients (IEC 61000-4-4). The specified (dI/dt)c for a Snubberless TRIAC is higher than the decreasing slope of its specified rms on-state current (IT(RMS)). This feature is important for several applications, including: ● Circuits in which the dI/dtOFF is higher than the dI/dtOFF calculated with the Equation 3. For universal motors, due to the impact of the brushes, the dI/dtOFF is typically three times higher (see Figure 14). Table 3 illustrates the component choice optimization by using Snubberless TRIACs. For example, a 8 A Snubberless TRIAC is sufficient to control a 110 V / 600 W motor instead of a 16 A standard TRIAC. 13/16 Logic level and Snubberless TRIACs AN439 Figure 14. TRIAC turn-off behavior for universal motors VT IT dI/dtOFF ~ 3 x ? ω x IPEAK Average slope of the TRIAC current Table 3. Power TRIAC choice for universal motor control dI/dtOFF Standard TRIAC Snubberless TRIAC 3.5 A/ms BTx10-600B BTx06-600BW 10 A 7 A/ms BTx16-600B (2) BTx08-600BW 6 A rms 10 A 7 A/ms 12 A rms 16 A 15 A/ms Mains voltage and frequency Load current IT(RMS) 220 V / 50 Hz 3 A rms 6A 110 V / 60 Hz 6 A rms 220 V / 50 Hz 110 V / 60 Hz Max. (1) 600 W BTx16-600B (2) BTx08-600BW BTx40-600B / BTx41-600B BTx24-600CW 1200 W 1. Maximum dI/dtOFF. This parameter depends on the type of motor and can be higher during start-up. 2. This type specified at 7 A/ms minimum can be too small. Certain applications could need 25 A standard TRIAC. ● Circuits which generate waveforms with a very high dI/dtOFF, such as inductive load controlled by a diode bridge (see Figure 15). The current variation at turn-off is then only limited by the parasitic inductance of the line and the diodes bridge circuit. Figure 15. Inductive load controlled by a diode bridge L VMains 14/16 - + R Inductive load (motor, valve …) AN439 3 Conclusion Conclusion Thanks to the logic level and Snubberless TRIACs, the designer can use devices with a commutation behavior which is compatible with all applications in the 50 or 60 Hz range. This includes phase control and static commutation for loads going from a few watts to several kilowatts. These classes of TRIAC offer: 4 ● An increase in the security margin of circuits, particularly where there is a risk of spurious triggering ● Reduction of costs by using logic level TRIACs, without the need of an interface between the TRIAC gate and the logic circuit, or using Snubberless TRIACs, which are specified without a resistive / capacitive network Revision history Table 4. Document revision history Date Revision Changes May-1992 1 Initial release. 19-Apr-2004 2 Stylesheet update. No content change. 07-Mar-2008 3 Reformatted to current standards. Complete rewrite for text and graphics. Part numbers updated for current products. 15/16 AN439 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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