AN4118
Application note
APWLink USB interface board
for Sound Terminal® demonstration boards
Introduction
This document describes APWLink which has been designed as a USB interface board to
control ST Sound Terminal® demonstration boards through APWorkbench, please refer to
user manual UM1545, “Using the Audio Processor Workbench (APWorkbench)”.
The orderable part number for APWLink is STEVAL-CCA035V1.
Figure 1.
October 2012
APWLink interface board (STEVAL-CCA035V1)
Doc ID 023226 Rev 2
1/13
www.st.com
Contents
AN4118
Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2
3.3 V digital power output to Sound Terminal® demonstration board . . . . . 4
2.3
Connection to Sound Terminal® demonstration board . . . . . . . . . . . . . . . . 4
2.4
LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.5
Analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.6
External I2S input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.7
Serial digital audio input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.8
Jumper configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
Schematic and bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2/13
Doc ID 023226 Rev 2
AN4118
1
Overview
Overview
In addition to providing control signals to the external Sound Terminal® demonstration
board, analog/digital audio inputs are also provided from APWLink.
The system connections are shown below in the following figure.
Figure 2.
System connections
Analog
Digital
source
source
APWorkbench
USB Cable
APWLink
Figure 3.
Sound Terminal ® demonstration board
APWLink general view
Doc ID 023226 Rev 2
3/13
Configuration
2
Configuration
2.1
Power supply
AN4118
APWLink is directly powered by a USB cable (Type B). No external power supply is needed.
Note that this power supply is NOT for the power bridge supply on the Sound Terminal®
demonstration board. Please refer to the application note of each specific Sound Terminal®
demonstration board.
2.2
3.3 V digital power output to Sound Terminal® demonstration
board
Jumper J12 is used for the selection of the external Sound Terminal® demonstration board
digital power supply. When J12 is closed, 3.3 VDC is provided to the external Sound
Terminal® demonstration board, and if the external Sound Terminal® demonstration board
has its own 3.3 V digital power supply, J12 has to be left open to avoid any current loop.
2.3
Connection to Sound Terminal® demonstration board
APWLink is simply connected to the Sound Terminal® demonstration board through J10, an
on-board 16-pin female 8x2 2.54 mm connector as shown below.
Figure 4.
4/13
Connection to Sound Terminal® demonstration board
Doc ID 023226 Rev 2
AN4118
2.4
Configuration
LEDs
APWLink provides the following three LEDs:
●
D1: power supply
–
●
–
●
ON when communication between PC and APWLink is wrong
Digital audio input error
–
2.5
ON when USB power is supplied
D2: communication wrong
ON when the digital input signal is not validated or no digital signal is input
Analog input
An analog signal (can be DC coupled) can be input from J9 (3.5 mm phone jack). There is
an on-board ADC (ST part number: STA529Q) to convert the analog signal to a digital I2S
format signal and feed it to the external Sound Terminal® demonstration board. To enable
the on-board STA529Q ADC, the following actions should be taken within APWorkbench as
shown in the screenshots below.
Figure 5.
Enabling the ADC using APWorkbench
Doc ID 023226 Rev 2
5/13
Configuration
2.6
AN4118
External I2S input
The external I2S signal can be input to APWLink through J15 directly. For example, the
external I2S signal can come from an external ADC if the on-board ADC is bypassed. J5
includes the analog signals from J9 (stereo analog input jack), plus 3.3 VDC power supply,
which can be fed to the external ADC. The I2S from the external ADC can be fed into
APWLink through J15, as indicated below.
Figure 6.
2.7
I2S input from an external ADC through J15
Serial digital audio input
Electrical and optical inputs are supported on-board to receive serial digital audio signals. A
jumper (JP2) is used to select either the electrical or optical signal. The input signal is then
converted to an I2S format by the on-board decoder (ST part number: STA120D) and fed to
the external Sound Terminal® demonstration board.
Serial digital formats supported by the STA120D:
●
S/PDIF
●
AES/EBU
●
IEC 958
●
EIAJ CP-340/1201
The proper jumper setting is described in Section 2.8: Jumper configuration.
6/13
Doc ID 023226 Rev 2
AN4118
Configuration
2.8
Jumper configuration
Table 1.
Jumper configuration
Jumper
Mode
Serial digital input
External I2S
On-board
ADC(1)
J2
LR clock from STA529Q - on-board ADC
Open
Open
Close
J3
Bit clock from STA529Q - on-board ADC
Open
Open
Close
J4
I2S data from STA529Q - on-board ADC
Open
Open
J5
Analog output / 3.3 VDC for external ADC
J7
MCLK to STA529Q – on-board ADC
J12
3.3 VDC to external Sound
demonstration board
J13
Reserved, not used
Terminal®
All open
Close
(2)
See footnote
All open
Open
Open
Close
Close
Close
Close
All open
All open
All open
See footnote(3)
All open
Close only the relevant pins
J15
I2S selector for external
Sound Terminal® demonstration board
J16
I2S data selector for external Sound
Terminal® demonstration board
All close
All close
All close
JP1
Reserved, not used
All open
All open
All open
Do not care
Do not care
For electrical:
JP2
Serial digital audio source selector
For optical:
1. APWorkbench supports on-board ADC function.
2. Please refer to Section 2.6: External I2S input on page 6 for detailed signal definition for each pin.
3. Please refer to Section 2.6: External I2S input on page 6 for detailed signal definition for relevant pins. All other pins can be
left open.
Doc ID 023226 Rev 2
7/13
Schematic and bill of material
AN4118
3
Schematic and bill of material
Figure 7.
APWLink schematic - part 1
VCC_USB
L1
VCC_USB
VCC_USB
C3
C4
27pF
Y1
6.000MHz
27pF
R3
470R
BEAD
+ C6
C5
10nF
C7
D1
R1
33uF100nF
TP8
TP2
TP7
%'%86
%'%86
9&&
%'%86
%'%86
;7,1
3:5(1
$*1'
;7287
7(67
%&%86
%&%86
6,:8$
%&%86
$&%86
6,:8%
$&%86
*1'
$'%86
*1'
$'%86
%&%86
$'%86
86%'0
$'%86
C9
33nF
86%'3
TP6
TP4
TP5
VCC_3V3
TP9
TP10
TP11
TP12
R11
10k
R13
5k1
R14
C8
100nF 5k1
TP13
TP14
13
14
15
16
17
18
19
20
21
22
23
24
USB
9&&,2%
$'%86
10k
C10
47pF
%'%86
$'%86
R10
VCC_3V3
4
567287
*1'
R12
3
'
*1'
27R
%'%86
9287
$'%86
2
'
*1'
FT2232D
5(6(7
TP3
36
35
34
33
32
31
30
29
28
27
26
25
%'%86
U2
9&&
$'%86
1k5
27R
R9
%'%86
(('$7$
9&&,2$
1
9%86
((6.
$&%86
J6
1
2
3
4
5
6
7
8
9
10
11
12
$&%86
R4 10k
R8
$9&&
((&6
48
47
46
45
44
43
42
41
40
39
38
37
Green
TP1
R2 1M
C1
100nF
470R
C2
100nF
I2C_CTRL
FTDI_SCL
FTDI_SA
CONF_TH_W
FTDI_XTI
FTDI_TMODE
CONF_FAIL
0R
R15
R16
VCC_USB
VCC_3V3
L2
96
1
*1'
2
C54 +
10uF
C12
100nF
C14
100nF
3
'$7$
C13
100nF
VCC_3V3
BEAD
J9
VCC_3V3
470R
D2
Red
FTDI_SDA
FTDI_RESET
FTDI_STBY
FTDI_MUTE
JP2
1
&
2
&G)
3
&F)
4
&E(
C16 100nF
SPDT/SM
28
(5)
27
DATA_SPDIF
5
&D(
0
24
&(
0
23
7
9'
8
'*1'
U3
STA120D
R17
D3
560R
Blue
25
9$
22
$*1'
21
9
5;3
),/7
20
10
5;1
0&.
19
0
18
L3
C15 BEAD
100nF
R18 330R C19470nF
R20 4R7
C17
100nF NS
R19
82R
&H)
6
*3)$95.
J11
9(5)
6'$7$ 26
11 )6<1&
C21
100nF NS
C20
100nF
12
6&.
0
17
13
&6)&.
6(/
16
14
8
&%/
15
XTI_SPDIF
C18 15nF
BICK_SPDIF
LRCK_SPDIF
VCC_1V8
SDATAI_030
LRCKI_030
BICKI_030
R22
0R
VCC_3V3
VCC_3V3
C26
100nF
C24
100nF
C25
100nF
C23
82pF
R24
FILT
GNDPLL
VDD2
GND2
VDDPLL
LRCLKI
SDATAI
LRCLKO
SDATAO
I2CDIS
U4
AGND
TM
STA030 / STA529Q
VCM
PWRFAULT/EADP
VCC33
RST_N
GNDIO1
VDD1
GND33
VCC2A
VDDIO1
GND1
OUT2A
CLKOUT
GND2A
Y#PV
VLO
39
38
37
36
35
34
33
32
31
30
29
28
27
C22
220pF
R27 0R
CONF_MCLKI
R38 100R
R39
C52
120pF
VCC_3V3
8/13
C37
C38
100nF
1uF
Doc ID 023226 Rev 2
100R
FTDI_SDA
FTDI_SCL_030
C53
10pF
C35
100nF
14
15
16
17
18
19
20
21
22
23
24
25
26
C49
100nF
C36
100nF
SCL
GND2B
C33 10nF
SDA
VHI
OUT2B
10k
SELCLK33
AVDD
VCC2B
+
R35
VCC_1V8
VBIAS
VCC1B
VCC_3V3
+
C32
C30
10nF
100nFC31
10uF
C34
10uF
XTI
MCLK33
GND1B
C29 +
10uF
AGND
470R
XTO
INR
OUT1B
R30
BICLKI
BICLKO
C28 1uF
R28
4k7
0R
12k
INL
MUTE
R29
4k7
R31
0R
STBY
VCC1A
R26 4k7
ADC_IN
1
2
3
4
5
6
7
8
9
10
11
12
13
OUT1A
+
2
3
VDDIO2
R23
0R
C27 1uF
R25 4k7
1
+
J14
GND1A
AINL
AINR
GNDIO2
52
51
50
49
48
47
46
45
44
43
42
41
40
R21
VCC_3V3
AN4118
Schematic and bill of material
Figure 8.
APWLink schematic - part 2
J15
1
2
3
J3
BICKI_030
CONF_BICKI
5
CONF_LRCKI
8
4
LRCKI_030
J4
SDATAI_030
CONF_SDATAI1
CONF_SDATAI2
1
2
3
4
5
CONF_SDATAI3
7
10
6
13
14
CONF_MCLKI
CONF_SDATAO
17
CONF_CLKOUT
20
16
3
1
19
CONF_CLKOUT
21
SPDT/SM
VCC_XT VCC_3V3
R40
4
2
CONF_SDATAO
18
VCC_XT
FTDI_XTI
XTI_SPDIF
15
JP1
0R
J7
Y2
12.288MHz
DATA_SPDIF
12
R7
10k
LRCK_SPDIF
9
11
J16
R6
BICK_SPDIF
6
J2
10R
C11
100nF
VCC_3V3
1
100R
2
3
C48
100nF
,1
6
9&&
'
*1'
6
6
10k
R33
U1
R32
I2C_CTRL
10k
R34
VCC_3V3
FTDI_SCL_EXT
5
FTDI_SCL
4
FTDI_SCL_030
STG719
J13
FTDI_TMODE
CONF_CLKOUT
FTDI_SA
9
10
7
8
5
6
3
4
1
CONF_SDATAO
C47
16
13
14
11
12
9
10
7
8
5
6
CONF_SDATAI3
3
4
CONF_SDATAI1
1
2
0R
J12
VCC_3V3
2
FTDI_MUTE
R36
FTDI_SCL_EXT
VCC_3V3
100R
CONF_BICKI
J5
1
2
C51
10pF
3
+
4
AGND
J10
15
AUX_CON
AINR
47pF
R5
CONF_MCLKI
100uF C55
CONF_TH_W
MB_CON
FTDI_STBY
FTDI_RESET
R37
CONF_FAIL
FTDI_SDA
100R
CONF_LRCKI
CONF_SDATAI2
C50
120pF
5
AINL
VCC_3V3 VCC_USB
VCC_USB
VCC_1V8
U6
LD2985A18
Vin
1
GND
Vin
100nF
Vout
33uF
C44
Vout
+ C43
C45
C46+
100nF
10uF
C39
C40
1uF 100nF
3
Vout
5
GND
2
INH BYPASS
U5 AP1117_33
Doc ID 023226 Rev 2
+ C41
4
10uF
C42
100nF
9/13
Schematic and bill of material
Table 2.
Item Qty
AN4118
Bill of material
Reference
Part name
Value
Footprint
1
1
U1
IC
STG719
SOT23-6L
2
1
U2
IC
FT2232D
LQFP48
3
1
U3
IC
STA120D
SO28
4
1
U4
IC
STA529Q
VFQFPN52
5
1
U5
IC
LD1117
SOT223
6
1
U6
IC
LD2985B18
SOT23-5L
7
1
D1
LED
Green
0603
8
1
D2
LED
Red
0603
9
1
D3
LED
Blue
0603
10
3
L1-3
Ferrite bead
600 ohms / 100 MHz
0805
11
1
Y1
Crystal,
6.000 MHz
6.000 MHz
XTAL_HC49SMT
12
1
Y2
Oscillator,
12.288 MHz
12.288 MHz
SMD, 7 mm x 5 mm
13
5
J2-4, J7, J12
Header
Header 2 x 1
2.54 mm x 2
14
1
J5
Header
Header 5 x 1
2.54 mm x 5
15
1
J6
USB
connector
Type B
Type B
16
1
J9
Optical
receiver
GP1F31R
17
1
J10
Female
connector
Female 8 x 2
2.54 mm x 8 x 2
18
1
J11
RCA
RCA connector
RCA
19
1
J13
Header
Header 5 x 2
2.54 mm x 5 x 2
20
1
J14
21
1
J15
Header
Header 7 x 3
2.54 mm x 7 x 3
22
1
J16
Header
Header 3 x 2
2.54 mm x 3 x 2
23
2
JP1-2
Header
Header 3 x 1
2.54 mm x 3
24
24
C1-2, C7-8, C11-16, C20,
C24-26, C30, C35-37, C40,
C42, C44-45, C48-49
CAP
100 nF
0603
25
2
C17, C21
CAP
100 nF NS
0603
26
3
C5, C32-33
CAP
10 nF
0603
27
2
C51, C53
CAP
10 pF
0603
28
2
C50, C52
CAP
120 pF
0603
29
1
C18
CAP
15 nF
0603
10/13
Remarks
bottom
side
Headphone
Stereo headphone jack
jack
Doc ID 023226 Rev 2
Not fitted
AN4118
Table 2.
Item Qty
Schematic and bill of material
Bill of material
Reference
Part name
Value
Footprint
30
2
C38-39
CAP
1 µF
0603
31
1
C22
CAP
220 pF
0603
32
2
C3-4
CAP
27 pF
0603
33
1
C9
CAP
33 nF
0603
34
1
C19
CAP
470 nF
0603
35
2
C10, C47
CAP
47 pF
0603
36
1
C23
CAP
82 pF
0603
37
1
C55
TantalumCAP
100 µF
Sized
38
6
C29, C31, C34, C41, C46, C54
TantalumCAP
10 µF
1206
39
2
C27-28
TantalumCAP
1 µF
1206
40
2
C6, C43
TantalumCAP
33 µF
1206
41
8
R5, R7, R15, R22-24, R27,
R31
RES
0R
0603
42
5
R32, R36-39
RES
100R
0603
43
1
R40
RES
10R
0603
44
7
R4, R6, R10-11, R33-35
RES
10K
0603
45
1
R21
RES
12K
0603
46
1
R2
RES
1M
0603
47
1
R8
RES
1K5
0603
48
2
R9, R12
RES
27R
0603
49
1
R18
RES
330R
0603
50
4
R1, R3, R16, R30
RES
470R
0603
51
1
R20
RES
4R7
0603
52
4
R25-26, R28-29
RES
4K7
0603
53
1
R17
RES
560R
0603
54
2
R13-14
RES
5K1
0603
55
1
R19
RES
82R
0603
Doc ID 023226 Rev 2
Remarks
11/13
Revision history
4
AN4118
Revision history
Table 3.
12/13
Document revision history
Date
Revision
Changes
22-Jun-2012
1
Initial release.
16-Oct-2012
2
Minor textual updates; revised presentation of schematics.
Doc ID 023226 Rev 2
AN4118
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Doc ID 023226 Rev 2
13/13