dm00042610

AN4015
Application note
Dual-BTL class-D audio amplifier demonstration board
based on the TDA7498E
Introduction
The purpose of this application note is to describe:
■
how to connect the TDA7498 demonstration board
■
how to evaluate the performance of the demonstration board using the electrical curves
■
how to avoid critical issues in the PCB schematic and layout of the TDA7498E
The TDA7498E represents a new generation of analog input class-D devices from
STMicroelectronics and is housed in a PSSO36 package. It is able to deliver 160 W +160 W
in stereo configuration with VCC = 36 V and a 4 Ω load(a).
Figure 1.
TDA7498E demonstration board
a. All of the results and graphs included in this document are measured using Audio Precision equipment.
January 2012
Doc ID 022507 Rev 1
1/22
www.st.com
Contents
AN4015
Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Test conditions and connections of the demonstration board . . . . . . . 5
2.1
Power supply and interface connection . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2
Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3
Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Schematic diagram and PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Test curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6
Design guidelines for PCB schematic and layout . . . . . . . . . . . . . . . . 14
6.1
6.2
7
2/22
Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1.1
Main driver for the selection of components . . . . . . . . . . . . . . . . . . . . . 14
6.1.2
Decoupling capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1.3
Output filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Doc ID 022507 Rev 1
AN4015
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
TDA7498E demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
TDA7498E demonstration board connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
TDA7498E schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PCB layout - top side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PCB layout - bottom side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PCB layout - top and bottom sides plus components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
THD+N vs. power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
THD+N vs. frequency (ref = 1 W at 1 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DNR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
FFT (0 dBr at 1 W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Pout vs. VCC and THD level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Snubber filter - solution 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Snubber filter - solution 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Dumping network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Frequency shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Decoupling capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Snubber network. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
VCC decoupling electrolytic capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
ROSC - component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Filter capacitors for SVR, VREF, SVCC, VSS and VDDPW. . . . . . . . . . . . . . . . . . . . . . . . 19
Input signal routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Signal ground and power ground routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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Overview
1
AN4015
Overview
The following terms used in this application note are defined as follows:
●
THD+N vs. Pout: Total Harmonic Distortion (THD) plus noise versus output power
●
THD+N vs. Freq: Total Harmonic Distortion plus noise versus frequency curve
●
S/N Ratio: Signal-to-noise ratio
●
DNR: Dynamic range
●
FFT: Fast Fourier Transform Algorithm (method)
●
XTalk: Channel separation L to R, or R to L channel crosstalk
The equipment used includes the following:
●
Audio Precision 2722A + AES-17 filter + DCX+ AUX-0025 filter
●
DC power supply
●
Digital oscilloscope (Tektronix TDS5054B)
●
Differential voltage probe (LeCroy AP031)
●
Current probe (Tektronix TCP300)
Reference documents include:
4/22
●
TDA7498E datasheet
●
Schematic diagram
●
PCB layout
●
Test curves
Doc ID 022507 Rev 1
AN4015
Test conditions and connections of the demonstration board
2
Test conditions and connections of the
demonstration board
2.1
Power supply and interface connection
2.2
1.
Connect PSU to the VCC terminal block
2.
Connect the analog input cable to the RCA connectors on the demonstration board, the
other side must be connected to a signal source such as the Audio Precision analog
outputs or a DVD player
Output configuration
The TDA7498E demonstration board has been configured in 2-channel BTL output.
2.3
Connections
The board terminals (top view of demonstration board) are visible in Figure 2.
Figure 2.
TDA7498E demonstration board connections
Left Load
Right Load
Gain selection
Single-ended
input/differential
input mode
selection
Analog input
Doc ID 022507 Rev 1
Standby and mute
controls
5/22
Schematic diagram and PCB layout
AN4015
3
Schematic diagram and PCB layout
Figure 3.
TDA7498E schematic
6/22
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AN4015
Schematic diagram and PCB layout
Figure 4.
PCB layout - top side
Figure 5.
PCB layout - bottom side
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7/22
Schematic diagram and PCB layout
Figure 6.
8/22
AN4015
PCB layout - top and bottom sides plus components
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AN4015
4
Electrical characteristics
Electrical characteristics
Referring to Figure 3: TDA7498E schematic, the Left (L) and Right (R) channels are the
output for a stereo configuration. VCC = +36 V, Gain 23.6 dB; Tamb = 25.5 °C;
InputFreq = 1 kHz; RefLevel = 1 W (0 dBr), Load = 4 Ω (resistive dummy load).
Table 1.
Electrical characteristics
THD+N vs. power
Pout = 1 W
0.0555%
12 A
IOCP
No filter
-74.3 dB
AW - filter
-77.5 dB
No filter
-94 dB
AW - filter
-98 dB
1 kHz
-85.9 dB
SNR
DNR
Xtalk
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Test curves
5
AN4015
Test curves
Figure 7.
THD+N vs. power
10
5
2
1
0.5
%
0.2
0.1
0.05
0.02
0.01
1m
2m
5m
10m 20m
50m 100m
500m
1
2
5
10
20
50
100
200 400
W
Sweep
Trace
Color
Line Style
Thick
Data
Axis
Comment
1
1
1
3
Red
Blue
Solid
Solid
2
2
Anlr.THD+N Ratio
Anlr.THD+N Ratio
Left
Left
Vcc=36V; Load=4ohm; 1kHz; Ch L
Vcc=36V; Load=4ohm; 1kHz; Ch R
Figure 8.
THD+N vs. frequency (ref = 1 W at 1 kHz)
1
0.5
0.2
%
0.1
0.05
0.02
0.01
20
50
100
200
500
1k
2k
5k
10k
Hz
10/22
Sweep
Trace
Color
Line Style
Thick
Data
Axis
1
1
1
2
Red
Blue
Solid
Solid
2
2
Anlr.THD+N Ratio
Anlr.THD+N Ratio
Left
Left
Doc ID 022507 Rev 1
Comment
Vcc=36V; [email protected]; Ch L
Vcc=36V; [email protected]; Ch R
20k
AN4015
Test curves
Figure 9.
DNR
-20
-25
-30
-35
-40
-45
d
B
-50
-55
-60
-65
-70
-75
-80
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
+0
dBr
Sweep
Trace
Color
Line Style
Thick
Data
Axis
Comment
1
1
2
2
1
2
1
2
Red
Blue
Green
Black
Solid
Solid
Solid
Solid
2
2
2
2
Anlr.THD+N Ratio
Anlr.THD+N Ratio
Anlr.THD+N Ratio
Anlr.THD+N Ratio
Left
Left
Left
Left
Vcc=36V_1kHz_4 ohm;
Vcc=36V_1kHz_4 ohm;
Vcc=36V_1kHz_4 ohm;
Vcc=36V_1kHz_4 ohm;
Ch L
Ch R
Ch R - AW Filter
Ch L - AW Filter
Figure 10. FFT (0 dBr at 1 W)
d
B
r
A
+0
+0
-10
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-100
-110
-110
-120
-120
-130
-130
-140
-140
-150
20
50
100
200
500
1k
2k
5k
10k
20k
d
B
r
B
-150
Hz
Sweep
Trace
Color
Line Style
Thick
Data
Axis
Comment
1
1
1
2
Red
Blue
Solid
Solid
2
2
Fft.Ch.1 Ampl
Fft.Ch.2 Ampl
Left
Right
Vcc=36V; Ref: [email protected]: Ch L
Vcc=36V; Ref: [email protected]: Ch R
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Test curves
AN4015
Figure 11. Crosstalk
+0
-10
-20
-30
-40
-50
d
B
-60
-70
-80
-90
-100
-110
-120
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Sweep
Trace
Color
Line Style
Thick
Data
Axis
Comment
1
1
1
2
Red
Blue
Solid
Solid
2
2
S2C.Anlr.Crosstalk
S2C.Anlr.Crosstalk
Left
Left
Vcc=36V; 1W; 4ohm; (Ch L on)
Vcc=36V; 1W; 4ohm; (Ch R on)
Figure 12. Linearity
Gain Linearity
24
23.5
23
Gain [dB]
22.5
22
21.5
21
20.5
Left
Right
20
12/22
0
0.2
0.4
0.6
0.8
1
1.2
Input Level [V]
Doc ID 022507 Rev 1
1.4
1.6
1.8
2
AN4015
Test curves
Figure 13. Bandwidth
+1
+1
+0.5
d
B
r
A
+0.5
+0
+0
-0.5
-0.5
-1
d
B
r
-1
-1.5
-1.5
-2
B
-2
-2.5
-2.5
-3
10
20
50
100
200
500
1k
2k
5k
10k
20k
50k
-3
Hz
Sweep
Trace
Color
Line Style
Thick
Data
Axis
Comment
1
1
1
2
Red
Blue
Solid
Solid
2
2
Anlr.Level A
Anlr.Level B
Left
Right
Vcc=36V; 1W; Ch L
Vcc=36V; 1W; Ch R
Figure 14. Pout vs. VCC and THD level
200
180
160
140
120
W
100
80
60
40
20
+10
+12.5
+15
+17.5
+20
+22.5
+25
+27.5
+30
+32.5
+35
+37.5
+40
Vdc
Sweep
Trace
Color
Line Style
Thick
Data
1
2
3
4
1
1
1
1
Cyan
Green
Blue
Red
Solid
Solid
Solid
Solid
2
2
2
2
Anlr.Level
Anlr.Level
Anlr.Level
Anlr.Level
Doc ID 022507 Rev 1
A
A
A
A
Axis
Comment
Left
Left
Left
Left
Pout
Pout
Pout
Pout
vs.
vs.
vs.
vs.
Vcc;
Vcc;
Vcc;
Vcc;
Load=4ohm;
Load=4ohm;
Load=4ohm;
Load=4ohm;
THD=1%
THD=10%
THD=20%
THD=30%
13/22
Design guidelines for PCB schematic and layout
6
Design guidelines for PCB schematic and layout
6.1
Schematic
6.1.1
Main driver for the selection of components
6.1.2
AN4015
●
Absolute maximum rate (input VCC supply): 40 V
●
Bypass capacitor 100 nF in parallel to 1µF for each power VCC branch. Dielectric X7R
is suggested.
●
Coil saturation current must be compatible with the peak current of application
Decoupling capacitors
There are two different ways to use the decoupling capacitors:
6.1.3
14/22
●
The decoupling capacitor(s) can be shared among channels; the layout must be
designed to implement a "star route" for the VCC paths.
●
One decoupling capacitor can be used for each channel. It is mandatory that each
decoupling capacitor be placed as close as possible to the IC pins. This solution is
implemented on the TDA7498E demonstration board.
Output filter
●
Snubber network: the key function of a snubber network is to absorb energy from the
inductive component in the power circuit (the output coils and the speaker). The
purpose of the snubber RC network is to dissipate the unnecessary high pulse energy,
such as a high voltage spike, in the power circuit which is dangerous to the system.
●
Main filter (low-pass filter): The purpose of the main filter is to remove the carrier
frequency (≈310 kHz) and to cut off the frequency higher than the audible range of
20 kHz. The LPF filter is implemented by a passive Butterworth topology. In order to
have a clean and flat frequency response, it is mandatory to design the filter to fix the
cutoff frequency a little bit above 20 kHz.
●
Damping network: The purpose of the damping network is to avoid the high-frequency
oscillation issue on the output circuit. When the load is disconnected from the amplifier,
the frequency response of the main filter is not flat and there is the possibility of adding
gain in a frequency band. The damping network also improves the THD performance.
The damping network can also avoid the inductive effect of the PCB tracks when the
system is working at high frequency with PWM.
Doc ID 022507 Rev 1
AN4015
Design guidelines for PCB schematic and layout
Snubber filter
The snubber circuit must be optimized for the specific application. Starting values are
330 pF in series to 22 ohm. The power dissipation of this network (resistor) depends on the
power supply, frequency and capacitor values using following formula:
P = C ⋅ f ⋅ (2 ⋅ V)
2
This power is dissipated on the series resistance.
Figure 15. Snubber filter - solution 1
INxA
C126
330p
R44
22
INxB
To increase the efficiency, it is possible to use two equal snubber networks toward GND. In
this case, the formula to evaluate power is:
P = C⋅f⋅2⋅V
2
This power is dissipated on the resistance.
Figure 16. Snubber filter - solution 2
INxA
C127
330p
R45
22
R46
22
INxB
C130
330p
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Design guidelines for PCB schematic and layout
AN4015
Dumping network
The C-R-C is a dumping network. It is mainly intended for high inductive loads and for
common-mode noise attenuation.
Figure 17. Dumping network
PWM output frequency shifting for AM band radio sensitivity improvement
Using a logic control signal (FS) from MCU or from a DSP (3.3 V) it is possible to modify the
PWM output frequency.(b)
Figure 18. Frequency shift
b. For the PWM frequency calculation formula please refer to the datasheet.
16/22
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AN4015
6.2
Design guidelines for PCB schematic and layout
Layout
●
Solder 100 nF and 1µF bypass ceramic capacitors as close as possible to the related
IC pin
●
To avoid the effect due to the parasitic inductive coil generated by the copper wires, it is
suggested to use the ceramic capacitor to balance the reactance. It's mandatory to
place the ceramic capacitor as close as possible to the related pins. The distance
between the capacitor to the related pins is recommended to be within 5 mm.
Figure 19. Decoupling capacitors
Ground pin and Vcc pin of
100 nF and 1μF capacitors
should be connected to the
related IC pin directly
●
Solder the snubber networks as close as possible to the related IC pin. A high level
spike may occur if the snubber network is placed too far from the pins. It's
recommended that the distance from the snubber network be within 3 mm which takes
into consideration the width of the copper wire.
Figure 20. Snubber network
Snubber network
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Design guidelines for PCB schematic and layout
●
Use electrolytic capacitors first to separate the VCC branches. A "star route" for the VCC
supply is suggested to avoid interference between the channels such as when one
channel is idle while the other channel is working with a full load. In applications with
high output power, another approach is to filter the two channels separately. This
solution is implemented in this demonstration board.
Figure 21. VCC decoupling electrolytic capacitors
●
ROSC network: Place the RC filter for the ROSC pin close to the IC
Figure 22. ROSC - component placement
R-C network for
ROSC
18/22
AN4015
Doc ID 022507 Rev 1
AN4015
Design guidelines for PCB schematic and layout
●
Place the filter capacitors for SVR, VREF, SVCC, VSS and VDDPW close to the IC.
Figure 23. Filter capacitors for SVR, VREF, SVCC, VSS and VDDPW
Filter capacitors for
VREF, SVCC and
VSS
Filter capacitor for SVR
Filter capacitors
for VDDS and
VDDPW
●
Input signal routing
Figure 24. Input signal routing
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Design guidelines for PCB schematic and layout
●
Signal ground and power ground routing: the signal ground should be connected to the
bulk capacitor negative terminal via a dedicated copper track; no vias must be present
in the connection path.
Figure 25. Signal ground and power ground routing
20/22
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7
Revision history
Revision history
Table 2.
Document revision history
Date
Revision
09-Jan-2012
1
Changes
Initial release.
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AN4015
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