AN4209 Application note Design methodology for repetitive voltage suppressors (RVS) in repetitive mode: STRVS Introduction The silicon transient voltage suppressor (TVS) device such as the Transil™ was initially specified with a power surge capability to respond to industrial standard test conditions, especially against high-energy single transient voltages. Today, many components in switched mode power supplies are continuously subjected to very short transient voltages. Little data is given in TVS specifications regarding the repetitive mode operation. Therefore, it is not easy for the designer to accurately assess the clamping voltage and power losses under these conditions. This application note introduces the new repetitive voltage suppressor STRVSX features, specifically adapted to the repetitive mode operation. A design guideline is presented and selection processes are described. September 2013 DocID023949 Rev 2 1/19 www.st.com Contents AN4209 Contents 1 STRVS parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1.1 1.2 2 Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2.1 Steady state parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2.2 Transient parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 General design procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 Key Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.2 Transil selection process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.3 3 Simplified electrical model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2.1 Step 1: STRVS pre-selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.2 Step 2: Clamping voltage assessment . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.3 Step 3: Dissipated power calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.4 Step 4: In-situ test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Transil selection flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Design example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 STRVS preselection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 Clamping voltage assessment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3 Dissipated power calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4 3.3.1 Power losses calculation: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3.2 Peak and average junction temperature calculation: . . . . . . . . . . . . . . . 16 In-situ verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2/19 DocID023949 Rev 2 AN4209 1 STRVS parameters STRVS parameters This section defines the electrical and thermal characteristics of the STRVS. Electrical parameters V RM (25°C ) V BR (25°C ) Figure 1. Typical reverse characteristic VR = (IR) of an STRVS device V CL (25°C ) 1.1 V(V) 0 IRM(25°C)- 1µA IBR(25°C)- 1mA IPP(25°C) TJ2 > TJ1 TJ1= 25°C I(A) Figure 1 shows the typical reverse characteristic given at two temperatures of an STRVS device. Stand-off voltage (VRM) The stand-off voltage is specified for I = IRM = 1 µA and Tj = 25 °C. Under these conditions, the device is still acting as an open circuit. This parameter is one of the key parameters in circuit protection. Breakdown voltage (VBR) The breakdown voltage corresponds to the voltage from which the STRVS starts to go into the avalanche region. This parameter is specified for I = IBR = 1 mA and Tj = 25 °C. The VBR parameter follows a linear variation with junction temperature as shown in Equation 1. Equation 1 VBR (Tj ) = VBR (TREF)·(1+ α T · (Tj - TREF)) Where TREF = reference temperature expressed in °C, generally given at 25 °C and T = temperature coefficient in 1/°C. DocID023949 Rev 2 3/19 STRVS parameters AN4209 Clamping voltage (VCL) The clamping voltage is the total voltage across the STRVS over the peak pulse current IPP at a given temperature. A range of typical values provides the characteristics of the clamping voltage for given values of peak current (IPP), and three controlled junction temperatures: 25 °C, 85 °C and 125 °C. All curves start from VCL(1 mA) = VBRmax. Figure 2 illustrates VCL curves of an STRVS185X02B. These curves are useful for verifying the suitability of the allowable clamping voltage in application. Figure 2. Clamping voltage characteristic over temperatures of an STRVS185X02B I (A) 5.0 Tj=85°C Tj=25°C Tj=125°C 4.0 3.0 2.0 1.0 1m 0.0 155 1.1.1 VBRmax VBRmax VBRmax 25°C 85°C 125°C 160 165 170 175 VCL (V) 180 185 190 195 Simplified electrical model A linear model can be employed to approximate the VCL = f (IPP) characteristics of the STRVS. A straight line is used to approximate the actual curve inside the working area imposed by the application conditions (see Figure 3). The line intersects the horizontal axis at the voltage VCL0. The slope of the line is inversely proportional to the dynamic resistance RD. The equivalent circuit that models this equation is shown in Figure 4. 4/19 DocID023949 Rev 2 AN4209 STRVS parameters VBR(T j) VCL0 (T j) VCL1 (I CL1 ; T j) VCL2 (I CL2 ; T j) Figure 3. Simplified characteristics of an STRVS device V(V) IPP1 IPP2 1/RD (IPP1; IPP2; Tj) Operating region I (A) Figure 4. Simplified electrical model of an STRVS device V CL K A I PP V CL (IPP; Tj) I PP RD V CL0 (IPP1; IPP2; Tj) (IPP1; IPP2; Tj) A simple rule to calculate RD and VCL0 is to use IPP2=Ipeak of the application and IPP1 = IPP2 / 2 The clamping voltage is defined in Equation 2. Equation 2 VCL ( I PP ; Tj ) = VCL0 ( I PP1; I PP2 ; Tj ) + RD( I PP1; I PP2 ; Tj ) · I PP DocID023949 Rev 2 5/19 STRVS parameters AN4209 RD can be calculated as shown in Equation 3. Equation 3 RD( I PP1; I PP2 ; TJ ) = VCL2 ( I PP2 ; Tj ) - VCL1 ( I PP1; Tj ) I PP2 - I PP1 VCL0 is shown in Equation 4 Equation 4 VCL0 ( I PP1; I PP2 ; Tj ) = VCL1 ( I PP1; Tj ) - RD ( I PP1; I PP2 ; Tj ) · I PP1 This model will be useful to assess the power dissipation of the device. 1.2 Thermal parameters 1.2.1 Steady state parameters Thermal resistance (Rth(j-Ref)) The thermal resistance represents the package's dissipation capability from the junction (active die surface) to a specified reference point (case, lead, board, ambient, etc…). Its value is defined as the temperature difference between two specified points, divided by the dissipated power under thermal equilibrium conditions. Equation 5 RTH ( j - Re f ) = Tj - TRe f PD Where: Rth(j-Ref) Junction-to-reference thermal resistance expressed in °C/W PD Average dissipated power of the die, expressed in W Tj Junction temperature of the die expressed in °C TRef Temperature of the reference point expressed in °C The previous equation can be easily reworked to estimate the junction temperature in steady mode operation as shown in Equation 6. Equation 6 Tj = RTH ( j - Re f ) · PD + TRe f In STRVSX specifications, the junction-to-lead (Rth(j-l)) and junction-to-ambient (Rth(j-a)) thermal resistances are commonly provided to help designers. These parameters are determined under standard test conditions with specific board dimensions and layers in compliance with the JEDEC standard. Table 1 shows typical thermal resistances for available packages. 6/19 DocID023949 Rev 2 AN4209 STRVS parameters Table 1. Typical package performance comparison for minimum footprint and 35 µm copper thickness on board Package Thermal resistance Unit DO-15 DO-201 SMB SMC Junction-to-lead, Rth(j-l) 35 23 13 12 °C/W Junction-to-ambient Rth(j-a) 105 100 185 150 °C/W Junction-to-ambient thermal resistance (Rth(j-a)) The thermal resistance Rth(j-a) is the heat dissipation capability from the junction surface of the die to the ambient, via all paths. Its value is strongly dependent on the type of board, the copper plane underneath the device, the neighboring components interacting through the PCB, and the mounting and cooling methods (free or forced airflow). Actual performance of the product in real applications may be different. Values provided in datasheet are typical values and should be used with some measure of caution. It is useful for comparing the thermal performance of one package to another as shown in Table 1. Therefore, this information may be used for the first pass of junction temperature calculation. The thermal resistance Rth(j-a) value with minimum footprint is recommended when the user starts a design calculation. Figure 5 shows the Rth(j-a) dependency of a SMB package over copper plane area. Figure 5. Junction-to-ambient thermal resistance over copper plane area of SMB package Rth(j-a) (°C/W) 200 180 160 140 120 100 80 60 40 Copper surface (cm2) 20 0 0 1 2 3 4 5 6 7 8 9 10 Junction-to-lead thermal resistance (Rth(j-l)) The thermal resistance Rth(j-l) is the heat dissipation capability from the junction surface of the die to the package lead. This parameter is useful for estimating the junction temperature from a measurement of the lead temperature. The designer can determine the lead temperature of the device under application conditions with a fine gauge thermocouple or DocID023949 Rev 2 7/19 STRVS parameters AN4209 infrared camera and calculate the junction temperature using Equation 6. The lead is the most interesting reference point to evaluate accurately the average operating junction temperature Tjavg. The thermal resistance value Rth(j-l) depends only on the package proprieties unlike Rth(j-a). 1.2.2 Transient parameter Transient thermal impedance (ZTH(j-Ref)(tp)) The transient thermal impedance ZTH(j-Ref)(tp) is the temporary variation of thermal resistance from an input power step function up to reaching a stable value as defined Equation 7. lim tp Æ 8 Equation 7 Zth(j-Ref) (tp) = Rth(j-Ref) Transient thermal impedance can be calculated using Equation 8. Equation 8 ZTH( j - Re f ) (t p ) = Tj (t p ) - TRe f PStep Where: ZTH(j-Ref) Junction to reference transient thermal impedance expressed in °C/W. tp Pulse duration of the step power expressed in s. PStep Step power function applied to the die expressed in W. Tj(tp) Junction temperature over the time width, expressed in °C. TRef Temperature of the reference point expressed in °C. Junction to ambient, ZTH(j-a) and junction to lead, ZTH(j-l) transient thermal impedance curves are provided in the datasheet. However ZTH(j-l) should be preferred to evaluate the peak junction temperature to get a better assessment. Thus from Equation 8, the dynamic change in temperature over the time can be determined using Equation 9 Tj (t p ) = PStep · ZTH ( j - l ) (t p ) + Tl The transient thermal impedance diagram provides a quick and simple method to estimate the rise of junction temperature under transient conditions. Figure 6 below illustrates transient thermal impedance diagrams of the SMB package. Note that thermal impedances increase until they reach their asymptotic limit corresponding to their thermal resistance Rth(j-l) and Rth(j-a). 8/19 DocID023949 Rev 2 AN4209 STRVS parameters Figure 6. Thermal impedance variation of SMB package versus the pulse duration 1000 100 °C/W Recommended pad layout Printed circuit board FR4, copper thickness = 35 µm ZTH(j-a) 10 ZTH(j-l) 1 0.1 0.01 tp(s) 0.001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 10000 When the STRVS works under repetitive mode operation, the peak junction temperature Tjpeak must be below absolute rating Tjmax specified in the datasheet. For an infinite pulse train case, Tjpeak is expressed as shown in Equation 10: Equation 10 Tj peak(t p ) = PD · RTH ( j - l ) + ( PStep - PD ) · ZTH ( j - l ) (t p ) + Tl Note: The background average power PD has been subtracted, to avoid counting this effect twice in calculating temperature rise. In power conversion applications, two main cases occur. The time constants of the transient thermal impedance thermal must be considered regarding the switching period tSW in the application. Figure 7 illustrates the impact of operating frequency on the ripple temperature. The time constant of a thermal system is dependent on its transient thermal impedance curve. A sufficient estimation of thermal constant can be easily made from the simple RC thermal model representing the Zth(j-Ref) curve. Equation 11 Zth(j-Ref)(t) = Rth(j-Ref) · (1 - e (-t/tau) ) Equation 12 tau = -t(ln(1-Zth(t)/Rth) Equation 12 applied to Figure 6 for an application working switching period tsw, around 10 µs, gives tau much greater than tsw due to the low value of Zth(@ 10 µs) before the Rth value. In this case the junction temperature rises and falls with a negligible dynamic temperature Tj near Tjavg as shown in Figure 7. Since Tjpeak Tjavg, only the average junction temperature evaluation is needed using Equation 6. Notice that this case represents 90% of switch mode power supply applications (FSW > 20 kHz). Under these conditions, pulse widths are generally in the range of some tens to hundreds of nanoseconds and pulses may be viewed as a short block of constant power PSTEP, sustaining the junction temperature. DocID023949 Rev 2 9/19 STRVS parameters AN4209 When tSW is not negligible regarding the thermal of the device (Figure 7), average temperature verification is not enough to ensure that the junction temperature of the die remains within specifications. Consequently, the instantaneous peak junction temperature Tjpeak must be verified using Equation 10 Figure 7. Switching frequency effect on the junction temperature variation in repetitive mode. t sw >> τthermal t sw << τthermal ΔTj Tjmax Tjmax Tjpeak Tj(t) Tjpeak Δ?Tj Tj(t) Tjavg Tjavg t t P(t) P(t) Ppeak PStep Ppeak PStep PD t tp t SW 10/19 tSW = switching period tp = pulse width DocID023949 Rev 2 tp t SW PD t AN4209 2 General design procedure General design procedure This section presents general design guidelines. Figure 8 shows a simplified schematic where an STRVS device is inserted between the noisy source and the vulnerable device to protect it against repetitive transient surges. Figure 8. Basic STRVS protection circuit Noisy source Vsurge VCL IPP 2.1 Protection IPP VPmax Voperationmax Vsurge VCL Device under test t Key Rules To ensure that absolute ratings are not exceeded, designers have to evaluate the worst case conditions in the application to select the suitable device. The three criteria shown in Table 2 are required: Table 2. Basic design criteria 2.2 Criteria Application conditions Device parameter Be invisible under operating voltage (standby). Leakage current should 1 have no effect on normal circuit performance Maximum operating voltage, Voperationmax Stand-off voltage Voperationmax < VRM Protect device against repetitive electrical overstress by instantly 2 clamping spike voltages to a nondestructive level. Voltage protection, VPmax Clamping voltage VCLtyp (IPPmax;125 °C) < VPmax Maintain the junction temperature within specifications to guarantee a 3 high reliability. This point must be obeyed in transient and steady state working mode. Repetitive current, IPPmax Power dissipation, Tj < Tjmax Transil selection process This proposed methodology is based on a systematic approach to match the general case study. The device selection uses a recursive process. Steps are described below: DocID023949 Rev 2 11/19 General design procedure 2.2.1 AN4209 Step 1: STRVS preselection In the absence of transient voltages, the STRVS should act as an open circuit and should have no effect on normal circuit performance (Criteria 1 in Table 2). The preselection begins with VRM parameters where the leakage current will not exceed 1 µA @ 25 °C when Voperationmax is applied. Then, all STRVS having a VBR > VPmax can be removed from consideration to ensure the circuit protection (Criteria 2 Table 2). Note that VPmax represents the admissible clamping voltage which includes a safety margin generally 15% below the absolute rating of the end-component to protect. At this time, several STRVS may cover both criteria 1 and criteria 2. In the first pass using the highest rated voltage available is recommended. This generally minimizes the standby consumption and power dissipation. The smallest package available is primarily chosen to optimize the solution from the thermal point of view with minimum loop numbers. 2.2.2 Step 2: Clamping voltage assessment The designer has to check the clamping voltage VCLtyp(IPPmax;125°C) (Criteria 2 Table 2) by using curves provided in the datasheet. This point has to be verified in the worst case application and thus the current IPPmax flowing though the device must be identified. Under steady state operation, we recommend that designers should ensure that Tjpeak should not exceed 125 °C. This step requires a current measurement because the STRVS current is generally unknown. If so, it is recommended the designer starts the evaluation with the highest pre-selected rated voltage and with the biggest package available to avoid a thermal failure. When the peak current can be predicted or simulated, the clamping voltage can be directly calculated. While the VCLtyp(IPPmax;125 °C) > VPmax is true (Criteria 2 Table 2), the rated voltage is decreased by recursion until the lowest pre-selected STRVS can be identified at a cost of a higher power dissipation and quiescent current consumption. 2.2.3 Step 3: Dissipated power calculation Power dissipation assessment is requested to evaluate the maximum and average junction temperature of the device. Power dissipation is performed with the VCLtyp characteristic given at 125°C overestimating losses. By using Equation 6 and/or Equation 10, operating junction temperature of the device can be computed. In case of Tjpeak < 125°C, the result corresponds to the smallest package solution compatible with design rules. Otherwise, the user should return to step 1 or 2 to go over the available electrical characteristics and package performances of the device. When dissipated power is too high, a second option is to use STRVS in serial configuration in order to spread the heat flow between packages. 2.2.4 Step 4: In-situ test In the last step, we recommend checking the application to ensure that all criteria are respected with the final selected device. This step requires a current waveform and lead temperature measurement to calculate the actual junction temperature and the clamping voltage. 12/19 DocID023949 Rev 2 AN4209 2.3 General design procedure Transil selection flowchart Figure 9 summarizes the selection procedure: Figure 9. Device selection process overview Application conditions Application conditions : : operationmax; ;VVPmax; ; TTambmax VVoperationmax Pmax ambmax Theoretical VRM (25°C) > Voperationmax VBR (25°C) < V Pmax Select the smallest package Select the smallest package available. available. Use Use bigger bigger package package Selectthe thehighest highestrated ratedvoltage voltage Select to reduce both Transil power to reduce both Transil power dissipation&&quiescent quiescentcurrent.. current.. dissipation Decrease the voltage rating Voperationmax Maximum operating voltage across the device in standby mode (negligible leakage current consumption). VPmax Maximum clamping voltage to not exceed in application. VCLtyp(IPPmax ; 125°C) Typical clamping voltage versus peak current flowing though the device and its operating junction. NO VCLtyp (IPPmax ;125°C) < V Pmax YES Power losses calculation Power losses calculation Tj evaluation Tj evaluation NO Tj < 125°C YES Experimental Checkifif33criteria criteriaare arerespected respected Check with the final device in practice. with the final device in practice. Requested measurements IPP Æ V CLtyp Tlead Æ T jpeak < 125°C Design safe Design safe DocID023949 Rev 2 13/19 Design example 3 AN4209 Design example The case study corresponds to protection of a MOSFET device. Because of stray inductance in series with the power switch STP50NF25, fast transient over voltages appear across it at each switching period. A STRVS device is therefore inserted in parallel to protect the switch. Applications conditions are shown in Table 3: Table 3. Worst case application conditions (maximum values) 3.1 Voperationmax FSW IPP Tambmax VDSS Package 120 V 100 kHz Unknown 50 °C 250 V SMD STRVS pre-selection Considering a safety margin of 15% VPmax is given by Equation 13. Equation 13 VP max = VDSS · 0.85 = 212 V Considering the criteria 1 and 2, several STRVS can be pre-selected as shown in Table 4 Table 4. Possible pre-selected devices VRMmax @ VBRmax @ Tmax @ [1 µA, 25 °C] [1 mA, 25 °C] [1 mA] STRVS182X02F/C 128 V 158 V 10.8·10-4/°C DO-201/SMC STRVS185X02B/E 128 V 158 V 10.8·10-4/°C SMB/DO-15 189 V 10.8·10-4/°C DO-201 189 V -4/°C Order code STRVS222X02F STRVS225X02E 3.2 154 V 154 V 10.8·10 Package DO-15 Clamping voltage assessment Since the application requires a surface mount package (SMD) protection, STRVS185X02B is primarily selected. Based on the methodology, the current will be sensed in application with a DO-15 package to minimize the thermal issue. Current and voltage waveforms across the device are shown below during the clamping time. 14/19 DocID023949 Rev 2 AN4209 Design example Figure 10. Current and voltage waveforms across the STRVS185X02B. VDSS 250V 200mA/DIV 30V/DIV 50ns/DIV 15% of safety margin VPmax VCLtyp 212V 180V given in datasheet (500mA ; 125 °C) VCL Voperationmax 120V IPPmax CLpeak = 500mA IPP CL PStep 0A, 0V tp = 75ns Let’s verify with the current measurement and device features that: VCLtyp(500 mA;125°C) < VPmax. From Figure 11,VCLtyp (500 mA;125°C) 181 V Figure 11. Clamping voltage characteristics of STRVS185X02B provided in datasheet. 2.0 IPP (A) 125 °C 1.6 1.2 0.8 [0.5A; 180.5 V] RD = 5 Ω 0.4 VCLtyp (V) 0.0 170 175 VCL0 = 178 V 180 185 190 Since VCLtyp (500 mA;125°C) < VPmax, STRVS185X02B could be selected. DocID023949 Rev 2 15/19 Design example 3.3 AN4209 Dissipated power calculation Let’s verify that Tjpeak < 125 °C, and VCLtyp(500 mA; Tjavg) < VPmax. 3.3.1 Power losses calculation: The curve is fitted in operating region to find RD, VCL0 (see Figure 11): From Equation 4, RD equals: RD (400mA;600 mA;125 °C) = RD = 5 Ω From Equation 5, VCL0 is calculated as: VCL0 (400 mA ; 600 mA ;125°C) = VCL0 = 178 V The dissipated power during the clamping time is now calculated: tp PStep = PStep = 1 VCL (t ) · I PP (t )dt t p ∫0 I PPmax · (3·VCL0 + 2 · I PPmax · RD) 6 PStep = 44.9 W The average power dissipation PD is calculated: PD = t p · FSW · Pstep PD = 0.34 W 3.3.2 Peak and average junction temperature calculation: Considering the low Tj, due to the low value of tsw, before the thermal cst time thermal of the device (see Section 1.2.2), the peak and average junction temperature are considered identical: From Equation 5, Tjpeak equals: Tj peak = RTH ( j - a) · PD + Tambmax Tj peak = 112 °C VCLtyp(IPPmax; 112°C) < VCLtyp(IPPmax; 125°C) < VPmax, STRVS185X02B is selected. The power switch and STRVS should be both safe. 3.4 In-situ verification The designer verifies all criteria with the final protection device. Due to neighboring components sharing the same PCB layout in the system, Tjpeak can be estimated more accurately with thermal measurement done from the lead. Table 5 presents measurements results obtained with STRVS. Table 5. Sample measurements 16/19 IPPpeak tp Tj 600 mA 65 ns 116 °C DocID023949 Rev 2 AN4209 Conclusion Using the measurements from Table 5: PStep = 54 W PD = 0.351 W Tj peak = RTH ( j - l ) · PD + Tl = 121 °C VCLtyp ( I PPmax ;121°C) < VCL ( I PPmax ; 125 °C) The component matches the application requirements. 4 Conclusion This application note has presented design guidelines for the new protection device family STRVS dedicated to the repetitive operation mode. The design procedure proposed by STMicroelectronics serves as basis of a quick and efficient design process to offer better protection. Note that this methodology is flexible and can fit a wide range the application requirements (such as safety margin, allowable Tjpeak values…). DocID023949 Rev 2 17/19 Revision history 5 AN4209 Revision history Table 6. Document revision history 18/19 Date Revision Changes 04-Mar-2013 1 Initial release. 05-Sep-2013 2 Updated Figure 1. DocID023949 Rev 2 AN4209 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2013 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com DocID023949 Rev 2 19/19

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