dm00064522

AN4165
Application note
STEVAL-ISA111V1: 12 V / 12 W, 115 kHz non-isolated flyback
By Mirko Sciortino
Introduction
This document describes a 12 V - 1 A power supply set in non-isolated flyback topology
based on the VIPER26, an offline high-voltage converter offered by STMicroelectronics.
The features of the device include:
• 800 V avalanche rugged power section
• PWM operation at 115 kHz with frequency jittering for lower EMI
• Limiting current with adjustable set point
• On-board soft-start
• Safe behavior during a fault condition (overload, short-circuit, open loop)
• Low standby consumption (< 30 mW at VIN = 230 VAC)
The available protections are:
• Thermal shutdown with hysteresis
• Delayed overload (or short-circuit) protection
• Open loop failure protection
All protections employ the auto-restart mode.
Figure 1. STEVAL-ISA111V1 evaluation board
May 2016
DocID023661 Rev 2
1/36
www.st.com
36
Contents
AN4165
Contents
1
Adapter features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4
Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
Testing the board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.1
Typical waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
6
Line/load regulation and output voltage ripple . . . . . . . . . . . . . . . . . . 12
7
Burst mode and output voltage ripple . . . . . . . . . . . . . . . . . . . . . . . . . 14
8
Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
9
Light-load performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
10
Functional check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
11
10.1
Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
10.2
Overload protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
10.3
Feedback loop failure protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Feedback loop calculation guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . 23
11.1
Transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
11.2
Compensation procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
12
Thermal measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
13
EMI measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
14
Board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
15
Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2/36
DocID023661 Rev 2
AN4165
Contents
Appendix A Test equipment and measurement of efficiency
and light load performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
A.1
Measuring input power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
16
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
17
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
DocID023661 Rev 2
3/36
36
Adapter features
1
AN4165
Adapter features
The electrical specifications of the evaluation board are listed in Table 1.
Table 1. Electrical specifications
Symbol
VIN
4/36
Parameter
Input voltage range
Value
[90 VAC - 265 VAC]
VOUT
Output voltage
12 V
IOUT
Max. output current
1A
∆ VOUT_LF
Precision of output regulation
∆ VOUT_HF
High-frequency output voltage ripple
50 mV
TAMB
Max. ambient operating temperature
60 oC
DocID023661 Rev 2
± 5%
AN4165
2
Circuit description
Circuit description
The power supply is set in flyback topology. The complete schematic is given in Figure 2. A
simplified schematic for VOUT ≥12 V and the relevant BOM are given in Figure 3 and in
Table 2 respectively. The input section includes a resistor R1 and an NTC for inrush current
limiting, a diode bridge (D0) and a Pi filter for EMC suppression (C1, L2, C2). The
transformer core is a standard E20. A Transil™ clamp network (D1, D4) is used for leakage
inductance demagnetization. The output voltage value is set simply through the R3-R4
voltage divider between the output terminal and the FB pin, according to the following
formula:
Equation 1
R3 

VOUT = 3.3V ⋅  1 +

 R4 
In fact, the FB pin is the input of an error amplifier and is an accurate 3.3 V voltage
reference. In the schematic the resistor R4 has been split into R4a and R4b in order to allow
better tuning of the output voltage value. The compensation network is connected between
the COMP pin (which is the output of the error amplifier) and the GND pin and consists of
C7, C8 and R7. The output rectifier D3 has been selected according to the calculated
maximum reverse voltage, forward voltage drop and power dissipation and is a power
Schottky. A resistor has been connected between the LIM and GND pins in order to reduce
the IDLIM to the value needed to supply the required output power, limiting the stress on the
power components.
At power-up the DRAIN pin supplies the internal HV startup current generator which
charges the VDD capacitor, C4, up to VDDon. At this point, the Power MOSFET starts
switching, the generator is turned off and the IC is powered by the energy stored in C4. If the
nominal value of VOUT exceeds the VDDcson threshold of the VIPER26 by a small signal
diode forward voltage drop, the IC can be supplied directly from the output, selecting jumper
J2 which is shown as open in Figure 2 (ie. no selection of either jumper J1 or J2 is
indicated). In this case jumper J1 is open because the auxiliary winding of the transformer is
not needed and the schematic can be simplified, as shown in Figure 3. Since
VDDcsonmax = 11.5 V, the minimum value of VOUT allowing this connection is 12 V. If
VOUT < 12 V, the VIPER26 must be supplied through the auxiliary winding of the transformer
(J1 selected, J2 open in Figure 2), delivering to the VDD pin a voltage higher than VDDcson.
The voltage generated by the auxiliary winding increases with the load on the regulated
output. An external clamp (D5, R1) can be added in this case, in order to avoid exceeding
the VDD operating range.
The figures and measurements in this document refer to a case in which VDD is supplied
from the output, i.e. to the simplified schematic shown in Figure 3.
DocID023661 Rev 2
5/36
36
6/36
DocID023661 Rev 2
D5
R1
AC IN
AC IN
C6
F
R4b
R4a
R3
NTC
+
t
C4
J1
C5
-
R7
C7
D0
FB
R2
COMP
C8
+
+
LIM
R5
CONTROL
VDD
C1
L2
D2
C2
GND
DRAIN
+
D1
D4
J2
T1
IC1
VIPER26
2
1
3
C9
5
8,9
6,7
D6
D3
C10
+
C11
+
L1
C12
+
GROUND
VOUT
AM11547v1
Circuit description
AN4165
Figure 2. Application schematic - complete
C6
AC IN
AC IN
DocID023661 Rev 2
R4b
R4a
R3
F
C4
+
NTC
C5
t
-
R7
C7
C8
D0
COMP
FB
+
+
LIM
R5
CONTROL
VDD
C1
L2
C2
GND
DRAIN
+
D4
D1
D6
VIPER26
3
1
3
5
T2
8,9
6,7
D3
C10
+
C11
+
GROUND
VOUT
AM11548v1
AN4165
Circuit description
Figure 3. Application schematic - simplified for VOUT ≥ 12 V
7/36
36
Bill of material
3
AN4165
Bill of material
Table 2. Bill of material (simplified schematic)
Reference
Part
NTC
2.2 Ω NTC
Thermistor, S236 series
F
T2A 250 V
2 A, 250 VAC fuse, TR5 series
Wickmann
C1
10 µF, 400 V NHG series electrolytic capacitor
Panasonic
C2
22 µF, 35 V SMG series electrolytic capacitor
Panasonic
C4
2.2 µF, 63 V electrolytic capacitor
C5
100 nF, 50 V ceramic capacitor
C6
2.2 nF, 50 V ceramic capacitor
C7
100 nF, 50 V ceramic capacitor
C8
2.2 nF, 50 V ceramic capacitor
C9
Description
Manufacturer
EPCOS
Not mounted
C10
1000 µF, 16 V ultra low ESR electrolytic capacitor ZL series
Rubycon
C11
680 µF, 16 V ultra low ESR electrolytic capacitor ZL series
Rubycon
C12
Not mounted
D0
DF06M
D1
STTH1L06
D2
Not mounted
D3
1 A - 600 V diode bridge
Vishay
1 A - 600 V ultrafast diode
ST
STPS3150
3 A-150 V power Schottky (output diode)
ST
D4
1.5KE300A
Transil
ST
D5
Not mounted
D6
1N4148
R1
Not mounted
R2
Not mounted
Small signal diode
R3
47 k Ω 1% 1/4 W resistor
R4a
15 k Ω 1% 1/4 W resistor
R4b
2.7 k Ω 1% 1/4 W resistor
R5
27 k Ω 1/4 W resistor
R7
33 k Ω 1/4 W resistor
L1
Short-circuit
L2
RFB0807-102
1335.0089
Input filter inductor (L = 1 mH, ISAT = 0.3 A; DCRmax = 3.4 Ω)
115 kHz switch mode transformer
Fairchild
Coilcraft
Magnetica
T1
750810131 Rev. 6A Flyback transformer
IC1
8/36
VIPER26HN
High-voltage 115 kHz PWM
DocID023661 Rev 2
Wurth
ST
AN4165
Bill of material
Table 2. Bill of material (simplified schematic) (continued)
Reference
Part
Description
J1
Not mounted
Jumper
J2
Short-circuit
Jumper
DocID023661 Rev 2
Manufacturer
9/36
36
Transformer
4
AN4165
Transformer
The characteristics of the transformer are listed in the table below.
Table 3. Transformer characteristics
Parameter
Value
Manufacturer
Magnetica
Part number
1335.0089
Test conditions
Primary inductance
1.8 mH ±15%
Measured at 1 kHz, TAMB = 20 oC
Leakage inductance
3.12%
Measured at 10 kHz, TAMB = 20 oC
Primary to secondary turn ratio (3 - 5)/(6,7- 8,9)
5.8 ± 5%
Measured at 10 kHz, TAMB = 20 oC
Primary to auxiliary turn ratio (3 - 5)/(1 - 2)
5.8 ± 5%
Measured at 10 kHz, TAMB = 20 oC
The figures below show the size, pinout, and pin distances (in mm) as well as the electrical
diagram of the transformer.
Figure 4. Transformer size and pin diagram,
bottom view
Figure 5. Transformer size, side view
AM13359v1
Figure 6. Transformer, pin distances
AM13360v1
Figure 7. Transformer, electrical diagram
AM13361v1
10/36
DocID023661 Rev 2
AM11552v1
AN4165
Testing the board
5
Testing the board
5.1
Typical waveforms
Drain voltage and current waveforms in full load condition are shown for the two nominal
input voltages in Figure 8 and 9, and for minimum and maximum input voltage in Figure 10
and 11 respectively.
Figure 8. Drain current and voltage at VIN = 115 Figure 9. Drain current and voltage at VIN = 230
VAC, full load
VAC, full load
AM13362v1
AM13363v1
Figure 10. Drain current and voltage at VIN = 90 Figure 11. Drain current and voltage at VIN = 265
VAC, full load
VAC, full load
AM13364v1
DocID023661 Rev 2
AM13365v1
11/36
36
Line/load regulation and output voltage ripple
6
AN4165
Line/load regulation and output voltage ripple
The output voltage of the board has been measured in different line and load conditions.
The results are shown in Table 4. The output voltage is practically unaffected by the line
condition.
Table 4. Output voltage line-load regulation
VOUT[V]
VIN [VAC]
No load
50% load
75% load
100% load
90
11.94
11.91
11.92
11.92
115
11.94
11.91
11.92
11.92
150
11.94
11.92
11.91
11.91
180
11.94
11.92
11.91
11.91
230
11.94
11.92
11.91
11.91
265
11.94
11.92
11.91
11.91
Figure 13. Load regulation
12.1
12.1
12
12
VOUT[V]
VOUT[V]
Figure 12. Line regulation
11.9
0
11.9
90
25%
11.8
50%
115
11.8
75%
230
100%
11.7
80
105
130
155 180
VIN[V AC ]
205
230
255
265
11.7
0
AM13366v1
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Iout[A]
1
1.1
AM13367v1
The ripple at the switching frequency superimposed at the output voltage has also been
measured and the results are given in Table 5.
Table 5. Output voltage ripple at half and full load
VOUT [mV]
VIN [VAC]
12/36
Half load
Full load
90
17
23
115
16
21
230
18
25
265
17
24
DocID023661 Rev 2
AN4165
Line/load regulation and output voltage ripple
Figure 14. Output voltage ripple at
VIN = 115 VAC, full load
Figure 15. Output voltage ripple at
VIN = 230 VAC, full load
AM13368v1
DocID023661 Rev 2
AM13369v1
13/36
36
Burst mode and output voltage ripple
7
AN4165
Burst mode and output voltage ripple
When the converter is lightly loaded, the COMP pin voltage decreases. As it reaches the
shutdown threshold, VCOMPL (1.1 V, typical), the switching is disabled and energy is no
longer transferred to the secondary side. So, the output voltage decreases and the
regulation loop makes the COMP pin voltage increase again. As it rises 40 mV above the
VCOMPL threshold, the normal switching operation is resumed. This results in a controlled
on/off operation (referred to as “burst mode”) as long as the output power is low enough to
require a turn-on time lower than the minimum turn-on time of the VIPER26. This mode of
operation keeps the frequency-related losses low when the load is very light or
disconnected, making it easier to comply with energy-saving regulations. The figures below
show the output voltage ripple when the converter is not (or lightly) loaded and supplied with
115 VAC and with 230 VAC respectively.
Figure 16. Output voltage ripple at
VIN = 115 VAC, no load
Figure 17. Output voltage ripple at
VIN = 230 VAC, no load
AM13370v1
Figure 18. Output voltage ripple at
VIN = 115 VAC, IOUT = 25 mA
AM13371v1
Figure 19. Output voltage ripple at
VIN = 230 VAC, IOUT = 25 mA
AM13372v1
14/36
DocID023661 Rev 2
AM13373v1
AN4165
Burst mode and output voltage ripple
Table 6 shows the measured value of the burst mode frequency ripple measured under
different operating conditions. The ripple in burst mode operation is very low.
Table 6. Output voltage ripple at no (or light) load
VOUT [mV]
VIN [VAC]
No load
25 mA load
90
2
3
115
2
5
230
2
6
265
3
6
DocID023661 Rev 2
15/36
36
Efficiency
8
AN4165
Efficiency
Active mode efficiency is defined as the average of the efficiencies measured at 25%, 50%,
75% and 100% of maximum load, at nominal input voltage (VIN = 115 VAC and
VIN = 230 VAC).
External power supplies (the power supplies which are housed separately from the end-use
devices they are powering) need to comply with the Code of Conduct (version 4.0) "Active
mode efficiency" criterion, which requires an active mode efficiency higher than 77.7% for a
power throughput of 12 W.
Another standard to be applied to external power supplies in the coming years is the DOE
(Department of Energy) recommendation, whose active mode efficiency requirement for the
same power throughput is 82.96%.
The average efficiencies of the board at 115 VAC (83.33%) and at 230 VAC (81.34%) are
represented by dotted lines, and, along with the above limits, show that the STEVALISA111V1 evaluation board is compliant with both standards at 115 VAC and with the Code
of Conduct only at 230 VAC (refer to Figure 20 below).
In the same figure the efficiency at 25%, 50%, 75% and 100% of maximum load for both
input voltages is also shown.
Figure 20. Active mode efficiency of the evaluation board in comparison to energy
efficiency standards
85
83
DOE limit
eff [%]
81
79
CoC4 limit
77
115
230
av @ 115Vac
av @ 230Vac
75
73
0.2
16/36
0.4
0.6
0.8
Iout [% I OUT ]
DocID023661 Rev 2
1
AM13375v1
AN4165
9
Light-load performance
Light-load performance
The input power of the converter has been measured in no load condition for different input
voltages and the results are given in Table 7.
Table 7. No load input power
VIN [VAC]
PIN [mW]
90
13.4
115
14.4
150
16.1
180
18.0
230
22.2
265
24.9
In version 4.0 of the Code of Conduct the power consumption of the power supply when it is
not loaded is also considered. The criteria for compliance are given in the table below:
Table 8. Energy consumption criteria for no load
Nameplate output power (Pno)
Maximum power in no load for AC-DC
EPS
0 W ≤ Pno ≤ 50 W
< 0.3 W
50 W < Pno < 250 W
< 0.5 W
The power consumption of the STEVAL-ISA111V1 board is about ten times lower than the
Code of Conduct (version 4) limit. Even if this performance seems to be disproportionately
better than the requirements, it is worth noting that often AC-DC adapter or battery charger
manufacturers have very strict requirements about no load consumption and when the
converter is used as an auxiliary power supply, the line filter is often the main line filter of the
entire power supply which considerably increases standby consumption.
Even if the Code of Conduct (version 4) program does not have other requirements
regarding light load performance, in order to give more information the input power and
efficiency of the evaluation board in two other light load cases is also shown. Table 9 and
Table 10 show the performance when the output load is 25 mW and 50 mW respectively.
Table 9. Light load performance at POUT = 25 mW
VIN [VAC]
POUT [mW]
PIN [mW]
Efficiency (%)
90
25
44.9
55.7
115
25
46.3
54.0
150
25
49.1
50.9
180
25
51.5
48.5
DocID023661 Rev 2
17/36
36
Light-load performance
AN4165
Table 9. Light load performance at POUT = 25 mW
VIN [VAC]
POUT [mW]
PIN [mW]
Efficiency (%)
230
25
55.0
45.5
265
25
59.0
42.4
Table 10. Light load performance at POUT = 50 mW
VIN [VAC]
POUT [mW]
PIN [mW]
Efficiency (%)
90
50
76.7
65.2
115
50
78.5
63.7
150
50
82.0
61.0
180
50
85.0
58.8
230
50
90.0
55.6
265
50
94.0
53.2
The input power vs. input voltage for no load and light load condition (Table 7, 9 and 10) are
shown in the figure below.
Figure 21. PIN vs. VIN at no load and light load
200
0
175
25mW
Pin [mW]
150
50mW
125
100
75
50
25
0
80
105
130
155
180
VIN [VAC]
205
230
255
AM11570v1
It’s possible to have several criteria to measure the standby or light load performance of a
converter. One criterion is the measurement of the output power when the input power is
equal to one watt. In Table 11 the output power needed to have 1 W of input power in
different line conditions is given. Figure 22 shows the output power corresponding to PIN = 1
W for different values of the input voltage.
18/36
DocID023661 Rev 2
AN4165
Light-load performance
Table 11. POUT @ PIN = 1 W
VIN [VAC]
PIN (W)
POUT (W)
Efficiency (%)
90
1
0.788
78.8
115
1
0.781
78.1
150
1
0.76
76.0
180
1
0.74
74.0
230
1
0.70
70.0
265
1
0.686
68.6
Figure 22. Efficiency vs. VIN at PIN = 1 W
90
85
80
eff [%]
75
70
65
60
55
50
80
110
140
170
200
VIN [V AC ]
230
260
AM13378v1
Another requirement (EuP lot 6) is that the input power should be less than 500 mW when
the converter is loaded with 250 mW. The converter can satisfy even this requirement, as
shown in Figure 23.
Figure 23. PIN at POUT = 0.25 W
0.5
0.45
PIN [W]
0.4
0.35
0.3
0.25
80
110
140
170
Vin[V]
DocID023661 Rev 2
200
230
260
AM11571v2
19/36
36
Functional check
10
Functional check
10.1
Soft-start
AN4165
At startup the current limitation value reaches IDLIM after an internally set time, tSS, whose
typical value is 8.5 msec. This time is divided into 16 time intervals, each corresponding to a
current limitation step progressively increasing. In this way the drain current is limited during
the output voltage increase, therefore reducing the stress on the secondary diode. The softstart phase is shown in Figure 24 and 25.
Figure 24. Soft-start at startup
Figure 25. Soft-start at startup (zoom)
AM13379v1
10.2
AM13380v1
Overload protection
In case of overload or short-circuit (see Figure 26), the drain current reaches the IDLIM
value (or the one set by the user through the RLIM resistor). Every cycle that this condition
is met, a counter is incremented. If the fault is maintained continuously for the time tOVL
(50 msec typical, set internally), the overload protection is tripped, the power section is
turned off and the converter is disabled for a tRESTART time (1 s typical). After this time has
elapsed, the IC resumes switching and, if the short is still present, the protection occurs
indefinitely in the same way (Figure 27). This ensures restart attempts of the converter with
low repetition rate, so that it works safely with extremely low power throughput and avoids
overheating of the IC in case of repeated overload events.
Moreover, every time the protection is tripped, the internal soft-start function (Figure 25) is
implemented, in order to reduce the stress on the secondary diode.
After the short removal, the IC resumes working normally. If the short is removed during tSS
or tOVL, i.e. before the protection is tripped, the counter is decremented on a cycle-by-cycle
basis down to zero and the protection is not tripped.
If the short-circuit is removed during tRESTART, the IC waits for the tRESTART period to elapse
before resuming switching (Figure 29).
20/36
DocID023661 Rev 2
AN4165
Functional check
Figure 26. Output short-circuit applied:
OLP tripping
Figure 27. Output short-circuit maintained: OLP
steady-state
Output is shorted here
tRESTART
Normal
operation
AM11574v1
Figure 28. Output short-circuit maintained: OLP
steady-state, zoom
tSS
AM11575v1
Figure 29. Output short-circuit removal and
converter restart
tOVL
tRESTART
Normal
operation
Output short is
removed here
AM13381v1
10.3
AM11577v1
Feedback loop failure protection
When the loop is broken (R4 = R4a + R4b shorted or R3 open), the output voltage VOUT
increases and the VIPER26 runs at its maximum current limitation. The VDD pin voltage
increases as well, because it is linked to the VOUT voltage either directly or through the
auxiliary winding.
If the VDD voltage reaches the VDDclamp threshold (23.5 V min.) in less than 50 msec, the IC
is shut down by the open loop failure protection (see Figure 30 and 31), otherwise by OLP,
as described in the previous section. The breaking of the loop has been simulated by
DocID023661 Rev 2
21/36
36
Functional check
AN4165
shorting the low-side resistor of the output voltage divider, R4 = R4a + R4b. The same
behavior can be caused by opening the high-side resistor, R3.
The protection acts in auto-restart mode with tRESTART = 1 s (Figure 31). When the fault is
removed, normal operation is restored after the last tRESTART interval has been completed
(Figure 33).
Figure 30. Feedback loop failure protection:
Figure 31. Feedback loop failure protection:
tripping
steady-state
Fault is applied here
VDD reaches VDDCLAMP
< tOVL
Normal
operation
tRESTART
AM11578v1
Figure 32. Feedback loop failure protection:
steady-state, zoom
AM11579v1
Figure 33. Feedback loop failure removal:
converter restart
Fault is removed here
tRESTART
Normal
operation
< tOVL
AM11580v1
22/36
DocID023661 Rev 2
AM11581v1
AN4165
Feedback loop calculation guidelines
11
Feedback loop calculation guidelines
11.1
Transfer function
The set PWM modulator + power stage is indicated with G1(f), while C(f) is the “controller”,
i.e. the network which is in charge of ensuring the stability of the system.
Figure 34. Control loop block diagram
AM11582v1
The mathematical expression of the power plant G1(f) is the following:
Equation 2
j ⋅2⋅π ⋅ f
j⋅ f
VOUT ⋅ (1 +
)
VOUT ⋅ (1 +
)
∆VOUT
z
fz
G 1 (f) =
=
=
j ⋅ 2 ⋅π ⋅ f
j⋅ f
∆I pk
Ipkp ( fsw,Vdc) ⋅ (1 +
) Ipkp ( fsw, Vdc ) ⋅ (1 +
)
p
fp
where VOUT is the output voltage, Ipkp is the primary peak current, fp is the frequency of the
pole due to the output load:
Equation 3
fp =
1
π ⋅ C OUT ·(R OUT + 2ESR)
and fz the frequency of the zero due to the ESR of the output capacitor:
Equation 4
fz =
1
2 ⋅π ⋅ C OUT ·ESR
DocID023661 Rev 2
23/36
36
Feedback loop calculation guidelines
AN4165
The mathematical expression of the compensator C(f) is:
Equation 5
C(f )=
∆I pk
∆V OUT
=
C0
⋅
H COMP
1+
f ⋅j
fZc

f ⋅j
2 ⋅ π ⋅ f ⋅ j ⋅ 1 +

fPc 

where (with reference to the schematic of Figure 2):
Equation 6
C0 = −
Gm
R4
⋅
C 7 + C 8 R3 + R 4
Equation 7
fZc =
1
2 ⋅ π ⋅ R7 ⋅ C7
Equation 8
fPc =
C7 + C 8
2 ⋅ π ⋅ R7 ⋅ C7 ⋅ C8
are to be chosen with the purpose to ensure the stability of the overall system. Gm = 2 mA/V
(typical) is the VIPER26 transconductance.
11.2
Compensation procedure
The first step is to choose the pole and zero of the compensator and the crossover
frequency, for instance:
•
fZc = fp/2
•
fPc = fz
•
fcross = fcross_sel ≤ fsw/10.
G1(fcross_sel) can be calculated from Equation 2 and, being by definition
|C(fcross_sel)*G1(fcross_sel)|= 1, C0 can be calculated as follows:
Equation 9
2 ⋅ π ⋅ fcross _ sel ⋅ j ⋅ 1 +
C0 =
1+
24/36
fcross _ sel ⋅ j
fPc
fcross _ sel ⋅ j
fZc
DocID023661 Rev 2
⋅
HCOMP
G1( fcross _ sel )
AN4165
Feedback loop calculation guidelines
At this point the Bode diagram of G1(f) * C(f) can be plotted, in order to check the phase
margin for the stability. If the margin is not high enough, another choice should be made for
fZc, fPc and fcross_sel, and the procedure repeated. When the stability is ensured, the next
step is to find the values of the schematic components, which can be calculated using
Equation 1, 6, 7, 8, 9 as follows:
Equation 10
R3
R4 = -----------------------V OUT
-------------- – 1
3.3V
Equation 11
C8 =
fZc Gm
R4
⋅
⋅
fPc C 0 R 4 + R 3
Equation 12
 fPc 
C7 = C8 ⋅ 
− 1
 fZc 
Equation 13
R7 =
C 7 + C8
2 ⋅ π ⋅ fPc ⋅ C7 ⋅ C8
DocID023661 Rev 2
25/36
36
Thermal measurements
12
AN4165
Thermal measurements
A thermal analysis of the board at full load condition,@ TAMB = 25 °C has been performed
using an IR camera. The worst case is VIN = 85 VAC, but the nominal input voltage cases
(VIN = 115 VAC and VIN = 230 VAC) have also been considered. The results are shown in
Figure 35, 36, 37 and 38 and summarized in Table 12.
Figure 35. Thermal map at TAMB = 25 °C,
VIN = 85 VAC, full load
Figure 36. Thermal map at TAMB = 25 °C,
VIN = 115 VAC, full load
AM13383v1
AM13382v1
Figure 37. Thermal map at TAMB = 25 °C,
VIN = 230 VAC, full load
Figure 38. Thermal map at TAMB = 25 °C,
VIN = 265 VAC, full load
AM13385v1
AM13384v1
Table 12. Temperature of key components at VIN = 85 VAC /230 VAC, full load (TAMB = 25 °C)
T [°C]
Point
26/36
Reference
VIN = 85 VAC
VIN = 265 VAC
A
82.4
76.6
VIPER26
B
68.3
73.3
Transformer
C
69.1
67.0
Output diode
D
55.4
53.0
Clamping diode
E
24.8
24.9
Room temperature
DocID023661 Rev 2
AN4165
13
EMI measurements
EMI measurements
A pre-compliance test to EN55022 (Class B) European normative has been performed
using an EMC analyzer and an LISN. First of all, a measurement of the background noise
(board disconnected from the mains) was performed and is shown in Figure 39.
Then the peak and average EMC measurements at 115 VAC/full load and 230 VAC/full load
were performed and the results are shown in Figure 40, 41, 42 and 43.
Figure 39. Background noise measurement
AM13386v1
Figure 40. Peak measurement at 115 VAC/full load
AM13387v1
DocID023661 Rev 2
27/36
36
EMI measurements
AN4165
Figure 41. Peak measurement at 230 VAC/full load
AM13388v1
Figure 42. Average measurement at 115 VAC/full load
AM13389v1
Figure 43. Average measurement at 230 VAC/full load
AM13390v1
28/36
DocID023661 Rev 2
AN4165
14
Board layout
Board layout
The board layout is shown in the figure below.
Figure 44. Bottom layer & top overlay
DocID023661 Rev 2
29/36
36
Conclusions
15
AN4165
Conclusions
The VIPER26 allows a simple design of a non-isolated converter with few external
components. In this document a non-isolated flyback has been described and
characterized. Special attention has been given to light load performance, confirmed as very
good by bench analysis. Efficiency has been compared to the requirements of the Code of
Conduct (version 4) for external AC-DC power supplies with very good results.
30/36
DocID023661 Rev 2
AN4165
Test equipment and measurement of efficiency and light load performance
Appendix A
Test equipment and measurement of
efficiency and light load performance
The converter input power has been measured using a wattmeter. The wattmeter measures
simultaneously the converter input current (using its internal ammeter) and voltage (using its
internal voltmeter). The wattmeter is a digital instrument so it samples the current and
voltage and converts them to digital forms. The digital samples are then multiplied giving the
instantaneous measured power. The sampling frequency is in the range of 20 kHz (or higher
depending on the instrument used). The display provides the average measured power,
averaging the instantaneous measured power in a short period of time (1 sec typ.).
Figure 45 shows how the wattmeter is connected to the UUT (unit under test) and to the AC
source and the wattmeter internal block diagram.
Figure 45. Connections of the UUT to the wattmeter for power measurements
Switch
1
WATT METER
2
U.U.T
(Unit Under test)
Voltmeter
AC
SOURCE
+
V
Multiplier
A
X
Ammeter
INPUT
OUTPUT
AVG
DISPLAY
AM11590v1
An electronic load has been connected to the output of the power converter (UUT), allowing
the converter load current to be set and measured, while the output voltage has been
measured by a voltmeter. The output power is the product between load current and output
voltage. The ratio between the output power, calculated as previously stated, and the input
power, measured by the wattmeter, is the converter’s efficiency, which has been measured
in different input/output conditions.
A.1
Measuring input power
With reference to Figure 45, the UUT input current causes a voltage drop across the
ammeter’s internal shunt resistance (the ammeter is not ideal as it has an internal
resistance higher than zero) and across the cables connecting the wattmeter to the UUT.
If the switch of Figure 45 is in position 1 (see also the simplified scheme of Figure 46), this
voltage drop causes an input measured voltage higher than the input voltage at the UUT
input that, of course, affects the measured power. The voltage drop is generally negligible if
the UUT input current is low (for example when we are measuring the input power of UUT in
light load condition).
DocID023661 Rev 2
31/36
36
Test equipment and measurement of efficiency and light load performance
AN4165
Figure 46. Switch in position 1 - setting for standby measurements
Wattmeter
Ammeter
A
AC
SOURCE
~
+
U.U.T.
AC
INPUT
V
-
UUT
Voltmeter
AM11591v1
In the case of high UUT input current (i.e. for measurements in heavy load conditions), the
voltage drop can be relevant compared to the UUT real input voltage. If this is the case, the
switch in Figure 45 can be changed to position 2 (see simplified scheme of Figure 47) where
the UUT input voltage is measured directly at the UUT input terminal and the input current
does not affect the measured input voltage.
Figure 47. Switch in position 2 - setting for efficiency measurements
Wattmeter
Ammeter
A
AC
SOURCE
+
~
V
-
U.U.T.
AC
INPUT
UUT
Voltmeter
AM11592v1
On the other hand, the position of Figure 47 may introduce a relevant error during light load
measurements, when the UUT input current is low and the leakage current inside the
voltmeter itself (which is not an ideal instrument and doesn't have infinite input resistance) is
not negligible. This is the reason why it is better to use the setting of Figure 46 for light load
measurements and Figure 47 for heavy load measurements.
If it is not clear which measurement scheme has the lesser effect on the result, try with both
and register the lower input power value.
32/36
DocID023661 Rev 2
AN4165
Test equipment and measurement of efficiency and light load performance
As noted in IEC 62301, instantaneous measurements are appropriate when power readings
are stable. The UUT is operated at 100% of nameplate output current output for at least 30
minutes (warm-up period) immediately prior to conducting efficiency measurements.
After this warm-up period, the AC input power is monitored for a period of 5 minutes to
assess the stability of the UUT. If the power level does not drift by more than 5% from the
maximum value observed, the UUT can be considered stable and the measurements can
be recorded at the end of the 5-minute period. If AC input power is not stable over a 5minute period, the average power or accumulated energy is measured over time for both AC
input and DC output.
Some wattmeter models allow integration of the measured input power in a time range and
then measure the energy absorbed by the UUT during the integration time. The average
input power is calculated dividing by the integration time itself.
DocID023661 Rev 2
33/36
36
References
16
34/36
AN4165
References
–
Code of Conduct on energy efficiency of external power supplies, version 4
–
VIPER26 datasheet
DocID023661 Rev 2
AN4165
17
Revision history
Revision history
Table 13. Document revision history
Date
Revision
Changes
18-Feb-2013
1
Initial release.
18-May-2016
2
Added: new T1 part 750810131 Rev 6A in Table 2.
DocID023661 Rev 2
35/36
36
AN4165
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2016 STMicroelectronics – All rights reserved
36/36
DocID023661 Rev 2
Similar pages