dm00055759

AN4116
Application note
STEVAL-ISA112V1: 12 V/4 W, 115 kHz non-isolated flyback
By Mirko Sciortino
Introduction
This document describes a 12 V-350 mA power supply set in non-isolated flyback topology
with the VIPER06, a new offline high voltage converter by STMicroelectronics.
The features of the device are:
■
800 V avalanche rugged power section
■
PWM operation at 115 kHz with frequency jittering for lower EMI
■
limiting current with adjustable set point
■
onboard soft-start
■
safe auto-restart after a fault condition (overload, short-circuit)
The VIPER06 does not require a biasing circuit to operate because the IC can be supplied
by an internal current generator, therefore saving the cost of the transformers auxiliary
winding. If the device is biased through an auxiliary winding, the demonstration board can
reach very low standby consumption (< 30 mW at 230 VAC, with output load disconnected).
Both cases are treated in the present document. The available protections are: thermal
shutdown with hysteresis, delayed overload protection, open loop failure protection (the last
is available only if self-biasing is excluded).
Figure 1.
Demonstration board image
STEVAL-ISA112V1
January 2013
Doc ID 023220 Rev 1
1/38
www.st.com
Contents
AN4116
Contents
1
Adapter features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
Schematic and bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5
Testing the board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6
7
5.1
Typical waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2
Precision of the regulation and output voltage ripple . . . . . . . . . . . . . . . . 14
5.3
Burst mode and output voltage ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.4
Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.5
Light load performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Functional check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1
Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.2
Overload protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.3
Feedback loop failure protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Feedback loop calculation guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.1
Transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.2
Compensation procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8
Thermal measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9
EMI measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
10
Board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
11
Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2/38
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AN4116
Contents
Appendix A Test equipment and measurement of efficiency and light load
performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
A.1
Measuring input power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
12
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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3/38
List of figures
AN4116
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
4/38
Demonstration board image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
VDD waveforms IC externally biased (J1 selected) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VDD waveforms IC self-biased (J1 not selected) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Transformer size and pin diagram pin distances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Transformer electrical diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Transformer side view 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Transformer side view 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Drain current/voltage @ 115 VAC max. load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Drain current/voltage @ 230 VAC max. load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Drain current/voltage @ 90 VAC max. load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Drain current/voltage @ 265 VAC max. load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Line regulation at different loads; IC externally biased (J1 selected) . . . . . . . . . . . . . . . . . 14
Line regulation at different loads; IC self-biased (J1 not selected) . . . . . . . . . . . . . . . . . . . 14
Load regulation at different input voltages; IC externally biased (J1 selected). . . . . . . . . . 15
Load regulation at different input voltages; IC self-biased (J1 not selected) . . . . . . . . . . . 15
Output voltage ripple @ 115 VAC no load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Output voltage ripple @ 230 VAC no load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Output voltage ripple @ 115 VAC 25 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Output voltage ripple @ 230 VAC 25 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Active mode efficiency of the demonstration board
and comparison with energy efficiency standards (IC externally biased) . . . . . . . . . . . . . 17
PIN vs. VIN at no load and light load; IC externally biased (J1 selected) . . . . . . . . . . . . . . 19
PIN vs. VIN at no load and light load, IC self-biased (J1 not selected) . . . . . . . . . . . . . . . . 19
Efficiency @ PIN=1 W; IC externally biased (J1 selected) . . . . . . . . . . . . . . . . . . . . . . . . . 20
Efficiency @ PIN=1 W; IC self-biased (J1 not selected) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PIN @ POUT = 250 mW; IC externally biased (J1 selected) . . . . . . . . . . . . . . . . . . . . . . . . 20
PIN @ POUT = 250 mW; IC self-biased (J1 not selected) . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Soft-start at startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Soft-start at startup (zoom) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Output short-circuit applied: OLP tripping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Output short-circuit maintained: OLP steady-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Output short-circuit maintained: OLP steady-state (zoom) . . . . . . . . . . . . . . . . . . . . . . . . . 22
Output short-circuit removal and converter restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Feedback loop failure protection: tripping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Feedback loop failure protection: steady-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Feedback loop failure protection: steady-state, zoom . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Feedback loop failure protection: converter restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Control loop block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Thermal map at VIN=85 VAC, TAMB=25 °C, full load; IC externally biased . . . . . . . . . . . . . 27
Thermal map at VIN=85 VAC, TAMB=25 °C, full load; IC self-biased . . . . . . . . . . . . . . . . . . 27
Thermal map at VIN=115 VAC, full load, TAMB=25 °C; IC externally biased. . . . . . . . . . . . 27
Thermal map at VIN=115 VAC, full load, TAMB=25 °C; IC self-biased . . . . . . . . . . . . . . . . . 27
Thermal map @ VIN=230 VAC, full load, TAMB=25 °C; IC externally biased. . . . . . . . . . . . 28
Thermal map @ VIN=230 VAC, full load, TAMB=25 °C; IC self-biased . . . . . . . . . . . . . . . . 28
Thermal map @ VIN=265 VAC, full load, TAMB=25 °C; IC externally biased. . . . . . . . . . . . 28
Thermal map @ VIN=265 VAC, full load, TAMB=25 °C; IC self-biased . . . . . . . . . . . . . . . . 28
Peak measurements @ VIN=115 VAC, full load, TAMB=25 ×C; IC externally biased . . . . . 29
Doc ID 023220 Rev 1
AN4116
Figure 48.
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
List of figures
Peak measurements @ VIN=230 VAC, full load, TAMB=25 ×C; IC externally biased . . . . . 29
Quasi-peak measurements @ VIN=115 VAC, full load, TAMB=25 ×C; IC externally biased 29
Quasi-peak measurements @ VIN=230 VAC, full load, TAMB=25 ×C; IC externally biased 29
Average measurements @ VIN=115 VAC, full load, TAMB=25 ×C; IC externally biased . . . 30
Average measurements @ VIN=230 VAC, full load, TAMB=25 ×C; IC externally biased . . . 30
Board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Connections of the UUT to the wattmeter for power measurements . . . . . . . . . . . . . . . . . 33
Switch in position 1 - setting for standby measurements . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Switch in position 2 - setting for efficiency measurements . . . . . . . . . . . . . . . . . . . . . . . . . 34
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5/38
List of tables
AN4116
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
6/38
Electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Transformer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Output voltage line-load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output voltage ripple at no/light load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
No load input power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Energy consumption criteria for no load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Light load performance POUT=25 mW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Light load performance POUT=50 mW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
POUT @ PIN=1 W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Doc ID 023220 Rev 1
AN4116
1
Adapter features
Adapter features
The electrical specifications of the demonstration board are listed below in Table 1.
Table 1.
Electrical specifications
Parameter
Symbol
Value
VIN
[90 VAC; 265 VAC]
Output voltage
VOUT
12 V
Max. output current
IOUT
0.35 A
Precision of output regulation
ΔVOUT_HF
± 5%
High frequency output voltage ripple
ΔVOUT_HF
50 mV
Max. ambient operating temperature
TAMB
60 ºC
Input voltage range
2
Circuit description
The power supply is set in flyback topology. The schematic is given in Figure 2 and the bill of
materials in Table 2. The input section includes a resistor R0 for inrush current limiting and a
diode bridge (D0) and Pi filter for EMC suppression (Cin1, Lin, Cin2). The transformer core
is a standard E13. The output voltage value is set in a simple way through the RfbH-RfbL
voltage divider between the output terminal and the FB pin, according to the following
formula:
Equation 1
⎛
RfbH ⎞
VOUT = 3.3 ⋅ ⎜⎜1 +
⎟
RfbL ⎟⎠
⎝
In fact, the FB pin is the input of an error amplifier and is an accurate 3.3 V voltage
reference. In the schematic the upper resistor RfbH has been split into RfbH1 and RfbH2;
and the lower resistor RfbL into RfbL1 and RfbL2 in order to allow a better tuning of the
output voltage value. The compensation network is connected between the COMP pin
(which is the output of the error amplifier) and the GND pin and is made up of Cp, Cc and
Rc. The resistor RLIM, placed between the LIM and GND pins, has the purpose of reducing
the drain current limitation, from IDLIM to about 250 mA in order to limit the deliverable
output power of the converter and keep the power components safe. At power-up, as the
rectified input voltage rises over the VDRAINSTART threshold, the high voltage current
generator starts charging the VDD capacitor, CVDD, from 0 V up to VDDON. At this point the
Power MOSFET starts switching, the HV current generator is turned off and the IC is biased
by the energy stored in CVDD. In this demonstration board, if jumper J1 is not selected, the
IC is biased through the internal high voltage startup current generator, which is
automatically turned on as the VDD voltage drops to VDDCS_ON and switched off as VDD is
charged up to VDDON (self-biasing). The use of self-biasing means higher power dissipation
and must be avoided if low standby consumption is required. Self-biasing is excluded by
keeping the VDD pin voltage always above the VDDCS_ON threshold. In this board, since the
output voltage is higher than VDDCS_ON, this is obtained selecting jumper J1, which
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7/38
Circuit description
AN4116
connects the output terminal to the VDD through a small signal diode. If the output voltage is
lower than VDDCS_ON, the self-biasing can be excluded only using an auxiliary winding. The
IC biasing through auxiliary winding or through the output is referred to as external biasing.
In Figure 3 the VDD waveforms for both cases (IC external biased and self-biased) are
shown.
8/38
Doc ID 023220 Rev 1
R0
Doc ID 023220 Rev 1
AC IN
+
85Vac - 265Vac
AC IN
D0
Cin1 +
CVDD
Cin2 +
+
Cf ilt1
Cp
Cc
Rc
COMP
FB
LIM
RLIM
GND
DRAIN
VIPER06H
CONTROL
VDD
J1
1
Daux
Raux
3
2
Cf b
TR
7,8
5,6
D2
COUT
+
VOUT
Rf bL2
Rf bL1
Rf bH2
Rf bH1
GROUND
Cf ilt2
12V/350mA
Figure 2.
D1
Dz
Cc1
4
3
Lin
AN4116
Schematic and bill of material
Schematic and bill of material
Application schematic
-
AM11677v1
9/38
Schematic and bill of material
Table 2.
Ref.
Bill of material
Part
Description
Cin1
3.3 µF, 400 V NHG series electrolytic
capacitor
Cin2
3.3 µF, 400 V NHG series electrolytic
capacitor
CVDD
1 µF, 50 V electrolytic capacitor
Cfilt1
100 nF, 50 V ceramic capacitor
Cc
10 nF, 50 V ceramic capacitor
Cp
1 nF, 50 V ceramic capacitor
Cfb
1 nF, 50 V ceramic capacitor
Cout
330 µF, 16 V ZL series ultra-low ESR
electrolytic capacitor
Ccl
Not mounted
Cfilt2
Not mounted
D0
DF06M
D1
Not mounted
D2
STPS2H100
Daux
1N4148
Dz
Not mounted
600 V, 1 A diode bridge
100 V, 2 A, power Schottky rectifier
Manufacturer
Rubycon
Vishay
ST
Small signal diode
4.7 Ω 3/4 W resistor
R0
10/38
AN4116
RLIM
15 kΩ 5% 1/4 W resistor
Rc
47 kΩ 5% 1/4 W resistor
RfbH1
33 kΩ 1% 1/4 W resistor
RfbH2
0Ω
RfbL1
12 kΩ 1% 1/4 W resistor
RfbL2
0.47 kΩ 1% 1/4 W resistor
Raux
Not mounted
IC1
VIPer06HN
Offline high voltage PWM controller
T1
1921.0040
Transformer
Lin
B82144A2105J000
1 mH inductor LBC series
Doc ID 023220 Rev 1
ST
Magnetica
Epcos
AN4116
Figure 3.
Schematic and bill of material
VDD waveforms IC externally
biased (J1 selected)
Figure 4.
AM11678v1
Doc ID 023220 Rev 1
VDD waveforms IC self-biased
(J1 not selected)
AM11679v1
11/38
Transformer
4
AN4116
Transformer
The transformer characteristics are listed in the table below.
Table 3.
Transformer characteristics
Parameter
Value
Test conditions
Manufacturer
Magnetica
Part number
1921.0040
Primary inductance (pins 3 - 4)
1.2 mH ± 15%
Measured at 1 kHz 0.1 V
Leakage inductance
2.8%
Measured at 10 kHz 0.1 V
Primary to secondary turn ratio (3 - 4)/(5 - 8)
6.11 ± 5%
Measured at 10 kHz 0.1 V
Primary to auxiliary turn ratio (3 - 4)/(2 - 1)
5 ± 5%
Measured at 10 kHz 0.1 V
The following figures show size and pin distances ([mm]) of the transformer.
Figure 5.
Transformer size and pin diagram
pin distances
Figure 6.
Transformer electrical diagram
AM11680v1
Figure 7.
Transformer side view 1
AM11681v1
Figure 8.
AM11682v1
12/38
Doc ID 023220 Rev 1
Transformer side view 2
AM11683v1
AN4116
Testing the board
5
Testing the board
5.1
Typical waveforms
Figure 9.
Drain voltage and current waveforms in full load condition are reported for the two nominal
input voltages in Figure 9 and 10, and for minimum and maximum input voltage in Figure 11
and 12 respectively.
Drain current/voltage @ 115 VAC
Figure 10. Drain current/voltage @ 230 VAC
max. load
max. load
AM11684v1
Figure 11. Drain current/voltage @ 90 VAC
max. load
AM11685v1
Figure 12. Drain current/voltage @ 265 VAC
max. load
AM11686v1
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AM11687v1
13/38
Testing the board
5.2
AN4116
Precision of the regulation and output voltage ripple
The output voltage of the board has been measured in different line and load conditions with
the results shown in Table 4. The output voltage is practically not affected by the line
condition and by the IC biasing (self-supply or not).
Table 4.
Output voltage line-load regulation
VOUT [V]
No load
VIN [VAC]
50% load
75% load
100% load
IC
externally
biased
IC selfbiased
IC
externally
biased
IC selfbiased
IC
externally
biased
IC selfbiased
IC
externally
biased
IC selfbiased
90
12.04
12.05
12.00
11.98
12.00
11.98
11.99
11.97
115
12.05
12.05
12.00
11.99
12.00
11.98
11.99
11.97
150
12.05
12.05
12.00
11.98
12.00
11.98
11.99
11.97
180
12.05
12.04
12.00
11.98
12.00
11.98
11.99
11.97
230
12.05
12.04
12.00
11.98
12.00
11.98
11.99
11.97
265
12.05
12.04
12.00
11.98
12.00
11.98
11.99
11.97
12.2
12.2
12.1
12.1
12
12
0
11.9
25%
VOUT [V]
VOUT [V]
Figure 13. Line regulation at different loads; IC Figure 14. Line regulation at different loads; IC
externally biased (J1 selected)
self-biased (J1 not selected)
0
11.9
25%
50%
11.8
75%
50%
11.8
75%
100%
80
105
130
155
180
VIN[V AC ]
14/38
100%
11.7
11.7
205
230
255
80
AM11688v1
Doc ID 023220 Rev 1
105
130
155
180
VIN [V AC ]
205
230
255
AM11689v1
AN4116
Testing the board
Figure 16. Load regulation at different input
voltages; IC self-biased
(J1 not selected)
12.2
12.2
12.1
12.1
VOUT [V]
VOUT [V]
Figure 15. Load regulation at different input
voltages; IC externally biased
(J1 selected)
12
90
11.9
12
90
11.9
115
115
11.8
230
11.8
230
265
265
11.7
11.7
0
5.3
0.05
0.1
0.15
0.2 0.25
IOUT [A]
0.3
0.35
0.4
0
0.05
AM11690v1
0.1
0.15
0.2 0.25
IOUT [A]
0.3
0.35
0.4
AM11691v1
Burst mode and output voltage ripple
When the converter is lightly loaded, the COMP pin voltage decreases. As it reaches the
shutdown threshold, VCOMPL (1.1 V, typical), the switching is disabled and no more energy is
transferred to the secondary side. So, the output voltage decreases and the regulation loop
makes the COMP pin voltage increase again. As it rises 40 mV above the VCOMPL
threshold, the normal switching operation is resumed. This results in a controlled on/off
operation which is referred to as “burst mode”. This mode of operation keeps the frequencyrelated losses low when the load is very light or disconnected, making it easier to comply
with energy saving regulations.
The figures below show the output voltage ripple when the converter is no/lightly loaded and
supplied with 115 VAC and 230 VAC respectively.
Figure 17. Output voltage ripple @ 115 VAC
no load
Figure 18. Output voltage ripple @ 230 VAC
no load
AM11692v1
Doc ID 023220 Rev 1
AM11693v1
15/38
Testing the board
AN4116
Figure 19. Output voltage ripple @ 115 VAC
25 mA
Figure 20. Output voltage ripple @ 230 VAC
25 mA
AM11694v1
AM11695v1
Table 5 shows the measured value of the burst mode frequency ripple measured in different
operating conditions. The ripple in burst mode operation is very low.
Table 5.
Output voltage ripple at no/light load
VOUT [mV]
VIN [VAC]
5.4
No load
25 mA load
90
2
7
115
2
7
230
4
8
265
4
9
Efficiency
The active mode efficiency is defined as the average of the efficiencies measured at 25%,
50%, 75% and 100% of maximum load, at nominal input voltage (VIN = 115 VAC and VIN =
230 VAC).
External power supplies (the power supplies which are contained in a separate housing
from the end-use devices they are powering) need to comply with the Code of Conduct
(version 4) “Active Mode Efficiency” criterion, which states an active mode efficiency higher
than 71.18% for a power throughput of 4.2 W.
Another standard to be applied to external power supplies in the coming years is the DOE
(Department of Energy) recommendation, whose active mode efficiency requirement for the
same power throughput is 76.6%.
If the IC is externally biased, the presented demonstration board is compliant with both
standards, as can be seen from Figure 21, where the average efficiencies of the board at
115 VAC (81.6%) and at 230 VAC (77.2%) are plotted with dotted lines, together with the
above limits. In the same figure the efficiency at 25%, 50%, 75% and 100% of output load
for both input voltages is also shown.
16/38
Doc ID 023220 Rev 1
AN4116
Testing the board
Figure 21. Active mode efficiency of the demonstration board and comparison with
energy efficiency standards (IC externally biased)
85
83
81
eff [%]
79
77
DOE limit
75
73
71
CoC4 limit
69
115
230
av @ 115Vac
av @ 230Vac
67
65
0.2
5.5
0.4
0.6
0.8
Iout [% I OUT ]
1
AM11696v1
Light load performance
The input power of the converter has been measured in no load condition for different input
voltages and the results are reported in Table 6.
Table 6.
No load input power
PIN [mW]
VIN [VAC]
IC externally biased
IC self-biased
90
17.2
108
115
18.3
137
150
20.2
178
180
22.1
213
230
25.9
273
265
28.5
314
In version 4 of the Code of Conduct, also the power consumption of the power supply when
it is no loaded is considered. The criteria to be compliant with are reported in Table 7 below:
Table 7.
Energy consumption criteria for no load
Nameplate output power (Pno)
Maximum power in no load for AC-DC EPS
0 W ≤ Pno ≤ 50 W
< 0.3 W
50 W < Pno < 250 W
< 0.5 W
The performance of the presented board (when the self-supply function is not used) is much
better than required; the power consumption is more than ten times lower than the limit fixed
by version 4 of the Code of Conduct. Even though the performance seems to be
Doc ID 023220 Rev 1
17/38
Testing the board
AN4116
disproportionally better than requirements, it is worth noting that often AC-DC adapter or
battery charger manufacturers have very strict requirements about no load consumption and
if the converter is used as an auxiliary power supply, the line filter is often the big line filter of
the entire power supply that increases greatly the standby consumption.
Even though version 4 of the Code of Conduct does not have other requirements regarding
light load performance, in order to give a more complete overview, we report the input power
and efficiency of the demonstration board also in two other low load cases. Table 8 and 14
show the performance when the output load is 25 mW and 50 mW respectively.
Table 8.
Light load performance POUT=25 mW
PIN [mW]
VIN [VAC]
POUT [mW]
Efficiency (%)
IC externally
biased
IC self-biased
IC externally
biased
IC self-biased
90
25
49.7
128
50.30
19.6
115
25
51.5
157
48.54
15.9
150
25
54.7
200
45.70
12.5
180
25
57.3
236
43.63
10.6
230
25
61.7
296
40.52
8.4
265
25
64.8
337
38.58
7.4
Table 9.
Light load performance POUT=50 mW
PIN [mW]
VIN [VAC]
POUT [mW]
Efficiency (%)
IC externally
biased
IC self-biased
IC externally
biased
IC self-biased
90
50
82.4
167
60.71
29.94
115
50
85.0
198
58.82
25.25
150
50
89.3
242
55.99
20.66
180
50
93.0
280
53.76
17.86
230
50
98.0
341
51.02
14.66
265
50
101.1
384
49.46
13.02
The input power vs. input voltage for no and light load conditions (Table 7, 8 and 14) are
reported in the diagrams below.
18/38
Doc ID 023220 Rev 1
AN4116
Testing the board
Figure 22. PIN vs. VIN at no load and light
load; IC externally biased
(J1 selected)
Figure 23. PIN vs. VIN at no load and light load,
IC self-biased (J1 not selected)
400
200
0
350
25mW
150
300
PIN [mW]
PIN [mW]
50mW
100
250
200
150
0
100
50
25mW
50
50mW
0
0
80
105
130
155
180
VIN [V AC ]
205
230
80
255
105
130
155
180
205
230
VIN [V AC ]
AM11543v1
255
AM11544v1
Depending on the equipment supplied, we can have several criteria to measure the standby
or light load performance of a converter. One of these is the measurement of the output
power when the input power is equal to one watt. In Table 10 the output power needed to
have 1 W of input power in different line conditions is reported. Figure 24 and 25 show the
diagram of the output powers corresponding to PIN = 1 W for different values of the input
voltage.
Table 10.
POUT @ PIN=1 W
POUT [W]
VIN [VAC]
PIN [W]
Efficiency (%)
IC externally
biased
IC self-biased
IC externally
biased
IC self-biased
90
1
0.78
0.64
78
64
115
1
0.77
0.60
77
60
150
1
0.73
0.55
73
55
180
1
0.70
0.49
70
49
230
1
0.68
0.43
68
43
265
1
0.65
0.40
65
40
Doc ID 023220 Rev 1
19/38
Testing the board
AN4116
Figure 24. Efficiency @ PIN=1 W; IC externally Figure 25. Efficiency @ PIN=1 W; IC selfbiased (J1 selected)
biased (J1 not selected)
80
80
75
75
70
70
65
eff [%]
eff [%]
65
60
55
60
55
50
50
45
45
40
40
35
80
110
140
170
200
230
VIN [V AC ]
260
80
110
140
170
200
230
VIN[V AC ]
AM11545v1
260
AM11546v1
Another requirement (EuP lot 6) is that the input power should be less than 500 mW when
the converter is loaded with 250 mW. The performance is shown in Figure 26 for IC
externally biased and in Figure 27 for self-biasing.
Figure 26. PIN @ POUT = 250 mW; IC externally Figure 27. PIN @ POUT = 250 mW; IC selfbiased (J1 selected)
biased (J1 not selected)
0.8
0.5
0.75
0.7
0.45
0.65
0.6
PIN [W]
PIN [W]
0.4
0.35
0.55
0.5
0.45
0.4
0.3
0.35
0.25
0.25
0.3
80
110
140
170
VIN [V AC ]
20/38
200
230
260
80
AM13108v1
Doc ID 023220 Rev 1
110
140
170
200
VIN [V AC ]
230
260
AM13109v1
AN4116
Functional check
6
Functional check
6.1
Soft-start
At startup the current limitation value reaches IDLIM after an internally fixed time, tSS,
whose typical value is 8.5 msec. This time is divided into 16 time intervals, each
corresponding to a current limitation step progressively increasing. In this way the drain
current is limited during the output voltage increase, therefore reducing the stress on the
secondary diode.
The soft-start phase is shown in Figure 28 and 29.
Figure 28. Soft-start at startup
Figure 29. Soft-start at startup (zoom)
AM13094v1
6.2
AM13095v1
Overload protection
In the case of overload or short-circuit (see Figure 38), the drain current reaches the IDLIM
value (or the one set by the user through the RLIM resistor). In every cycle where this
condition is met, a counter is incremented; if it is maintained continuously for the time tOVL
(50 msec typical, internally fixed), the overload protection is tripped, the power section is
turned off and the converter is disabled for a tRESTART time (1sec typical). After this time has
elapsed, the IC resumes switching and, if the short is still present, the protection occurs
indefinitely in the same way (Figure 31). This ensures restart attempts of the converter with
low repetition rate, so that it works safely with extremely low power throughput and avoids
the IC overheating in the case of repeated overload events.
Furthermore, every time the protection is tripped, the internal soft startup function is invoked
(Figure 32), in order to reduce the stress on the secondary diode.
After the short removal, the IC resumes normal working. If the short is removed during tSS or
tOVL, i.e. before the protection tripping, the counter is decremented on a cycle-by-cycle basis
down to zero and the protection is not tripped.
If the short-circuit is removed during tRESTART, the IC must wait for the tRESTART period to
elapse before switching is resumed (Figure 33).
Doc ID 023220 Rev 1
21/38
Functional check
AN4116
Figure 30. Output short-circuit applied: OLP
tripping
Figure 31. Output short-circuit maintained:
OLP steady-state
Output is shorted here
Normal
operation
tRESTART
AM13096v1
Figure 32. Output short-circuit maintained:
OLP steady-state (zoom)
tSS
AM13097v1
Figure 33. Output short-circuit removal and
converter restart
tOVL
tRESTART
Normal
operation
tRESTART
Output short is
removed here
AM13098v1
6.3
AM13099v1
Feedback loop failure protection
This protection is available any time the IC is not self-biased. As the loop is broken (RfbL
shorted or RfbH open), the output voltage VOUT increases and the VIPER06 runs at its
maximum current limitation. The VDD pin voltage increases as well, because it is linked to
the VOUT voltage either directly or through the auxiliary winding, depending on the cases.
If the VDD voltage reaches the VDD clamp threshold (23.5 V min.) in less than 50 msec, the
IC is shut down by open loop failure protection (see Figure 34 and 35), otherwise by OLP, as
described in the previous section. The breaking of the loop has been simulated by shorting
the low side resistor of the output voltage divider, RfbL = RfbL1+RfbL2. The same behavior
can be induced opening the high side resistor, RfbH = RfbH1+RfbH2.
22/38
Doc ID 023220 Rev 1
AN4116
Functional check
The protection acts in auto-restart mode with tRESTART = 1sec (Figure 35). As the fault is
removed, normal operation is restored after the last tRESTART interval has been completed
(Figure 37).
Figure 34. Feedback loop failure protection:
tripping
Figure 35. Feedback loop failure protection:
steady-state
Fault is applied here
tRESTART
VDD reaches VDDCLAMP
Normal
operation
< tOVL
Normal
operation
Output short is
removed here
tRESTART
AM13203v1
Figure 36. Feedback loop failure protection:
steady-state, zoom
AM13204v1
Figure 37. Feedback loop failure protection:
converter restart
Fault is removed here
tRESTART
< tOVL
AM13205v1
Doc ID 023220 Rev 1
Normal
operation
AM13206v1
23/38
Feedback loop calculation guidelines
AN4116
7
Feedback loop calculation guidelines
7.1
Transfer function
The set PWM modulator + power stage is indicated with G1(f), while C(f) is the “controller”,
i.e. the network which is in charge to ensure the stability of the system.
Figure 38. Control loop block diagram
AM11582v1
The mathematical expression of the power plant G1(f) is the following:
Equation 2
ΔVOUT
G1 (f) =
=
ΔI pk
j ⋅ 2 ⋅π ⋅ f
j⋅ f
)
VOUT ⋅ (1 +
)
z
fz
=
j ⋅2 ⋅π ⋅ f
j⋅ f
) Ipkp( fsw, Vdc) ⋅ (1 +
)
Ipkp( fsw, Vdc ) ⋅ (1 +
p
fp
VOUT ⋅ (1 +
where fp is the pole due to the output load and fz the zero due to the ESR of the output
capacitor:
Equation 3
fp =
1
π ⋅ C OUT ·(R OUT + 2ESR)
Equation 4
fz =
24/38
1
2 ⋅ π ⋅ C OUT ·ESR
Doc ID 023220 Rev 1
AN4116
Feedback loop calculation guidelines
The mathematical expression of the compensator C(f) is:
Equation 5
C( f ) =
ΔI pk
ΔVOUT
C0
=
⋅
HCOMP
f⋅j
fZc
⎛
f ⋅ j⎞
2 ⋅ π ⋅ f ⋅ j ⋅ ⎜⎜1 +
⎟
fPc ⎟⎠
⎝
1+
where:
Equation 6
Co = −
Gm
RfbL
⋅
Cc + Cp RfbL + RfbH
Equation 7
fZc =
1
2 ⋅ π ⋅ Rc ⋅ Cc
Equation 8
fPc =
Cc + Cp
2 ⋅ π ⋅ Rc ⋅ Cc ⋅ Cp
are chosen in order to ensure the stability of the overall system. Gm = 2 mA/V (typical) is the
VIPER06 transconductance.
7.2
Compensation procedure
The first step is to choose the pole and zero of the compensator and the crossing frequency,
for instance:
–
fZc = fp/2
–
fPc = fz
–
fcross = fcross_sel ≤fsw/10
G1(fcross_sel) can be calculated from Equation 2 and, since by definition it is
| C(fcross_sel)*G1(fcross_sel)| = 1, C0 can be calculated as follows:
Equation 9
2 ⋅ π ⋅ fcross _ sel ⋅ j ⋅ 1 +
C0 =
1+
fcross _ sel ⋅ j
fPc
fcross _ sel ⋅ j
fZc
Doc ID 023220 Rev 1
⋅
HCOMP
G1( fcross _ sel )
25/38
Feedback loop calculation guidelines
AN4116
At this point the bode diagram of G1(f)*C(f) can be plotted, in order to check the phase
margin for the stability. If the margin is not high enough, an alternative choice should be
made for fZc, fPc and fcross_sel, and the procedure repeated. When the stability is
ensured, the next step is to find the values of the schematic components, which can be
calculated, using the above formulas, as follows:
Equation 10
RfbL =
RfbH
Vout
−1
3. 3V
Equation 11
Cp =
fZc Gm
RfbL
⋅
⋅
fPc C 0 RfbL+ RfbH
Equation 12
⎛ fPc ⎞
Cc = Cp ⋅ ⎜⎜
− 1⎟⎟
⎝ fZc ⎠
Equation 13
Rc =
26/38
Cc + Cp
2 ⋅ π ⋅ fPc ⋅ Cc ⋅ Cp
Doc ID 023220 Rev 1
AN4116
8
Thermal measurements
Thermal measurements
A thermal analysis of the board has been performed using an IR camera for 85 VAC, 115
VAC, 230 VAC and 265 VAC mains input, full load condition, both with and without the selfbiasing function. The results are shown in the following figures. When the self-biasing
function is used, the VIPER06 temperature is higher, due to the power dissipated by the HVstartup generator.
Figure 39. Thermal map at VIN=85 VAC,
TAMB=25 °C, full load; IC externally
biased
Figure 40. Thermal map at VIN=85 VAC,
TAMB=25 °C, full load; IC self-biased
Figure 41. Thermal map at VIN=115 VAC, full
load, TAMB=25 °C; IC externally
biased
Figure 42. Thermal map at VIN=115 VAC, full
load, TAMB=25 °C; IC self-biased
Doc ID 023220 Rev 1
27/38
Thermal measurements
AN4116
Figure 43. Thermal map @ VIN=230 VAC, full
load, TAMB=25 °C; IC externally
biased
Figure 44. Thermal map @ VIN=230 VAC, full
load, TAMB=25 °C; IC self-biased
Figure 45. Thermal map @ VIN=265 VAC, full
load, TAMB=25 °C; IC externally
biased
Figure 46. Thermal map @ VIN=265 VAC, full
load, TAMB=25 °C; IC self-biased
28/38
Doc ID 023220 Rev 1
AN4116
9
EMI measurements
EMI measurements
A pre-compliant test of the EN55022 (Class B) European standard has been performed
using an EMC analyzer and an LISN. Peak, quasi-peak and average measurements have
been conducted as reported in the following figures.
Figure 47. Peak measurements @
Figure 48. Peak measurements @
VIN=115 VAC, full load, TAMB=25 ° C;
VIN=230 VAC, full load, TAMB=25 ° C;
IC externally biased
IC externally biased
AM13101v1
AM13102v1
Figure 49. Quasi-peak measurements @
Figure 50. Quasi-peak measurements @
VIN=115 VAC, full load, TAMB=25 ° C;
VIN=230 VAC, full load, TAMB=25 ° C;
IC externally biased
IC externally biased
AM13103v1
Doc ID 023220 Rev 1
AM13104v1
29/38
EMI measurements
AN4116
Figure 51. Average measurements @ VIN=115 Figure 52. Average measurements @ VIN=230
VAC, full load, TAMB=25 ° C; IC
VAC, full load, TAMB=25 ° C; IC
externally biased
externally biased
AM11646v1
30/38
Doc ID 023220 Rev 1
AM11647v1
AN4116
10
Board layout
Board layout
Figure 53. Board layout
AM11625v1
Doc ID 023220 Rev 1
31/38
Conclusions
11
AN4116
Conclusions
The VIPER06 allows a non-isolated converter to be designed in a simple way and with few
external components. In this document a flyback has been described and characterized.
Special attention has been given to light load performance. The efficiency performance has
been compared to the requirements of the Code of Conduct (version 4) for an external ACDC adapter with very good results, the measured active mode efficiency is always higher
with respect to the minimum required.
32/38
Doc ID 023220 Rev 1
AN4116
Test equipment and measurement of efficiency and light load performance
Appendix A
Test equipment and measurement of
efficiency and light load performance
The converter input power has been measured using a wattmeter. The wattmeter measures
simultaneously the converter input current (using its internal ammeter) and voltage (using its
internal voltmeter). The wattmeter is a digital instrument so it samples the current and
voltage and converts them to digital forms. The digital samples are then multiplied giving the
instantaneous measured power. The sampling frequency is in the range of 20 kHz (or higher
depending on the instrument used). The display provides the average measured power,
averaging the instantaneous measured power in a short period of time (1 sec typ.).
Figure 54 shows how the wattmeter is connected to the UUT (unit under test) and to the AC
source and the wattmeter internal block diagram.
Figure 54. Connections of the UUT to the wattmeter for power measurements
Switch
1
WATT METER
2
U.U.T
(Unit Under test)
Voltmeter
AC
SOURCE
+
V
Multiplier
A
X
Ammeter
INPUT
OUTPUT
AVG
DISPLAY
AM13105v1
An electronic load has been connected to the output of the power converter (UUT), allowing
to set and measure the converter load current, while the output voltage has been measured
by a voltmeter. The output power is the product between load current and output voltage.
The ratio between the output power, calculated as previously stated, and the input power,
measured by the wattmeter, is the converter’s efficiency, which has been measured in
different input/output conditions.
A.1
Measuring input power
With reference to Figure 54, the UUT input current causes a voltage drop across the
ammeter’s internal shunt resistance (the ammeter is not ideal as it has an internal
resistance higher than zero) and across the cables connecting the wattmeter to the UUT.
If the switch of Figure 54 is in position 1 (see also the simplified scheme of Figure 55), this
voltage drop causes an input measured voltage higher than the input voltage at the UUT
input that, of course, affects the measured power. The voltage drop is generally negligible if
the UUT input current is low (for example, when measuring the input power of UUT in light
load condition).
Doc ID 023220 Rev 1
33/38
Test equipment and measurement of efficiency and light load performance
AN4116
Figure 55. Switch in position 1 - setting for standby measurements
Wattmeter
Ammeter
AC
SOURCE
~
A
+
U.U.T.
AC
INPUT
V
-
UUT
Voltmeter
AM13106v1
In the case of high UUT input current (i.e. for measurements in heavy load conditions), the
voltage drop can be relevant compared to the UUT real input voltage. If this is the case, the
switch in Figure 54 can be changed to position 2 (see simplified scheme of Figure 56),
where the UUT input voltage is measured directly at the UUT input terminal and the input
current does not affect the measured input voltage.
Figure 56. Switch in position 2 - setting for efficiency measurements
Wattmeter
Ammeter
A
AC
SOURCE
+
~
V
-
U.U.T.
AC
INPUT
UUT
Voltmeter
AM13107v1
On the other hand, the position of Figure 56 may introduce a relevant error during light load
measurements, when the UUT input current is low and the leakage current inside the
voltmeter itself (which is not an ideal instrument and doesn't have infinite input resistance) is
not negligible. This is why it is recommended to use the setting of Figure 55 for light load
measurements and the setting of Figure 56 for heavy load measurements.
If it is not clear which measurement scheme has the lesser effect on the result, try with both
and register the lower input power value.
As noted in IEC 62301, instantaneous measurements are appropriate when power readings
are stable. The UUT is operated at 100% of nameplate output current for at least 30 minutes
(warm-up period) immediately prior to conducting efficiency measurements. After this warmup period, the AC input power is monitored for a period of 5 minutes to assess the stability of
the UUT. If the power level does not drift by more than 5% from the maximum value
34/38
Doc ID 023220 Rev 1
AN4116
Test equipment and measurement of efficiency and light load performance
observed, the UUT can be considered stable and the measurements can be recorded at the
end of the 5-minute period. If AC input power is not stable over a 5-minute period, the
average power or accumulated energy is measured over time for both AC input and DC
output.
Some wattmeter models allow the measured input power to be integrated in a time range
and then the energy absorbed by the UUT to be measured during the integration time. The
average input power is calculated by dividing by the integration time itself.
Doc ID 023220 Rev 1
35/38
References
12
36/38
AN4116
References
–
[1] Code of Conduct on Energy Efficiency of External Power Supplies, Version 4.
–
[2] VIPER06 datasheet.
Doc ID 023220 Rev 1
AN4116
13
Revision history
Revision history
Table 11.
Document revision history
Date
Revision
23-Jan-2013
1
Changes
Initial release.
Doc ID 023220 Rev 1
37/38
AN4116
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