AN4149 Application note Designing a CCM PFC pre-regulator based on the L4984D By Hiroshi Andrea Fusillo Introduction Two methods of controlling power factor corrector (PFC) pre-regulators based on boost topology are currently in use: the fixed-frequency (FF) PWM and the transition mode (TM) PWM (fixed on-time, variable frequency). With the first method the boost inductor works in a continuous conduction mode (CCM) and employs average current-mode control, a relatively complex technique requiring sophisticated controller ICs (e.g. the L4981A/B from STMicroelectronics) and a considerable component count. The second one uses the more simple peak current-mode control and makes the inductor work on the boundary between continuous and discontinuous mode, which is implemented with cheaper controller ICs (e.g. the L6562A, L6563x and L6564x from STMicroelectronics), and much fewer external parts, making it far more cost efficient. For a given power throughput, TM operation involves higher peak currents compared to FF-CCM (see the figures below). Figure 1. Line and inductor currents in CCM PFC Figure 2. Line and inductor currents in TM PFC AM13300v1 AM13301v1 This demonstration, consistent with the above-mentioned cost considerations, suggests the use of TM in a lower power range, while FF-CCM is recommended for higher power levels. In the power range of around 150-300 W, assessing which approach gives the better cost/ performance trade-off needs to be done on a case-by-case basis, considering the cost and stress of both power semiconductors and magnetic components, but also of the EMI filter. At the same power level, the switching frequency component to be filtered out in a TM system is twice the line current, whereas it is typically 1/3 or 1/4 in a CCM system. In this document the CCM using a fixed-off-time (FOT) control mode, fully integrated in the controller, is proposed, coupling simplicity and low port count similar to a TM control. The design procedure is explained too. June 2013 DocID023523 Rev 2 1/43 www.st.com Contents AN4149 Contents 1 CCM PFC using FOT control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Designing a CCM FOT-controlled PFC . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 2.1 Input specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 Power section design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.1 Bridge rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.2 Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.3 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.4 Boost inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.5 Power MOSFET selection and power dissipation calculation . . . . . . . . 18 2.3.6 Boost diode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 L4984D biasing circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.1 Feedback and OVP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.2 Current sense resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3 Mult divider and VFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.4 Gate driver (GD) and VCC pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4 FOT PFC boost control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5 Layout hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6 Design example using the L4984D-CCM PFC excel spreadsheet . . . 38 7 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2/43 DocID023523 Rev 2 AN4149 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Line and inductor currents in CCM PFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Line and inductor currents in TM PFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Block diagram of an FOT-controlled PFC preregulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Line-modulated FOT modulator internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Line-modulated FOT modulator key waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Boundary between DCM and CCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Typical frequency change along a line half-cycle in a boost PFC operated in LM FOT . . . . 8 Typical frequency change along a line half-cycle in a boost PFC operated in TM . . . . . . . . 8 LM FOT controlled boost PFC: current waveforms (line current) . . . . . . . . . . . . . . . . . . . . . 8 LM FOT controlled boost PFC: current waveforms (boost inductor current envelope). . . . . 8 Line-modulated, FOT controlled boost PFC: input current harmonic contents . . . . . . . . . . . 9 Total MOSFETs losses in the 350 W FOT PFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Multiplier characteristics family for VFF = 1 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Multiplier characteristics family for VFF = 3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Small signal model of a PFC stage with a constant-power load (DC-DC converter) . . . . . 30 Bode plots of the control-to-output transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Schematic diagram of a type II compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Bode plots of a type II amplifier's transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Bode plots of the closed-loop transfer function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 115 Vac step load (50 % to 100 %): improper compensation . . . . . . . . . . . . . . . . . . . . . . . 36 115 Vac step load (50 % to 100 %): good compensation . . . . . . . . . . . . . . . . . . . . . . . . . . 36 EVL4984-350W PCB layout (SMT side view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Excel spreadsheet design specification input table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Other design data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 CCM PFC schematic based on the L4984D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Excel spreadsheet BOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 DocID023523 Rev 2 3/43 CCM PFC using FOT control 1 AN4149 CCM PFC using FOT control Fixed-frequency PWM is not the only alternative when CCM operation is desired. An additional approach that couples the simplicity and affordability of TM operation with the high-current capability of CCM operation can be a solution to the problem. Fixed-frequency PWM modulates both switch ON and OFF times (their sum is constant by definition), and a given converter operates in either CCM or DCM depending on the input voltage and the loading conditions. Exactly the same result can be achieved with FOT approach: a conventional "peak" current mode control, where the ON-time TON of the external power switch is determined by the peak inductor current reaching the programmed value and the OFF-time TOFF is determined by a special Fixed-off-time (FOT) modulator in such a way that the resulting switching period is constant as long as the boost converter is operated in CCM (i.e. the current in the boost inductor remains greater than zero in a switching cycle). In Figure 3 a block diagram of an FOT-controlled CCM PFC pre-regulator is shown. An error amplifier (VA) compares a portion of the boosted output voltage Vout with a reference VREF and generates an error signal VC proportional to their difference, a DC voltage by hypothesis, which is fed into an input of the multiplier block and multiplied by a portion of the rectified input voltage VMULT. The multiplier output (VCSREF) is a rectified sine wave whose amplitude is proportional to that of VMULT and to VC, and is used as a reference for PWM modulation. The multiplier output is fed into the inverting input of a PWM comparator that, on the non-inverting input, receives the voltage VCS from the sense resistor Rsense, proportional to the current flowing through the switch M (typically a MOSFET) and the inductor L during the ON-time of M. When the two voltages are equal, the comparator resets the PWM latch and M is turned off. As a result, the multiplier output determines the peak current through the switch and the inductor, and as, it is a rectified sinusoid, the inductor peak current is also enveloped by a rectified sinusoid. When VCSREF and VCS are equal the PWM latch output Q going high activates the timer that, after a predetermined time in which TOFF has elapsed, sets the PWM latch, therefore turning the switch on and starting another switching cycle. If TOFF is such that the inductor current does not fall to zero, the system operates in CCM. For the CCM PFC controller, please refer to Figure 4. To understand how TOFF needs to be modulated to achieve a fixed switching frequency independent of the instantaneous line voltage and the load, it is useful to consider the V·s balance equation for the boost inductor under the assumption of CCM operation: Equation 1 TON Vpk sin θ = TOFF ( Vout −Vpk sin θ ) where Vpk is the peak line voltage, Vout is the regulated output voltage, and θ is the instantaneous phase angle of the line voltage. Solving for TON we get: Equation 2 Vout TON = − 1 TOFF Vpk sin θ 4/43 DocID023523 Rev 2 AN4149 CCM PFC using FOT control then, the switching period TSW will be: Equation 3 Vout Vout Tsw = TON + TOFF = − 1 TOFF + TOFF = TOFF Vpk sin θ Vpk sin θ In the end, if TOFF is changed proportionally to the instantaneous line voltage, i.e. if: Equation 4 TOFF = K t Vpk sin θ then TSW will be equal to Kt·Vout and, since Vout is regulated by the voltage loop, also TSW (and fSW=1/TSW) will be fixed. This result is based on the sole assumption that the instantaneous line voltage and the output load are such that the boost inductor operates in CCM. Figure 3. Block diagram of an FOT-controlled PFC preregulator DocID023523 Rev 2 5/43 CCM PFC using FOT control AN4149 Figure 4. Line-modulated FOT modulator internal block diagram 0 COMP MULT CS + - Multiplier - ITimer PWM Comparator S + Q GD TIMER Driver R ON OFF PWM Latch CT AM13303v1 Figure 5. Line-modulated FOT modulator key waveforms MULT TIMER S TOFF TON t t R t Q t GD t Multiplier output CS t AM13304v1 With reference to the block diagram (Figure 4) and the relevant key waveforms in Figure 5, an OFF-time proportional to the instantaneous line voltage is achieved by charging the capacitor CT with a constant current ITIMER, accurately fixed internally and temperature compensated, while the MOSFET is off and commanding MOSFET's turn-on (and resetting CT at zero) as the voltage across CT equals that on the pin MULT. The voltage on this pin is: Equation 5 VMULT = K P Vpk sin θ where KP is the divider ratio of the resistors biasing pin MULT. As a result: Equation 6 TOFF = 6/43 CT ITIMER K P Vpk sin θ DocID023523 Rev 2 → Kt = CT I TIMER KP AN4149 CCM PFC using FOT control and the switching frequency will be: Equation 7 f sw = I TIMER 1 1 = = Tsw K P CT Vout K t Vout The timing capacitor CT, therefore, will be selected with the following design formula: Equation 8 CT = I TIMER K P Vout f sw Vout and fsw are design specifications, KP is chosen so that the voltage on pin MULT is within the multiplier's linearity range (0 to 3 V) and ITIMER is specified in the "Electrical characteristics" section of the L4984D datasheet. Along a line half-cycle, TOFF goes all the way from nearly zero to the maximum on the sinusoid peak. It is important to check that the OFF-time occurring on the peak of the sinusoidal voltage at minimum input voltage is greater than the minimum programmable value: Equation 9 TOFF min = CT I TIMER K P Vpk min > 1.2 μ s This constraint limits the maximum programmable frequency at: Equation 10 f sw. max = 833 Vpkmin Vout [KHz] As the line RMS voltage is increased and/or the output load is decreased the boost inductor current tends to become discontinuous starting from the region around the zero-crossings. As a result, in the DCM regions the switching frequency is no longer constant and tends to increase. Figure 6. Boundary between DCM and CCM AM13305v1 DocID023523 Rev 2 7/43 CCM PFC using FOT control AN4149 However, the frequency rise is significantly lower as compared to that of a transition-mode (TM) operated boost PFC stage, as illustrated in Figure 7 and 8 . Figure 7. Typical frequency change along Figure 8. Typical frequency change along a line half-cycle in a boost PFC operated a line half-cycle in a boost PFC operated in LM FOT in TM 9 1.6 1.4 Vin=230 Vac 1.2 1 Vin= 88 Vac 0.8 Vin=230 Vac 8 Normalized switching frequency Normalized switching frequency Vin=264 Vac Vin= 115 Vac 0.6 7 6 5 4 Vin= 115 Vac 3 Vin= 88 Vac 2 1 0.4 0 0.52 1.05 1.57 2.09 2.62 0 3.14 Line voltage phase angle (rad) Vin=264 Vac 0 0.52 1.05 1.57 2.09 2.62 3.14 Line voltage phase angle (rad) AM13306v1 AM13307v1 Due to the peak current vs. average current error which becomes much worse at low current levels (especially in DCM), the current that the boost PFC pre-regulator draws from the power line will not be exactly sinusoidal but will be affected by a distortion that will be lower as the current ripple in the boost inductor is smaller as compared to its peak value. Figure 9 and 10 show some theoretical waveforms, relevant to full load condition, in a line cycle at different input voltages. Figure 9. LM FOT controlled boost PFC: current waveforms (line current) Vin = 88 Vac Line current Inductor current (A) Line current (A) Vin = 88 Vac Figure 10. LM FOT controlled boost PFC: current waveforms (boost inductor current envelope) Vin = 190 Vac Vin = 264 Vac Vin = 230 Vac Line voltage phase angle (rad) rad) Boost inductor current envelope Vin = 264 Vac Line voltage phase angle (rad) AM13308v1 AM13309v1 In Figure 9 the line (input) current waveform is shown for different line voltages, while Figure 10 illustrates the envelope of the inductor current at minimum and maximum line voltage. The input current waveform relevant to Vin = 88 Vac shows no visible sign of distortion; the operation of the boost inductor is CCM throughout the entire line cycle as shown by the 8/43 DocID023523 Rev 2 AN4149 CCM PFC using FOT control inductor current envelope. The brown waveform is relevant to Vin=190 Vac, which is the condition where CCM operation no longer occurs at zero-crossings (this voltage value, for a given power level, depends on the inductance value of the boost inductor); a certain degree of distortion is already visible. The waveform relevant to Vin = 264 Vac shows the highest degree of distortion and the largest portion of the line cycle where the boost inductor operates in discontinuous mode (DCM). However, its harmonic content, shown in Figure 9 and 10, is still so low that is not an issue for EMC compliance. Almost all the distortion is concentrated in the third harmonic, whose amplitude is 17% of the fundamental one, while the THD is 17.7%. % Harmonic amplitude (normalized to fundamental) Figure 11. Line-modulated, FOT controlled boost PFC: input current harmonic contents Vin = 264Vac THD = 17.7% Harmonic order (n) AM13310v1 The compliance with conducted EMI emission regulations is also facilitated by the voltage ripple appearing across the output capacitor CO , at twice the line frequency fL, which has peak amplitude ΔVout proportional to the output current IOUT. As a consequence, fsw is not constant but is modulated at 2fL, spreading the spectrum of the electrical noise injected back into the power line. The relative frequency change due to the output voltage ripple is: Equation 11 Δf sw = f sw ΔVout Vout ΔVout 1+ Vout where ΔVout can be found with the following expression: Equation 12 ΔVout = Iout 4 π f L Cout DocID023523 Rev 2 9/43 Designing a CCM FOT-controlled PFC AN4149 2 Designing a CCM FOT-controlled PFC 2.1 Input specification The following is a possible design procedure for a CCM FOT-controlled PFC using the L4984D. This first part is a detailed specification of the operating conditions of the circuit that is needed for the calculations of the design steps in the following sections. In this example a 350 W wide-input range mains PFC circuit has been considered. Some design criteria are also given. Mains voltage range (Vacrms) : Equation 13 V A C m ax = 26 5V V A C m in = 9 0V Minimum mains frequency: Equation 14 f l = 47 H z Rated output power (W): Equation 15 Pout = 3 50 W Typically the output for a boost PFC output voltage is 400 Vdc as it has to be higher than the maximum rectified input voltage: Equation 16 2 ⋅V A C max In cases where the maximum AC input voltage VACmax is higher than 265 V, as typical in ballast applications, the output voltage must be set higher accordingly. As a rule of thumb the output voltage must be set 6 or 7% higher than the maximum input voltage peak. Regulated DC output voltage (Vdc): Equation 17 V out = 400 V The target efficiency and PF are set for the following calculations based on the operating condition of the PFC, here at minimum input voltage and maximum load. An efficiency of 92%, at minimum input voltage and maximum load, could be a starting point for a typical PFC. Expected efficiency (%): Equation 18 η= 10/43 Pout = 92% Pin DocID023523 Rev 2 AN4149 Designing a CCM FOT-controlled PFC Expected power factor: Equation 19 PF = 0 .99 Because of the narrow loop voltage bandwidth of the E/A to reject the ripple at twice the line frequency on the E/A output, the PFC output may experience overvoltage at startup or during load transients. In order to protect the controller from excessive output voltage that can overstress the output components and the load, in the L4984D a pin (PFC_OK, pin #6) has been dedicated to monitor the output voltage with a separate resistor divider. The divider is selected so that the voltage at the pin reaches 2.5 V if the output voltage exceeds a preset value (VOVP) larger than the maximum Vout that can be expected, also including worst-case load/line transients. Maximum output voltage (Vdc): Equation 20 V OVP = 430 V The output voltage has a ripple Vout at twice the line frequency (2fL), and whose amplitude is proportional to the load and depends on the impedance of the output capacitor. The ripple amplitude determines the AC current flowing into the output capacitor and the ESR. The value of the maximum output voltage ripple accepted should be below a certain level to keep the output voltage far from the VOVP limit during normal operating conditions, to increase hold-up time, and to reduce the AC losses on the output capacitor. The peak-topeak voltage ripple Vout is usually selected in the range between 2-8% of the output voltage. Here a ratio of 5% is chosen for the output voltage ripple, that is 20 V. Maximum output low frequency ripple (peak-to-peak): Equation 21 Δ V o u t = 20V The desired ripple on the output voltage is not the only parameter used to select the bulk capacitor. The hold-up time, if requested, should also be taken into account. The hold-up time is defined as the duration of time that a power supply's output will remain above a minimum level in case of mains dips. The hold-up time (tHold) is measured from the time when the line voltage disappears to the time when the output voltage reaches the required minimum voltage value (Voutmin). A holdup time of 10-20 ms is often required for today’s offline power supplies. Values of 300 V and 15 ms for the minimum output voltage after line drop and hold-up time, respectively, are chosen here: Minimum output voltage after line drop (Vdc): Equation 22 V out min = 300 V Hold-up time (ms): Equation 23 t Ho l d = 15 m s DocID023523 Rev 2 11/43 Designing a CCM FOT-controlled PFC AN4149 The design will be done on the basis of a maximum admitted ripple factor Kr , that is the ratio of the maximum peak-to-peak current ripple amplitude to the inductor peak current, at minimum line voltage and rated load. In the continuous conduction mode converters, the acceptable current ripple factor is typically fixed in a range between 20% and 35%. Low values for the Kr keep the peak-to-peak ripple current and the input current distortion low, but lead to larger inductor physical size. Choosing higher values for Kr , the inductor size can be smaller, but the input current distortion is increased. For this design, the maximum specified current ripple factor is chosen equal to 27%, as a trade-off between the inductor size and the input current distortion. Ripple factor: Equation 24 K r = 0 .2 7 In order to properly select the power components of the PFC and size the heat sinks, the maximum operating ambient temperature around the PFC circuitry must be known. Please note that this is not the maximum external operating temperature of the entire equipment, but it is the local temperature at which the PFC components are working. The power dissipation leading to a temperature rise combined with the ambient temperature must not result in any temperature exceeding the operating temperature rating of the components. Maximum ambient temperature ( °C): Equation 25 T ambx = 50 °C 2.2 Operating conditions The first step is to define the main parameters of the circuit, using the specifications given in Section 2.1. Rated DC output current: Equation 26 I out = Pout V out I ou t = 350W = 0 . 875 A 400V Maximum input power: Equation 27 Pin = 12/43 Pout Pin = η DocID023523 Rev 2 350 W ⋅ 100 = 380 .4 W 92 AN4149 Designing a CCM FOT-controlled PFC The maximum value of the RMS current circulating in the boost cell at the minimum line voltage of the selected range is equal to: Maximum RMS input current: Equation 28 I in = Pin I in = VAC m in ⋅ PF 380 .4W = 4 .27 A 90Vac ⋅ 0 .99 In order to describe the energy and relevant equations concerning a boost PFC, the ratios of the voltage inputs of the boost converter to the regulated output voltage are defined. In particular kmin and kmax refer to the ratio of the minimum and the maximum input voltage to the output voltage, respectively. Equation 29 k min = 2 VAC min V out k m ax = 2 90Vac = 0 . 32 400V k max = 2 VAC max V out k max = 2 2 65Vac = 0 .94 400V Combining equation 28 and equation 29 the maximum line peak current can be found. Maximum line peak current: Equation 30 I P K max = 2 ⋅ Pin I P K max = k m in ⋅ V out 2 ⋅ 380 .4W = 5 .98 A 0 .32 ⋅ 400V Maximum inductor peak current: Equation 31 IL PK max = K 2 ⋅ Pin ⋅ 1 + r V AC min ⋅ PF 2 IL P K max = 2 ⋅ 380 .4W 0 .27 ⋅ 1 + = 6 .8 5 A 90V ⋅ 0 .99 2 Inductor peak-to-peak ripple current : Equation 32 Δ IL PK max = K r ⋅ IL P K max ΔIL PK ma x = 0 .27 ⋅ 6 .85 A = 1 .85 A In order to calculate the losses of the switches, the RMS current flowing through the MOSFET and through the boost output diode are found. Maximum RMS switch current: DocID023523 Rev 2 13/43 Designing a CCM FOT-controlled PFC AN4149 Equation 33 Pin ISW rm s = ISW rm s = 2 ⋅ V AC min ⋅ PF 38 0 .4W 2 ⋅ 90V ⋅ 0 .99 ⋅ 2− ⋅ 2− 1 6 ⋅ k min 3π 16 ⋅ 0 .318 = 3 .65 A 3π Maximum RMS diode current: Equation 34 IDr m s = ID rms = Pin 2 ⋅ V A C min ⋅ PF 380.4W 2 ⋅ 90V ⋅ PF ⋅ ⋅ 1 6 ⋅ k min 3π 16 ⋅ 0.32 = 2.22 A 3π It is worth reminding that the accuracy of the equations developed here is quite good at low line voltage and worsens at high line and as the power throughput is reduced. As the current stresses of the switches are calculated at maximum load and minimum line voltage, the previous expressions are acceptable for design purposes. 2.3 Power section design 2.3.1 Bridge rectifier The input rectifier bridge can use standard slow recovery, low-cost devices. Typically a 600 V device is selected in order to have good margin against mains surges. An NTC resistor limiting the current at turn-on is required to avoid overstressing the bridge diodes. The rectifier bridge power dissipation can be calculated starting from the input RMS current and the input average current through the bridge diodes. Equation 35 I in _ rm s _ b ri d ge = 2 ⋅ I in = 2 2 ⋅ 4 . 36 A = 3 . 02 A 2 2 ⋅ I in 2 ⋅ 4 . 36 A Equation 36 I in _ avg _ b ri dg e = π = π = 1 . 92 A The power dissipated on a D15XB60 bridge can be estimated combining equation 35 and equation 36 with the threshold voltage (Vth) and dynamic resistance (Rdiode) of a single diode of the bridge, the values of which can be found in the datasheet of the diode. Equation 37 Pbridge = 4 ⋅ R diode ⋅ I 2 inrms + 4 ⋅V th ⋅ I in _ avg Pbridge = 4 ⋅ 0 .025 Ω ⋅ (3 .02 A) 2 + 4 ⋅ 0 .7V ⋅ 1 .92 A = 6 .29 W 14/43 DocID023523 Rev 2 AN4149 Designing a CCM FOT-controlled PFC From this number and the given maximum ambient temperature Tambx the total maximum thermal resistance required to keep the junction temperature below 125 °C is: Equation 38 R th = 2.3.2 125 °C − T a m b x P b r id g e R th = 125 ° C − 50 ° C °C = 11 . 92 6 . 29W W Input capacitor The input filter capacitor, Cin, is placed across the output of the bridge diodes. This capacitor must smooth the high-frequency ripple and must sustain the maximum instantaneous input voltage. In a typical application an EMI filter is placed between the mains and the PFC circuit. In this application the EMI filter is reinforced by a differential mode Pi-filter after the bridge to reject the differential noise coming from the whole switching circuit. The design of the EMI filters (common mode and differential mode) is not described here. For wide-range operation the minimum value of the input filter capacitor can be calculated as follows, using a practical formula based on the output power that the PFC delivers at full load: Equation 39 C in = 2 . 5 ⋅ 10 −3 ⋅ μF W C in = 2 . 5 ⋅ 10 − 3 ⋅ ⋅ Pout μF W ⋅ 350W = 875 nF The maximum value of this capacitor has to be not much higher than the minimum value to avoid the distortion of the input mains current, due to the residual voltage retained by the capacitor that causes the diodes of the bridge rectifier to be reverse-biased and the input current flow to temporarily stop. The selected value for the input filter capacitor of this design is 1 μF. 2.3.3 Output capacitor The output bulk capacitor (CO) selection depends on the regulated DC output voltage, the output power, the RMS current into the capacitor, the output voltage ripple and hold-up time (if requested). The value of the output capacitor to meet the output voltage ripple requirements can be defined using the following expression (equation 40). ΔVout has to be intended as twice the mains frequency peak-to-peak voltage ripple, function of the capacitor impedance and the peak capacitor current. The contribution of the ESR (equivalent series resistance) is neglected here as the capacitive reactance is dominant. Equation 40 Co ≥ I ou t Pou t = 2 π ⋅ f l ⋅ Δ V ou t 2 π ⋅ f l ⋅ V o u t ⋅ Δ V o ut Co ≥ 350 W = 148 . 1μ F 2π ⋅ 47 Hz ⋅ 400 V ⋅ 20V where fl is the minimum line frequency. Although ESR usually does not affect the output ripple, it should be taken into account for power loss calculation. The total capacitor RMS ripple current, including the mains frequency and switching frequency components, is: DocID023523 Rev 2 15/43 Designing a CCM FOT-controlled PFC AN4149 Equation 41 I Crms = I Crms = ID 2 rms − I 2 out (2. 22 A ) 2 − ( 0 .87 A ) 2 = 2 .04 A Reading the ESR value of the datasheet of the output capacitor chosen, the power losses associated to this ripple current can be easily calculated by: Equation 42 PCrms = I Crms ⋅ ESR 2 If the PFC stage has to guarantee a specified hold-up time, the calculation of the output capacitor is different. The value of the capacitor when the line voltage drops out, needed to deliver the output power for a certain time (tHold) until the output voltage reaches the required minimum voltage value (Voutmin), depends on the load and the value of the ripple. When Voutmin is reached, a 'power fail' is detected, stopping the downstream system supplied by the PFC. The worst case for the hold-up time is at minimum input voltage and full load, with the line drop starting at the valley of the sine-varying ripple of the output voltage. Equation 43 Co = 2 ⋅ Pout ⋅ t H old Co = 2 Δ V out 2 − V out min V out − 2 2 ⋅ 350 W ⋅ 15 ms (400 V − 10V )2 − (300V )2 = 169 μ F Considering a 20% tolerance on the electrolytic capacitors, a value of 200 μF has been chosen, using two capacitors of commercial value of 100 μF placed in parallel. The actual hold-up time and ripple voltage with the selected value are: Actual hold-up time: Equation 44 t Hold t Hold = 2 ΔVout 2 Co ⋅ Vout − − Vout min 2 = 2 ⋅ Pout [ ] 200 μF ⋅ (400V − 10V )2 − (300V )2 = 18 ms 2 ⋅ 350W Peak-to-peak output voltage ripple: Equation 45 Δ V out = 2.3.4 I out 2 ⋅ π ⋅ f l ⋅ Co Δ V out = 0 . 87 A = 14 . 81V 2 ⋅ π ⋅ 47 Hz ⋅ 200 μ F Boost inductor As indicated in the specs in Section 2.1: Input specification, the maximum current ripple factor Kr , that is the ratio of the maximum peak-to-peak current ripple amplitude to the 16/43 DocID023523 Rev 2 AN4149 Designing a CCM FOT-controlled PFC inductor peak current at minimum line voltage and rated load, is 27%, as a trade-off between the inductor size and the stress on the switches. This choice led to the inductor peak-to-peak ripple current (ILPK) equal to 1.89 A (equation 32). The value of the inductance L required for the boost inductor can be calculated starting from the volt-second balance of the inductor. The minimum value of L is then a function of the duration of the OFF-time, the voltage across the inductor during TOFF, and the inductor peak-to-peak ripple current. Equation 46 L= V out − 2 ⋅ V AC ⋅ TOFF (V AC ) Δ IL pk (V AC ) The latter expression should be calculated at low line and the value found is the minimum inductance value of the PFC inductor. To find the value of L, first TOFF needs to be calculated. In a fixed-off-time control using the L4984D, the off-time (TOFF) is changed proportionally to the instantaneous line voltage in order to make the switching frequency (fSW) constant. The switching frequency is determined by a capacitor connected between the TIMER pin and ground, charged by an accurate internal generator (ITIMER) of 156 μA (typ.), during the OFFtime, generating a voltage ramp. When the voltage ramp equals the voltage on the MULT pin, connected through a resistive divider to the rectified mains to get a sinusoidal voltage reference, the OFF-time of the power MOSFET is terminated, the gate driver (GD) pin is driven high and the ramp resets at zero. The timing capacitor CT is then selected with the following formula: Equation 47 CT = I TIM ER k p ⋅ V out ⋅ f SW where fsw is the switching frequency and kp the maximum required divider ratio, calculated considering the maximum value of the multiplier input, that is, the voltage measured on the MULT pin at maximum mains voltage. According to the datasheet of the L4984D, the linear operating range is between 0 to 3 V, so the maximum value of the multiplier input (VMULTmax) is equal to 3 V. The maximum required divider ratio kp can be now found as: Equation 48 kp = V MULT max 2 ⋅ VA C max = 3 . 00V = 8 ⋅ 10 − 3 2 ⋅ 265 Vac DocID023523 Rev 2 17/43 Designing a CCM FOT-controlled PFC AN4149 The switching frequency chosen for this design is around 70 kHz, so the capacitor on the TIMER pin needed to obtain the desired frequency is (equation 47): Equation 49 CT = 8 ⋅1 0 −3 1 56 μ A = 6 95 pF ⋅ 40 0 V ⋅ 70 kH z A commercial value of 680 pF has been selected. An NP0 capacitor has to be used. Now TOFF can be finally calculated. Along a line half-cycle, TOFF varies from nearly zero to the maximum value, occurring at the MULT peak voltage. To calculate the boost inductor the value at the MULT peak should be considered, found simply from the product of the maximum required divider ratio kp and the peak of the rectified input voltage at low mains voltage (Vpkmin). The maximum OFF-time at VACmin is then: Equation 50 T OFF (V AC min ) = 680 pF ⋅ 8 ⋅ 10 −3 ⋅ 2 ⋅ 90V = 4 .4 μ s 156 μ A The value of the inductance L required for the boost inductor at VACmin can now be calculated with equation 46. Equation 51 L (VAC min ) = L (VAC min ) = Vout − 2 ⋅ V AC min ⋅ TOFF (V AC min ) ΔIL pk (V AC min ) 400V − 2 ⋅ 90V ⋅ 4 .4 μ s = 654 μ H 1 .85 A The value chosen for the inductor is 700 μH. 2.3.5 Power MOSFET selection and power dissipation calculation The selection of the MOSFET concerns mainly RDS(on), that should be low in order to minimize conduction losses, without increasing the switching losses due to the MOSFET 's equivalent output capacitance Coss. To achieve high efficiency both RDS(on) and Coss have to be taken into account, and the trade-off between cost vs. performance must also be considered. The MOSFET breakdown voltage is needed, considering the PFC nominal output voltage and adding some margin (20%) to guarantee reliable operation. Therefore, a minimum voltage rating of 500 V (1.2 · Vout = 480 V) is selected. In this 350 W CCM PFC application, two STF21N65M5 (placed in parallel) have been chosen, to improve robustness against surges and burst tests, and 650 V MOSFETs have been chosen, having a good balance between RDSon and Coss. In order to calculate the contribution of the MOSFETs to the total efficiency of the system, the power losses have been calculated, which are mainly the sum of the conduction, switching and capacitive losses. 18/43 DocID023523 Rev 2 AN4149 Designing a CCM FOT-controlled PFC The conduction losses at maximum load and minimum input voltage are calculated by: Equation 52 Pcond (VAC ) = RDS on ⋅ (ISW rms (VAC ) ) 2 Because normally in a MOSFET datasheet RDS(on) is given at ambient temperature (25 °C), in order to properly calculate the conduction losses at 100 °C (typical MOSFET junction operating temperature), a factor KTEMP between 1.5 to 2, which can be found in the device datasheet, should be taken into account. In the case of the STF21N65M5, looking at the normalized ON resistance vs. temperature graph, a factor of 1.7 should be considered at 100 °C. Equation 53 R DSon _@ 100°C = RDS on _@ 25 °C Num _ of _ paralleled _ MOSFETs ⋅ K TEMP = 0 .179 Ω ⋅ 1 .7 = 0 .152 Ω 2 where the RDSon value is divided by two since two MOSFETs are placed in parallel. The maximum RMS switching current, at minimum VAC, has been found from equation 33. Now, from equation 52 and equation 53, and considering that two MOSFETs in parallel have been used, the maximum conduction losses at low line and full load can be calculated as: Equation 54 Pcond (VAC ) = R DSon _@ 100 ° C ⋅ (ISW rms (VAC ) )2 Pcond (90V ) = 0 . 152 Ω ⋅ (3 . 65 A ) = 2 . 02 W 2 The switching losses are difficult to predict as they depend on the particular switching waveform, determined by many factors (driving current, gate resistors, MOSFET gate internal resistance, Vth, gate charge, total capacitance on the drain node including parasitic capacitances etc.). A good approximation to determine the generic switching losses due to the MOSFET commutation occurring at turn-on and turnoff can be basically expressed by: Equation 55 Psw (VAC ) = 1 ⋅ V DS ⋅ I D ⋅ (t rise + t fall )⋅ f sw 2 where VDS is the drain-to-source of the MOSFET, ID the average drain current and trise and tfall refer to the rising and the falling edge of VDS . To estimate the rising and falling times of the drain voltage, datasheet values of the switching performance of the MOSFET can be used. First the average rising times of the drain voltage can be calculated considering the total drain node capacitance and the average value of the peak current flowing through the inductor. DocID023523 Rev 2 19/43 Designing a CCM FOT-controlled PFC AN4149 The exact value of the MOSFET's COSS is indicated in the datasheet looking at the graph representing COSS vs. VDS. At VDS equal to 400 V, COSS is 40 pF. This value should be multiplied by two as two MOSFETs have been used in parallel, and adding a rough 100pF of all other contributions, CD can be found: Equation 56 C D = 2 ⋅ C OSS + C stray = 2 ⋅ 40 pF + 100 pF = 180 pF Then the average rising time of the drain voltage is: Equation 57 t rise = C D ⋅ V DS C D ⋅ V DS = ≈ 17 ns π ID 1 ⋅ IL pk max π 0 However, the average falling time depends on the driving current IG (limited by the resistor placed on the gate), the MOSFET's total gate charge QG and the driving voltage Vdr, supposed here equal to VCC (for example, 15 V) applied for simplicity. In the resistor calculation the intrinsic gate resistance should also be considered. In the case of the STF21N65M5, RG is 2.5 Ω which has to be added to the externally placed resistor RGext (3.3 Ω in this design). Equation 58 t Cfall = QG = IG QG 50 nC = ≈ 19 ns V dr 15V R Gext + R G 3 .3Ω + 2 .5 Ω Finally, the MOSFET’s switching losses can be estimated with equation 55: Equation 59 PSW (90 V ) = 1 ⋅ 400 V ⋅ 4 .36 A ⋅ (17 ns + 19 ns )⋅ 70 kHz = 2 .2W 2 To estimate the capacitive losses, that is, the losses due to the discharge of the total drain capacitance through the MOSFET at turn-on, this simple expression can be considered: Equation 60 Pcap (VAC ) = Pcap (90V ) = 20/43 1 2 ⋅ C D ⋅ V DS ⋅ f sw (VAC ) 2 1 2 ⋅ 180 pF ⋅ (400 V ) ⋅ 70 kHz = 1W 2 DocID023523 Rev 2 AN4149 Designing a CCM FOT-controlled PFC The MOSFET total losses at minimum input voltage (VACmin) is the sum of the three previous losses from equation 54, equation 55, and equation 60: Equation 61 Ploss (VAC ) = Pcond (VAC ) + Psw (VAC ) + Pcap (VAC ) Ploss (90V ) = 2 .02W + 2 .2W + 1W = 5 .23W From equation 61, using the data relevant to the MOSFET selected, it can be observed that the maximum total losses, occurring at VACmin and full load, is around 5 W. From this number and the given maximum ambient temperature, the total maximum thermal resistance required to keep the MOSFET's junction temperature below 125 °C is: Equation 62 R th = 125 °C − T ambx Ploss (VAC ) R th = 125 °C − 50 °C °C = 14 . 3 5 . 23W W As the result of equation 62 is much lower than the junction-ambient thermal resistance given in the MOSFET datasheet for the selected device package (62.5 °C/W), a heatsink must be used. Figure 12 shows the trend of the total losses on the line voltage for the two selected STF21N65M5 MOSFETs. Figure 12. Total MOSFETs losses in the 350 W FOT PFC Power losses vs Input voltage (full load) 6 MOSFET losses (W) 5 4 3 2 1 0 80 100 120 140 160 180 Input voltage (Vac) 200 220 240 260 Conduction losses Switching losses Capacitive losses Total losses AM13311v1 DocID023523 Rev 2 21/43 Designing a CCM FOT-controlled PFC 2.3.6 AN4149 Boost diode selection Following criteria similar to those used for the calculation of the MOSFET losses, the output rectifier can be properly selected. A minimum breakdown voltage of 1.2·(Vout) and a minimum current rating higher than 5·Iout (equation 26) can be considered for an initial rough selection of the rectifier. The correct selection is then confirmed by the thermal calculation, as the diode junction temperature must be below 125 °C. Since this circuit operates in the continuous current mode, reverse recovery is experienced by the diode, and the MOSFET at turn-on has to carry also the boost diode minority carrier charge. Then, to minimize the recovery losses, an ultra-fast diode with low trr (reverse recovery time, the time required to deplete the stored charge) and Qrr (reverse recovery charges, the charge that must be dissipated on the MOSFET) or a SiC rectifier has to be selected. In this 350 W application the STTH8S06 (600 V, 8 A) has been selected and shows very fast reverse recovery time, 12 ns typical (measured for IF =1 A). The rectifier AVG (equation 26) and RMS (equation 33) current values, the Vth (rectifier threshold voltage) and Rd (dynamic resistance) given in the datasheet allow calculating the rectifier losses. From the STTH8S06 datasheet, Vth is 1.2 V, and Rd is 0.087 Ω, the conduction losses are equal to: Equation 63 Pdiode = Vth ⋅ I out + Rd ⋅ ID 2 rms Pdiode = 1.2V ⋅ 0.87 A + 0.087 Ω ⋅ (2.22 A ) = 1.48W 2 Since the converter is working in continuous conduction mode the losses in the MOSFETs due to the recovery of the boost diode have to be taken into account. The energy loss due to the reverse recovery effect of the diode is: Equation 64 E rr = V R ⋅ Q rr Where VR is the reverse voltage across the output diode, when it stops conducting, that is 400 V, and Qrr the reverse recovery charges, the charge that must be dissipated through the MOSFET. On the datasheet the graph of Qrr vs. dIF/dt is represented. Following the 0.5 xIF(AV) curve at Tj = 125 °C a value of 80 nC is found assuming the typical case of 200 A/us. Then the recovery energy is: Equation 65 E rr = 400 V ⋅ 80 nC = 32 μ J And the reverse recovery losses are: Equation 66 Prr = E rr ⋅ f sw = 32 μ J ⋅ 70 kH z = 2 . 24W 22/43 DocID023523 Rev 2 AN4149 Designing a CCM FOT-controlled PFC If a single heatsink for the MOSFETs and diode is used, the maximum total losses of the switches should be considered: Equation 67 Pswitch = Ploss (90 V ) + Pdiode ( 90V ) + Prr = 5 .84 W + 1 .48 W + 2 .24 W = 9 .56 W From this number and the given maximum ambient temperature, the total maximum thermal resistance required can be found as: Equation 68 R th = 125 °C − T ambx Pswitch R th = 125 °C − 50 °C °C = 7 .85 9 .56W W In this design in order to keep the junction MOSFET temperature below 100 °C (around 90 °C measured on the package) and to ensure a higher degree of reliability, the thermal resistance has been chosen equal to: Equation 69 R th = 100 °C − 50 °C °C = 5 .23 W 9 .57 W DocID023523 Rev 2 23/43 L4984D biasing circuitry 3 AN4149 L4984D biasing circuitry The following sections describe the selection of the circuitry around the L4984D. 3.1 Feedback and OVP Pin 1 (INV): this pin is connected both to the inverting input of the E/A and to the OVP circuitry. A resistive divider has to be connected between the boost regulated output voltage and this pin. The internal reference on the non-inverting input of the E/A is 2.5 V (typ.), the output voltage (Vout) of the PFC pre-regulator is set at the nominal value by the resistor ratio of the feedback output divider. RoutH and RoutL will be then selected considering the desired nominal output voltage and the desired output power dissipated on the output divider. For example for a 25 mW output divider dissipation: Equation 70 R outH = (V out − 2 .5V ) 25 mW 2 R outH = (400 V − 2 .5V )2 = 6 .320 M Ω 25 mW Please note that for RoutH a resistor with a suitable voltage rating (> 400 V) is needed, or more resistors in series have to be used. Here three 2.2 MΩ resistors in series have been selected. Equation 71 R outH 400V = − 1 = 159 RoutL 2 .5V R outH V = out − 1 R outL 2 .5V Equation 72 R outL = V out 159 R outL = 6 .6 M Ω = 39 .7 kΩ 159 For RoutL a value of 160 kΩ in parallel to a 56 kΩ has been selected. Pin 2 (COMP): this pin is the output of the E/A that is fed to one of the inputs of the multiplier. A feedback compensation network is placed between this pin and INV. It has to be designed in with a narrow bandwidth in order to avoid that the system rejects the output voltage ripple (100 Hz) that would bring high distortion of the input current waveform. A theoretical criterion to define the compensation network value is to set the E/A bandwidth (BW) below 20 Hz. The compensated two-pole feedback network selection for this 350 W FOT PFC has been described in detail in Section 4: FOT PFC boost control loop. Pin 6 (PFC_OK - Feedback failure protection): PFC_OK pin has been dedicated to monitor the output voltage of a separate resistor divider. This divider is selected so that the voltage at the pin reaches 2.5 V if the output voltage exceeds a preset value (Vovp), usually larger than the maximum Vout that can be expected, also including worst-case load/line transients. For a maximum output voltage Voutmax of 430 V and selecting a 50 μA current flowing in to the divider: 24/43 DocID023523 Rev 2 AN4149 L4984D biasing circuitry Equation 73 RL = V REF _ PFC _ OK RL = I divider 2 .5V = 50 k Ω 50 μ A By selecting a commercial value of 56 kΩ: Equation 74 V OUT _ MAX RH = R L ⋅ − 1 V REF _ PFC _ OK 430V R H = 56 k Ω ⋅ − 1 = 9 . 623 M Ω 2 . 5 V Three resistors 3.3 MΩ in series provide the calculated value for the PFC_OK high resistor. Notice that both feedback dividers connected to the L4984D pin #1 (INV) and pin #6 (PFC_OK) can be selected without any constraints. The unique criterion is that both dividers have to sink a current from an output bus which needs to be significantly higher than the current biasing the error amplifier and the PFC_OK comparator. The OVP function handles "normal" overvoltage conditions, i.e. those resulting from an abrupt load/line change or occurring at startup. In case the overvoltage is generated by a feedback failure, for instance when the upper resistor of the output divider (R1) fails open, eventually the error amplifier output (COMP) will saturate high and the voltage on its inverting input (INV) will drop from its steady-sate value (2.5 V). An additional comparator monitors the voltage on pin INV, comparing it against a reference located at 1.66 V. When the voltage on pin PFC_OK exceeds 2.5 V and, simultaneously, the voltage on pin INV falls below 1.66 V, the FFD function is triggered: the gate drive activity is immediately stopped, the device is shut down and its quiescent consumption reduced. This condition is latched and in order to restart the L4984D it is necessary to recycle the input power, so that the Vcc voltage falls below 6 V (VCCrestart). The pin PFC_OK doubles its function as a non-latched IC disable: a voltage below 0.23 V shuts down the L4984D, reducing its consumption below 2.2 mA. To restart simply let the voltage on the pin rise above 0.27 V. Note that these functions offer complete protection against not only feedback loop failures or erroneous settings, but also against a failure of the protection itself. Either resistor of the PFC_OK divider failing short or open or a pin PFC_OK floating will result in shutting down the L4984D and stopping the pre-regulator. DocID023523 Rev 2 25/43 L4984D biasing circuitry 3.2 AN4149 Current sense resistor Pin 4 (CS): The pin #4 is the inverting input of the current sense comparator. Through this pin, the L4984D senses the instantaneous inductor current, converted in a proportional voltage by an external sensing resistor (RS). As this signal crosses the threshold set by the multiplier output, the PWM latch is reset and the power MOSFET is turned off. The threshold is defined by: Equation 75 V CS = V CS _ OFF SE T + k m ⋅ (V COM P − 2 . 5V ) ⋅ V MU LT V F2F where: – VCS (multiplier output) is the reference for the current sense (VCS_OFFSET is its offset). – km=0.23 (typ.) is the multiplier gain. – VCOMP is the voltage on pin 2 (E/A output). – VMULT is the voltage on pin 3. – VFF is the second input to the multiplier for 1/V2 function. It compensates the control loop gain dependence on the mains voltage. The voltage at this pin is a DC level equal to the peak voltage on pin MULT (pin 3). The sense resistor value (RS) can be calculated as follows. For the 350 W PFC it will be: Equation 76 Rs < 0 .84 V = 0 .12 Ω 7 .0 A Where: – ILpk is the maximum peak current in the inductor, calculated with – Vcsm in = 0.84 V is the minimum value of the L4984D current sense reference clamp (VCSclamp in the datasheet). According to the result, three parallel resistors of 0.33 Ω with 1 W of power rating have been selected. Because the internal current sense clamping sets the maximum current that can flow in the inductor, the maximum peak of the inductor current will be calculated considering the maximum Vcsclamp admitted on the L4984D: Equation 77 IL pkx = 0 .93 V = 8 .45 A 0 .11 Ω The calculated ILpkx will be the value at which the boost inductor shall not saturate and it will be used for calculating the inductor number of turns and air gap length. The power dissipated by RS is given by: Equation 78 Ps = 0 .11Ω ⋅ (3 .73 ) = 1 .53W 2 2 Ps = R s ⋅ ISW rms 26/43 DocID023523 Rev 2 AN4149 Mult divider and VFF Pin 3 (MULT): the MULT pin is the second multiplier input. It will be connected, through a resistive divider, to the rectified mains to get a sinusoidal voltage reference. Figure 13. Multiplier characteristics family for VFF = 1 V Figure 14. Multiplier characteristics family for VFF = 3 V 500 1.2 VCOMP VCOMP 1.1 450 VFF = 3 V 1.0 400 Upper voltage clamp Upper Voltage 0.9 5.5 V 350 0.8 5.5 V 5.0 V 300 4.5 V 0.6 0.5 Vcs (mV) 0.7 Vcs (V) 3.3 L4984D biasing circuitry 4.0 V 5.0 V 250 4.5 V 200 0.4 3.5 V 4.0 V 150 0.3 3.5 V 100 0.2 3.0 V 3.0 V 50 0.1 2.6 V 2.6 V 0 0.0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 0 0.5 1 1.5 2 2.5 3 3.5 VMULT (V) VMULT (V) AM13313v1 AM13314v1 A complete illustration is given by the diagrams of Figure 13 and Figure 14 which show the typical multiplier characteristics family. The linear operation of the multiplier is guaranteed within the range 0 to 3 V of VMULT and the range 0 to 0.82 V (typ.) of Vcs, while the minimum guaranteed value of the maximum slope of the characteristics family (typ.) is: Equation 79 dV CS V = 1 .4 dV MULT V The voltage on the MULT pin is used also to derive the information on the RMS mains voltage for the VFF compensation and the brownout function: Pin 5 (VFF): the power stage gain of PFC pre-regulators varies with the square of the RMS input voltage. This applies as well to the crossover frequency fc of the overall open-loop gain because the gain has a single pole characteristic. This leads to large trade-offs in the design. For example, setting the gain of the error amplifier to get fc = 20 Hz at 264 Vac means having fc about 4 Hz at 88 Vac, resulting in sluggish control dynamics. Additionally, the slow control loop causes large transient current flow during rapid line or load changes that are limited by the dynamics of the multiplier output. This limit is considered when selecting the sense resistor to let the full load power pass under minimum line voltage conditions, with some margin. But a fixed current limit allows excessive power input at high line, whereas a fixed power limit requires the current limit to vary inversely with the line voltage. Voltage feed-forward can compensate for the gain variation with the line voltage and allow overcoming all of the above-mentioned issues. It consists of deriving a voltage proportional to the input RMS voltage, feeding this voltage into a squarer/divider circuit (1/V2 corrector) and providing the resulting signal to the multiplier that generates the current reference for the inner current control loop. DocID023523 Rev 2 27/43 L4984D biasing circuitry AN4149 In this way a change of the line voltage will cause an inversely proportional change of the half sine amplitude at the output of the multiplier (if the line voltage doubles, the amplitude of the multiplier output will be halved and vice versa) so that the current reference is adapted to the new operating conditions with (ideally) no need for invoking the slow dynamics of the error amplifier. Additionally, the loop gain will be constant throughout the input voltage range, which improves significantly dynamic behavior at low line and simplifies loop design. Actually, with other PFC embedding the voltage feed-forward, deriving a voltage proportional to the RMS line voltage implies a form of integration, which has its own time constant. If it is too small, the voltage generated will be affected by a considerable amount of ripple at twice the mains frequency that will cause distortion of the current reference (resulting in high THD and poor PF). If it is too large, there will be a considerable delay in setting the right amount of feed-forward, resulting in excessive overshoot and undershoot of the pre-regulator's output voltage in response to large line voltage changes. Clearly a tradeoff was required. The L4984D implements an innovative voltage feed-forward which, with a technique that makes use of just two external parts, overcomes this time constant trade-off issue whichever voltage change occurs on the mains, both surges and drops. A capacitor CFF and a resistor RFF, both connected from the pin VFF (pin #5) to ground, complete an internal peak-holding circuit that provides a DC voltage equal to the peak of the rectified sine wave applied on pin MULT (pin #3). In this case following values have been selected: Equation 80 C FF = 1μF R FF = 1M Ω In this way, in case of sudden line voltage rise, CFF will be rapidly charged through the low impedance of the internal diode. In case of line voltage drop, an internal "mains drop" detector enables a low impedance switch which suddenly discharges CFF avoiding a long settling time before reaching the new voltage level. Consequently, an acceptably low steady-state ripple and low current distortion can be achieved without any considerable undershoot or overshoot on the preregulator's output like in systems with no feed-forward compensation. This pin is internally connected to a comparator in order to provide the brownout (AC mains undervoltage) protection. A voltage below 0.8 V shuts down (does not latched) the L4984D and brings its consumption to a considerably lower level. The L4984D restarts as the voltage at the pin rises above 0.88 V. These data have to be considered during the MULT divider selection, setting the minimum operating voltage. Please find here following the procedure to set properly the operating point of the multiplier and the divider resistor values. Supposing a 60 uA (IMULT) current flowing into the multiplier divider, the lower resistor value can be calculated: Equation 81 RmultL = VMULT max 3.00V = = 50 kΩ I MULT 60μA A commercial value of 51 kΩ for the lower resistor is selected. The upper resistor value can now be calculated: Equation 82 R multH = 28/43 1− kp kp ⋅ R multL = 1 − 8 ⋅ 10 −3 ⋅ 56 kΩ = 6 .944 M Ω 8 ⋅ 10 −3 DocID023523 Rev 2 AN4149 L4984D biasing circuitry In this application example a RmultH = 6.9 MΩ and a RmultL = 51 kΩ have been selected. Please note that for RmultH a resistor with a suitable voltage rating (> 400 V) is needed, or more resistors in series will have to be used. The voltage on the multiplier pin with the selected component values re-calculated at minimum line voltage is 0.93 V and at maximum line voltage is 2.74 V, so the multiplier will work correctly within its linear region. Finally, depending on the MULT resistors the brownout functions also have to be checked, calculating the VSTART and VSTOP voltages: Equation 83 0 .88 V V START = 2 ⋅ R multH + R multL R multL V START = 0 .88V ⋅ R multH + R multL R multL V STOP = 0 .80V 2 ⋅ 6 .9 M Ω + 56 k Ω = 77 .29V 56 k Ω ⋅ 6 .9 M Ω + 51 kΩ = 70 .2V 51 k Ω Equation 84 V STOP = 0 .80 V 2 2 Start and stop PFC voltages are suitable for correct operation by the PFC; the MULT divider has to be set considering these two voltages, in order to disable the PFC with an anomalous input low mains voltage that could cause an overheating of the PFC due to the higher input mains current. In order to set the required voltage startup threshold reiterations could be required by selecting MULT resistors and checking the actual PFC start voltage. 3.4 Gate driver (GD) and VCC pins Pin 8 (GND): this pin acts as the current return both for the signal internal circuitry and for the gate drive current. When laying out the printed circuit board, these two paths should run separately. Pin 9 (GD): is the output of the driver. The pin is able to drive an external MOSFET with 600 mA source and 800 mA sink capability. The high-level voltage of this pin is clamped at about 12 V to avoid excessive gate voltages in case the pin is supplied with a high Vcc. To avoid undesired switch-on of the external MOSFET because of some leakage current when the supply of the L4984D is below the UVLO threshold, an internal pull-down circuit holds the pin low. The circuit guarantees 1.1 V maximum on the pin (at Isink=2mA), with Vcc > VCC_ON. This allows omitting the "bleeder" resistor connected between the gate and the source of the external MOSFET used for this purpose. Pin 10 (VCC): is the supply of the device. This pin will be externally connected to the startup circuit (usually, one resistor connected to the rectified mains) and to the self-supply circuit. Whatever the configuration of the self-supply system, a capacitor will be connected between this pin and ground. To start the L4984D, the voltage must exceed the startup threshold (12 V typ.). Below this value the device does not work and consumes around 65 µA (typ.) from VCC. This allows the use of high value startup resistors (in the hundreds of kΩ), which reduces power consumption and optimizes system efficiency at low load, especially in widerange mains applications. When operating, the current consumption (of the device only, not considering the gate drive current) rises to a value depending on the operating conditions but never exceeding 6 mA. The device keeps on working as long as the supply voltage is over the UVLO threshold (13 V max). If the VCC voltage exceeds 22.5 V, an internal Zener DocID023523 Rev 2 29/43 FOT PFC boost control loop AN4149 diode, 20 mA rated, will be activated in order to clamp the voltage. Please remember that during normal operation the internal Zener will not have to clamp the voltage, because in that case the power consumption of the device will increase considerably and its junction temperature will also increase. The recommended operating condition for safe operation of the device is below the minimum clamping voltage of the pin. 4 FOT PFC boost control loop In order to find a compensation network ensuring stability over a large variety of operating conditions and to prevent dangerous oscillations of the output voltage as a result of load changes, it is necessary to have a correct understanding of the control loop of FOT PFC systems. The loop gain of PFC pre-regulators must have a very low crossover frequency (fc) so as to keep VCOMP (error amplifier output) fairly constant over a given line cycle, filtering twice the line frequency ripple on the output of the error amplifier, in order to ensure low THD (total harmonic distortion). As a rule of thumb, fc should not exceed 20 Hz. The small signal model of a PFC stage with a constant power load (the regulated DC-DC converter) can be represented as a controlled current source delivering power to the output capacitor. Figure 15. Small signal model of a PFC stage with a constant-power load (DC-DC converter) Io Co Vo AM13315v1 The current generator: îo is controlled by the small-signal AC control voltage: v̂c and the system acts as a pure integrator and the resulting control-to-output transfer function is: Equation 85 v̂ o G = G ( jω ) = o v̂ c jω 30/43 DocID023523 Rev 2 AN4149 FOT PFC boost control loop where the unity gain factor Go is given by the following expression regardless of the control method and the characteristics of the control IC: Equation 86 Go = V out Pout ⋅ (V C − V C 0 ) ⋅ C o In the previous expression Vc is the error signal of the voltage control loop (voltage on the COMP pin for the L4984D), that is, the output of the error amplifier, and VCO the "zeropower" level of the control voltage, that is, the burst mode threshold of COMP voltage (2.4 V, typ.). The effective control voltage Vcomp - VC0, can be expressed for the L4984D starting from the expression of the variation of signal out from the modulator with respect to the E/A output (COMP) change, using the formula indicated in the datasheet of the L4984D (equation 87). Equation 87 V CS = VCS _ OFFSET + k m ⋅ (V COMP − 2 .4V ) ⋅ V MULT 2 V FF Where km is the small signal multiplier gain assumed here equal to the large single gain km (typ. 0.304). From this expression, replacing: Equation 88 V CS = R S ⋅ I Lpk V FF = 2 ⋅ V AC ⋅ K p and rewriting equation 31 which describes the maximum inductor peak current as: Equation 89 IL pk = K 2 ⋅ I out ⋅ V out ⋅ 1 + r 2 η ⋅ V AC ⋅ PF the effective control voltage Vcomp-VCO can be found: Equation 90 V COM P − VC 0 = 2 ⋅ R S ⋅ K p ⋅ Pin K ⋅ 1 + r 2 Km Then this expression can be used to find the unity gain factor (equation 86): DocID023523 Rev 2 31/43 FOT PFC boost control loop AN4149 Equation 91 Go = Go = km K 2 ⋅ η ⋅ Vout ⋅ R S ⋅ k p ⋅ 1 + r ⋅ C o 2 0. 23 0 .27 2 ⋅ 0 .92 ⋅ 400V ⋅ 0 .11Ω ⋅ k p ⋅ 1 + ⋅ 200 ⋅ μ F 2 = 955 .7 Looking at Figure 16, related to the gain and the phase of the control-to-output transfer function, it is possible to notice that it has just one pole at the origin. The gain falls with a slope -20 dB/dec and the phase shift is -90 ° at all frequencies. It can also be noted that the crossover frequency is much higher than the one required for a PFC (lower than 20 Hz). To make the gain roll off at low frequency (so as to cross the 0 dB axis at low frequency) and to boost the phase in the neighborhood of the crossover frequency (so as to increase phase margin), type II compensation is usually used, which adds a pole-zero couple. Figure 16. Bode plots of the control-to-output transfer function AM13316v1 Figure 17. Schematic diagram of a type II compensation C1 R2 C2 R1 VOUT Vref VCOMP AM13317v1 32/43 DocID023523 Rev 2 AN4149 FOT PFC boost control loop The transfer function of the compensated error amplifier is: Equation 92 G EA ( s ) = 1+ 1 R INV _H ⋅ C1 ⋅ 1 s ⋅ R2 ⋅ C 2 C1 + C 2 s ⋅ 1 + s ⋅ R 2 ⋅ C1 ⋅ C 2 In order to calculate the values of the components of the compensation network, the Venable K-Factor calculation is used, starting from the amount of phase margin needed at the crossover frequency and the desired maximum 3rd harmonic distortion level D3. Phase margin is defined as the difference between 180 ° and the actual phase lag at the frequency where the open-loop gain is unity. The higher the phase margin, the more overdamped the system is. As rule of thumb, to ensure fast transient response with a good level of ringing, a phase margin of 60 ° has to be chosen. Φ m = 60 ° D 3 = 2% The Venable K-factor is defined as: Equation 93 π ⋅φm 1 + sin 180 = 3 . 732 K = π ⋅φm cos 180 The required E/A gain (at 2fL) in order to keep the distortion below the desired maximum 3rd harmonic distortion (D3) is: Equation 94 H 2f = 2 ⋅ D 3 ⋅ (V COM P − V C 0 ) = Δ V ou t 2 2 ⋅ 0 .02 ⋅ H 2f = 2 ⋅ D3 ⋅ 2 ⋅ R S ⋅ k p ⋅ Pin K ⋅ 1 + r km 2 Δ V out 2 2 ⋅ 0. 011Ω ⋅ 8 ⋅ 10 − 3 ⋅ 380.4W 0. 27 ⋅ 1 + 0.23 2 = 0 .018 14. 81V 2 while the unity frequency gain is: Equation 95 H0 = 4π ⋅ f LINE _ min ⋅ H 2 f K2 H0 = 4π ⋅ 47 Hz ⋅ 0 .018 = 0 .763 3 .732 2 The frequency of the zero and the pole of the compensation network can be found with the following two expressions, where Go is the unity gain factor (equation 91). DocID023523 Rev 2 33/43 FOT PFC boost control loop AN4149 Equation 96 z= 1 ⋅ 2π Go ⋅ H o K z = 1 ⋅ 2π 955 .7 ⋅ 0 .763 = 2 . 2 Hz 3. 732 Equation 97 p= K ⋅ Go ⋅ H o ⋅ K 2π p= 3 .732 ⋅ 955 .7 ⋅ 0 .763 ⋅ 3 .732 = 30 .9 Hz 2π Then the values of the components can be calculated as follows. Feedback parallel capacitor: Equation 98 C1 = 1 z ⋅ H o ⋅ R outH p C1 = 1 2.2 Hz ⋅ = 14 .1nF 0 .763 ⋅ 6 .6 M Ω 30 . 9 Hz A value of 22 nF has been selected for the parallel feedback capacitor. Feedback series capacitor: Equation 99 p− z C 2 = C1 ⋅ z 30 .9 Hz − 2. 2 Hz C 2 = 22 nF ⋅ = 287 nF 2 .2 Hz A value of 220 nF has been selected for the series feedback capacitor. Feedback series resistor: Equation 100 R2 = 1 2π ⋅ z ⋅ C 2 R2 = 1 = 328 .8 k Ω 2 π ⋅ 2 .2 Hz ⋅ 220 nF A value of 330 kΩ has been selected for the series feedback resistor. The gain and the phase of the transfer function of the type II amplifier are represented in the bode plots in Figure 19. Figure 18. Bode plots of a type II amplifier's transfer function AM13318v1 34/43 DocID023523 Rev 2 AN4149 FOT PFC boost control loop The closed-loop transfer function is the product of the control-to-output transfer function (equation 85) and the E/A transfer function (equation 92): Equation 101 D3 = D3 = D3 = H 2 fL ⋅ Δ V out 2 100 ⋅ V COM P − V C 0 2 H 2 fL ⋅ Δ V out 2 100 ⋅ 2 ⋅ R S ⋅ k p ⋅ Pin K 2 ⋅ 1 + r 2 km 0 .0 11 ⋅ 14 .81 / 2 1 00 ⋅ = 1 .286 −3 2 ⋅ 0 .011 Ω ⋅ 8 ⋅ 10 ⋅ 380 .4W 0 .27 2 ⋅ 1 + 0 .23 2 The gain and the phase of the closed-loop transfer function is represented in the Bode plots in Figure 20. Figure 19. Bode plots of the closed-loop transfer function AM13319v1 Finally all the parameters describing the actual closed-loop transfer function are calculated. Crossover frequency: Equation 102 f c = root ( F (2 πf − 1, f )) f c = 5 . 9 Hz Phase margin: Equation 103 Φ = 180 ° + Φ F (2 ⋅ π ⋅ f c ) Φ = 56 .4 ° E/A gain at 2fL: DocID023523 Rev 2 35/43 FOT PFC boost control loop AN4149 Equation 104 ( ) H 2 fL = H 4 ⋅ π ⋅ f LINE _ min = 0 . 011 From equation 90 and equation 104 the actual 3rd harmonic distortion can be found: Equation 105 D3 = H 2 fL ⋅ Δ V out 100 ⋅ = 1 .253 V COMP − V ref 2 The comparison between Figure 20 and Figure 21 shows the practical difference between two different configurations of compensation network. In the first case, where the series resistor R2 is such to move the "phase boost" far from the crossover frequency, the phase margin is very low (around 22 °) then the system is underdamped, experiencing large overshoots and ringings. In the second case where the phase margin is around 56 ° the response of the system to the load variation is fast and without ringing, thus with limited deviations. Figure 20. 115 Vac step load (50 % to 100 %): improper compensation 36/43 Figure 21. 115 Vac step load (50 % to 100 %): good compensation DocID023523 Rev 2 AN4149 5 Layout hints Layout hints The layout of any converter is a very important phase in the design process which is sometimes neglected by the designers. Even if the layout phase sometimes looks to be time-consuming, a good layout undoubtedly saves time during the functional debugging and the qualification phases. Additionally, a power supply circuit with a correct layout needs smaller EMI filters or less filter stages, allowing consistent cost saving.The L4984D does not need any special attention to the layout, just requiring that the general layout rules for any power converter be carefully applied. Basic rules are listed here below, using the EVL4984350W PCB layout as a reference (Figure 23). – Keep the power and signal RTN separated. Connect the return pins of the components carrying high current such as the input filter, sense resistors or output capacitors as close as possible. This point is the RTN star point. A downstream converter must be connected to this return point. – Minimize the length of the traces relevant to the boost inductor, MOSFET's drain, boost rectifier and the output capacitor. – Keep signal components as close as possible to each relevant pin of the L4984D. Specifically, components and traces relevant to the error amplifier have to be placed far from traces and connections carrying signals with high dV/dt, such as the MOSFET's drain. – Connect heatsinks to power GND. – Add an external shield to the boost inductor and connect it to power GND. – Please connect the RTN of the signal components including the feedback, PFC_OK and MULT dividers close to pin 8 (GND) of the L4984D. – Connect a ceramic capacitor (100÷470 nF) close to pin #10 (VCC) and to pin #8 (GND) of the L4984D. Connect this point to the RTN star point (see rule 1). Figure 22. EVL4984-350W PCB layout (SMT side view) AM13320v1 DocID023523 Rev 2 37/43 Design example using the L4984D-CCM PFC excel spreadsheet 6 AN4149 Design example using the L4984D-CCM PFC excel spreadsheet An excel spreadsheet has been created for a quick and easy reference in order to design a boost CCM PFC pre-regulator using the L4984D. Figure 22 shows the first sheet already precompiled with the input design data used in Section 2.1. Figure 23. Excel spreadsheet design specification input table Figure 24. Other design data The spreadsheet generates a complete list of parts of the PFC schematic represented in Figure 25 on page 39 including the power dissipation calculation of the power components, following the calculation procedure described in this document . 38/43 DocID023523 Rev 2 AN4149 Design example using the L4984D-CCM PFC excel spreadsheet Rs MOS D COUT ROUTL ROUTH Vout RH RL Figure 25. CCM PFC schematic based on the L4984D 2 6 L4984D PFC-OK VFF RFF 5 7 TIMER CS GND MULT 3 CcompS ~ ~ CFF _ RmultH 90-264Vac CcompP RmultL + BRIDGE 4 8 9 GD COMP 2 1 INV CIN VCC 10 VCC L C_TIMER 1 3 RcompS AM13324v1 DocID023523 Rev 2 39/43 Design example using the L4984D-CCM PFC excel spreadsheet AN4149 The bill of material for Figure 25: CCM PFC schematic based on the L4984D is automatically compiled by the excel spreadsheet. It summarizes all selected components and some pertinent data. Figure 26. Excel spreadsheet BOM 350 BRIDGE RECTIFIER W FOT PFC BASED ON L4984D BILL OF MATERIAL Selected Value D15XB60 MOSFET P/N 2 x STF21N65M5 DIODE P/N STTH8S06 Inductor Max peak Inductor current L Ilpkx 700 7.91 μH A Pin 4 – CS Sense resistor Power dissipation Rsx Ps 0.11 1.53 Ω W INPUT Capacitor Cin 1 μF OUTPUT Capacitor Cout 330 μF Pin 3 - MULT Divider Rmult L Rmult H 100 12500 kΩ kΩ CT 680 pF fs 72.26 kHz RoutH RoutL 6600 41.5 kΩ kΩ RL RH 56 9900 kΩ kΩ Pin 1,2 - Compensation Network CcompP CcompS RcompS 22 220 390 nF nF kΩ Voltage Feedforward CFF RFF 1000 1000 nF kΩ Pin 7 - TIMER capacitor Switching frequency Pin 1 - Feedback Divider Pin 6 - Output divider for PFC_OK IC Controller 40/43 Unit [] L4984D DocID023523 Rev 2 AN4149 7 References References – L4984D, CCM PFC controller", datasheet. – A new continuous-time model for current-mode control with constant frequency, constant On-time and constant Off-time, in CCM and DCM", IEEE power electronics specialists conference record, San Antonio, Texas, pp. 382-389, 1990. – Current mode control, venable technical paper #5, www.venableind.com. – Fixed-Off-Time control of PFC pre-regulators", 10th European conference on power electronics and applications, EPE2003, Toulouse France, paper 382. – A systematic approach to frequency compensation of the voltage loop in boost PFC pre-regulator", abstract. DocID023523 Rev 2 41/43 Revision history 8 AN4149 Revision history Table 1. Document revision history 42/43 Date Revision Changes 07-Mar-2013 1 Initial release. 06-Jun-2013 2 Updated title in cover page and Figure 26: Excel spreadsheet BOM. Minor text changes. DocID023523 Rev 2 AN4149 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. ST PRODUCTS ARE NOT AUTHORIZED FOR USE IN WEAPONS. NOR ARE ST PRODUCTS DESIGNED OR AUTHORIZED FOR USE IN: (A) SAFETY CRITICAL APPLICATIONS SUCH AS LIFE SUPPORTING, ACTIVE IMPLANTED DEVICES OR SYSTEMS WITH PRODUCT FUNCTIONAL SAFETY REQUIREMENTS; (B) AERONAUTIC APPLICATIONS; (C) AUTOMOTIVE APPLICATIONS OR ENVIRONMENTS, AND/OR (D) AEROSPACE APPLICATIONS OR ENVIRONMENTS. WHERE ST PRODUCTS ARE NOT DESIGNED FOR SUCH USE, THE PURCHASER SHALL USE PRODUCTS AT PURCHASER’S SOLE RISK, EVEN IF ST HAS BEEN INFORMED IN WRITING OF SUCH USAGE, UNLESS A PRODUCT IS EXPRESSLY DESIGNATED BY ST AS BEING INTENDED FOR “AUTOMOTIVE, AUTOMOTIVE SAFETY OR MEDICAL” INDUSTRY DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS. PRODUCTS FORMALLY ESCC, QML OR JAN QUALIFIED ARE DEEMED SUITABLE FOR USE IN AEROSPACE BY THE CORRESPONDING GOVERNMENTAL AGENCY. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2013 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com DocID023523 Rev 2 43/43

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