Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
http://www.semicon.panasonic.co.jp/en/
7 x 7 Dots Matrix LED Driver LSI
FEATURES
DESCRIPTION
7 x 7 LED Matrix Driver
(Total LED that can be driven = 49)
AN32058A is 49 Dots Matrix LED Driver. It can drive up
to 16 RGB LEDs.
Built-in memory (ROM and RAM)
LDO
: 2-ch
APPLICATIONS
SPI Interface
: 1-ch
Mobile Phone
Driver for RGB color unit : 1-ch
Smart Phone
44 pin Plastic Quad Flat Non-leaded package
PCs
(QFN Type)
Game Consoles
Home Appliances etc.
TYPICAL APPLICATION
Battery
VB
VLED1
VLED2
R
G
B
LED
LDOCNT
LEDCTL
INT
CPU I/F
Y0~Y6
7
CE
CLK
DI
DO
7
1.0 F
LDO2
LDO1
1.0 F
1.0 F
VREFD
IREF
X0~X6
27 k
RGBGND
PGND
AGND
RSTB
Note)
The application circuit is an example. The operation of the mass production set is not guaranteed. Sufficient evaluation and
verification is required in the design of the mass production set. The Customer is fully responsible for the incorporation of the
above illustrated application circuit in the design of the equipment.
Page 1 of 64
Established : 2007-05-24
Revised
: 2013-04-15
Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
CONTENTS
FEATURES ………………………………………………………………………………… 1
DESCRIPTION ……..……………………………………………………………………… 1
APPLICATIONS …………………………………………………………………………… 1
TYPICAL APPLICATION ………………………………………………………………… 1
CONTENTS ………………………………………………………………………………… 2
ABSOLUTE MAXIMUM RATINGS ……………………………………………………… 3
POWER DISSIPATION RATING ………………………………………………………… 3
RECOMMENDED OPERATING CONDITIONS ……………………………………….. 4
ELECTRICAL CHARACTERISTICS .…………………………………………………… 5
PIN CONFIGURATION ……………………………………………………………………13
PIN FUNCTIONS ..………………………………………………………………………… 14
FUNCTIONAL BLOCK DIAGRAM ………………………………………………………16
OPERATION ….…………………………………………………………………………… 17
PACKAGE INFORMATION ……………………………………………………………… 63
IMPORTANT NOTICE .…………………………………………………………………… 64
Page 2 of 64
Established : 2007-05-24
Revised
: 2013-04-15
Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Note
VBMAX
6.0
V
*1
VLEDMAX
6.5
V
*1
Topr
– 30 to + 85
C
*2
Tj
– 30 to + 125
C
*2
Storage temperature
Tstg
– 55 to + 125
C
*2
Input Voltage Range
LEDCTL, RSTB, CE,
CLK, DI
– 0.3 to 3.4
V
—
LDOCNT
– 0.3 to 6.0
V
—
INT, DO
– 0.3 to 3.4
V
—
R, G, B,
LDO1, LDO2,
X0, X1, X2, X3, X4, X5, X6,
Y0, Y1, Y2, Y3, Y4, Y5, Y6
– 0.3 to 6.5
V
—
HBM (Human Body Model)
2.0
kV
—
Supply voltage
Operating ambience temperature
Operating junction temperature
Output Voltage Range
ESD
Note)
This product may sustain permanent damage if subjected to conditions higher than the above stated absolute
maximum rating. This rating is the maximum rating and device operating at this range is not guaranteeable as it is higher
than our stated recommended operating range.
When subjected under the absolute maximum rating for a long time, the reliability of the product may be affected.
*1 VBMAX = VB, VLEDMAX = VLED1 = VLED2.
The values under the condition not exceeding the above absolute maximum ratings and the power dissipation.
*2 Except for the power dissipation, operating ambient temperature, and storage temperature, all ratings are for Ta = 25C.
POWER DISSIPATION RATING
PACKAGE
JA
PD (Ta=25 C)
PD (Ta=85 C)
44 pin Plastic Quad Flat Non-leaded package (QFN Type)
71.8 C /W
1.392 W
0.557 W
Note) For the actual usage, please refer to the PD-Ta characteristics diagram in the package specification, follow the power supply
voltage, load and ambient temperature conditions to ensure that there is enough margin and the thermal design does not
exceed the allowable value.
CAUTION
Although this IC has built-in ESD protection circuit, it may still sustain permanent damage if not handled
properly. Therefore, proper ESD precautions are recommended to avoid electrostatic damage to the
MOS gates
Page 3 of 64
Established : 2007-05-24
Revised
: 2013-04-15
Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply voltage range
Input Voltage Range
Output Voltage Range
Symbol
Min.
Typ.
Max.
Unit
Note
VB
3.1
3.7
4.6
V
*1
VLED
3.1
5.0
5.6
V
*1
LEDCTL, RSTB, CE,
CLK, DI
– 0.3
—
3.0
V
—
LDOCNT
– 0.3
—
VB + 0.3
V
*2
INT, DO
– 0.3
—
3.0
V
—
R, G, B,
LDO1, LDO2,
X0, X1, X2, X3, X4, X5, X6,
Y0, Y1, Y2, Y3, Y4, Y5, Y6
– 0.3
—
VLED + 0.3
V
*2
Note) *1: The values under the condition not exceeding the above absolute maximum ratings and the power dissipation.
Do not apply external currents and voltages to any pin not specifically mentioned.
Voltage values, unless otherwise specified, are with respect to GND. GND is voltage for AGND, RGBGND and PGND.
VB is voltage for VB. VLED is voltage for VLED1 and VLED2.
*2: ( VB + 0.3 ) V must not exceed 6 V. ( VLED + 0.3 ) V must not exceed 6.5 V.
Page 4 of 64
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Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
ELECTRICAL CHARACTERISTICS
VB = 3.6 V, VLED1 = VLED2 = 4.9 V
Note)
Ta = 25 C 2 C unless otherwise specified.
Parameter
Symbol
Condition
Min
Limits
Typ
Max
Unit Note
Current consumption
Current consumption (1)
ICC1
At OFF mode
LDOCNT = Low
—
0
1
A
—
Current consumption (2)
ICC2
At Standby mode
LDOCNT = Low
LDO2 is active.
—
8
12
A
—
Current consumption (3)
ICC3
LDOCNT = High
LDO1 and LDO2 are active.
—
18
24
A
—
VREF
IVREF = 0 A
1.21
1.24
1.27
V
—
VIREF
IIREF = 0 A
0.44
0.54
0.64
V
—
VL1
ILDO1 = – 30 mA
1.79
1.85
1.91
V
—
IPT1
LDOCNT = High
REG18 = High
VLDO1 = 0 V, IPT1 = ILDO1
50
100
200
mA
—
PSL11
VB = 3.6 V + 0.2 V[p-p]
f = 1 kHz
ILDO1 = – 15 mA
PSL11 = 20log (acVLDO1 / 0.2)
—
– 45
– 40
dB
—
PSL12
VB = 3.6 V + 0.2 V[p-p]
f = 10 kHz
ILDO1 = – 15 mA
PSL12 = 20log (acVLDO1 / 0.2)
—
– 35
– 25
dB
—
Reference voltage
Output voltage
Reference current
Output voltage
Voltage regulator (LDO1)
Output voltage
Short circuit protection current
Ripple rejection (1)
Ripple rejection (2)
Page 5 of 64
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Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
ELECTRICAL CHARACTERISTICS (continued)
VB = 3.6 V, VLED1 = VLED2 = 4.9 V
Note)
Ta = 25 C 2 C unless otherwise specified.
Parameter
Symbol
Condition
Min
Limits
Typ
Max
Unit
Note
Voltage regulator (LDO2)
Output voltage
Short circuit protection current
Ripple rejection (1)
Ripple rejection (2)
VL2
ILDO2 = – 30 mA
2.76
2.85
2.94
V
—
IPT2
LDOCNT = High
VLDO2 = 0V
IPT2 = ILDO2
50
100
300
mA
—
PSL21
VB = 3.6 V + 0.2 V[p-p]
f = 1 kHz
ILDO2 = – 15 mA
PSL21 = 20log (acVLDO2 / 0.2)
—
– 35
– 30
dB
—
PSL22
VB = 3.6 V + 0.2 V[p-p]
f = 10 kHz
ILDO2 = – 15 mA
PSL22 = 20log (acVLDO2 / 0.2)
—
– 25
– 15
dB
—
0.96
1.20
1.44
MHz
—
—
2
4.8
—
Oscillator
Oscillation frequency
FDC
—
SCAN Switch
Resistance at the Switch ON
RSCAN
IY0, Y1, Y2, Y3, Y4, Y5, Y6 = 5 mA
RSCAN
= VY0, Y1, Y2, Y3, Y4, Y5, Y6 / 5 mA
Page 6 of 64
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Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
ELECTRICAL CHARACTERISTICS (continued)
VB = 3.6 V, VLED1 = VLED2 = 4.9 V
Note)
Ta = 25 C 2 C unless otherwise specified.
Parameter
Symbol
Condition
Limits
Unit Note
Min
Typ
Max
0.950
1.033
1.116
mA
*1
Current generator (For 7 7 dots matrix LED)
Output current (1)
IMX1
At 1mA setup
VX0, X1, X2, X3, X4, X5, X6 = 1 V
IMX1 = IX0, X1, X2, X3, X4, X5, X6
Output current (2)
IMX2
At 2 mA setup
VX0, X1, X2, X3, X4, X5, X6 = 1 V
IMX2 = IX0, X1, X2, X3, X4, X5, X6
1.907
2.073
2.239
mA
*1
IMX4
At 4 mA setup
VX0, X1, X2, X3, X4, X5, X6 = 1 V
IMX4 = IX0, X1, X2, X3, X4, X5, X6
3.824
4.157
4.490
mA
*1
Output current (4)
IMX8
At 8 mA setup
VX0, X1, X2, X3, X4, X5, X6 = 1 V
IMX8 = IX0, X1, X2, X3, X4, X5, X6
7.660
8.326
8.992
mA
*1
Output current (5)
IMX15
At 15 mA setup
VX0, X1, X2, X3, X4, X5, X6 = 1 V
IMX15 = IX0, X1, X2, X3, X4, X5, X6
14.408 15.661 16.914
mA
*1
Output current (3)
Leakage Current
when matrix LED turns off
Current OFF setup
IMXOFF VX0, X1, X2, X3, X4, X5, X6 = 4.75 V
IMXOFF = IX0, X1, X2, X3, X4, X5, X6
The error between channels
IMXCH
The average value of all
channels, and the current error
of each channel
—
—
1
A
—
–5
—
5
%
—
*1 : Values when recommended parts (ERJ2RHD273X) are used for IREF terminal.
The other current settings are combination of above items.
Page 7 of 64
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Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
ELECTRICAL CHARACTERISTICS (continued)
VB = 3.6 V, VLED1 = VLED2 = 4.9 V
Note)
Ta = 25 C 2 C unless otherwise specified.
Parameter
Symbol
Condition
Limits
Min
Typ
Max
Unit Note
Current generator (For RGB color unit)
Output current (1)
IRGB1
At 1mA setup
VR, G, B = 1 V
0.949
1.031
1.113
mA
*1
Output current (2)
IRGB2
At 2 mA setup
VR, G, B = 1 V
1.892
2.056
2.220
mA
*1
Output current (3)
IRGB4
At 4 mA setup
VR, G, B = 1 V
3.764
4.091
4.418
mA
*1
Output current (4)
IRGB8
At 8 mA setup
VR, G, B = 1 V
7.510
8.163
8.816
mA
*1
—
—
1
A
—
–5
—
5
%
—
Leakage Current
when RGB turn off
Current OFF setup
IRGBOFF VR, G, B = 4.75 V
IRGBOFF = IR, G, B
The error between channels
IRGBCH
The average value of all
channels, and the current
error of each channel
*1 : Values when recommended parts (ERJ2RHD273X) are used for IREF terminal.
The other current settings are combination of above items.
Page 8 of 64
Established : 2007-05-24
Revised
: 2013-04-15
Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
ELECTRICAL CHARACTERISTICS (continued)
VB = 3.6 V, VLED1 = VLED2 = 4.9 V
Note)
Ta = 25 C 2 C unless otherwise specified.
Parameter
Symbol
Condition
Limits
Min
Typ
Max
Unit Note
SPI I/F，LEDCTL，RSTB
Input voltage range of Highlevel
VIH
High-level recognition voltage
LDO1
0.8
—
LDO2
+ 0.3
V
—
Input voltage range of Lowlevel
VIL
Low-level recognition voltage
– 0.3
—
0.4
V
—
Input current of High-level
IIH
VLEDCTL, RSTB, CE, CLK, DI = 1.85 V
IIH = ILEDCTL, RSTB, CE, CLK, DI
—
0
1
A
—
Input current of Low-level
IIL
VLEDCTL, RSTB, CSB, CLK, DI = 0 V
IIL = ILEDCTL, RSTB, CE, CLK, DI
—
0
1
A
—
INT
Output voltage of High-level (1)
VOH1
IINT = – 2 mA
VDDSEL = LDO2
LDO2
0.8
—
—
V
—
Output voltage of Low-level (1)
VOL1
IINT = 2 mA
VDDSEL = LDO2
(IINT = 0.5 mA )
—
—
LDO2
0.2
(0.15)
V
—
Output voltage of High-level (2)
VOH2
IINT = – 2 mA
VDDSEL = LDO1
LDO1
0.8
—
—
V
—
VOL2
IINT = 2 mA
VDDSEL = LDO1
(IINT = 0.5 mA )
—
LDO1
0.3
(0.15)
V
—
Output voltage of Low-level (2)
—
Page 9 of 64
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Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
ELECTRICAL CHARACTERISTICS (continued)
VB = 3.6 V, VLED1 = VLED2 = 4.9 V
Note)
Ta = 25 C 2 C unless otherwise specified.
Parameter
Symbol
Condition
Input voltage range of High-level
VIH
Input voltage range of Low-level
Limits
Unit Note
Min
Typ
Max
High-level recognition voltage
VB
0.7
—
VB
+ 0.3
V
—
VIL
Low-level recognition voltage
– 0.3
—
0.4
V
—
Input current of High-level
IIH
VLDOCNT = 3.6 V
IIH = ILDOCNT
—
0
1
A
—
Input current of Low-level
IIL
VLDOCNT = 0 V
IIL = ILDOCNT
—
0
1
A
—
Output voltage of High-level
VOH
IDO = – 2 mA
LDO1
0.8
—
—
V
—
Output voltage of Low-level
VOL
IDO = 2 mA
—
—
LDO1
0.2
V
—
LDOCNT
DO
Page 10 of 64
Established : 2007-05-24
Revised
: 2013-04-15
Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
ELECTRICAL CHARACTERISTICS (continued)
VB = 3.6 V, VLED1 = VLED2 = 4.9 V
Note)
Ta = 25 C 2 C unless otherwise specified.
Parameter
Symbol
Limits
Condition
Min
Typ
Max
Unit Note
Voltage regulator (LDO1) Output capacitor 1 F, Output capacitor’s ESR less than 0.1
Rise time
Tsu1
Time until output voltage reaches
to 0 V to 90%
—
0.25
—
ms
*2
*3
Fall time
Tsd1
Time until output voltage reaches
to 10%
—
5
—
ms
*2
*3
—
15
—
mA
*3
Maximum load current
—
IOMAX1
Load transient response (1)
Vtr11
ILDO1 = – 50 A – 15 mA (1 s)
—
70
—
mV
*3
Load transient response (2)
Vtr12
ILDO1 = – 15 mA – 50 A (1 s)
—
70
—
mV
*3
Voltage regulator (LDO2) Output capacitor 1 F, Output capacitor’s ESR less than 0.1
Rise time
Tsu2
Time until output voltage reaches
to 0 V to 90%
—
0.25
—
ms
*2
*3
Fall time
Tsd2
Time until output voltage reaches
to 10%
—
5
—
ms
*2
*3
—
15
—
mA
*3
Maximum load current
IOMAX2
—
Load transient response (1)
Vtr21
ILDO2 = – 50 A – 15 mA (1 s)
—
70
—
mV
*3
Load transient response (2)
Vtr22
ILDO2 = – 15 mA – 50 A (1 s)
—
70
—
mV
*3
Tdet
Temperature which LDO1, LDO2,
Constant current circuit, Matrix SW
and RGB turns off.
—
160
—
C
*3
*4
Returning temperature
—
110
—
C
*3
*5
TSD (Thermal shutdown circuit)
Detection temperature
Return temperature
Note)
Tsd11
*2 : Rise time and Fall time are defined as below.
Actual evaluation result of rise time :
LDO1 : 290 to 400 s,
LDO2 : 220 to 310 s
Actual evaluation result of fall time :
LDO1 : 6.2 to 8.5 ms,
LDO2 : 5.8 to 7.9 ms
*3 : Typical Design Value
*4 : LDO1, LDO2, Constant current circuit, and Matrix SW and RGB are turned off when TSD is High.
When TSD is High, the register is set as 14hD1 = 1. However, data can be read only when the register
is read immediately after INT occurs since internal regulator is turned off.
*5 : Only LDO1 and LDO2 return after ON state of TSD. A logic part will be in Reset state.
LDOCNT
Serial
LDO1
90%
Tsu1
LDO2
10%
Tsd1
90%
Tsu2
10%
Tsd2
Page 11 of 64
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Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
ELECTRICAL CHARACTERISTICS (continued)
VB = 3.6 V, VLED1 = VLED2 = 4.9 V
Note)
Ta = 25 C 2 C unless otherwise specified.
Parameter
Symbol
Limits
Condition
Min
Typ
Max
Unit
Note
Microcomputer interface characteristic (Vdd = 1.85 V 3 %) Write access Timing
CLK cycle time
tscyc1
—
—
125
—
ns
*3
CLK cycle time High period
twhc1
—
—
60
—
ns
*3
CLK cycle time Low period
twlc1
—
—
60
—
ns
*3
Serial-data setup time
tss1
—
—
62
—
ns
*3
Serial-data hold time
tsh1
—
—
62
—
ns
*3
Transceiver interval
tcsw1
—
—
62
—
ns
*3
Chip enable setup time
tcss1
—
—
5
—
ns
*3
Chip enable hold time
tcgh1
—
—
5
—
ns
*3
Microcomputer interface characteristic (Vdd = 1.85 V 3 %) Read access Timing
CLK cycle time
tscyc1
—
—
125
—
ns
*3
CLK cycle time High period
twhc1
—
—
60
—
ns
*3
CLK cycle time Low period
twlc1
—
—
60
—
ns
*3
Serial-data setup time
tss1
—
—
62
—
ns
*3
Serial-data hold time
tsh1
—
—
62
—
ns
*3
Transceiver interval
tcsw1
—
—
62
—
ns
*3
Chip enable setup time
tcss1
—
—
5
—
ns
*3
Chip enable hold time
tcgh1
—
—
5
—
ns
*3
tdodly1
Only read mode
—
25
—
ns
*3
DC delay time
Note)
*3 : Typical Design Value
Timing chart
tcgh1
CE
tscyc1
tcss1
twhc1
twlc1
tcsw1
CLK
DI
tss1
tsh1
DO
tdodly1
Page 12 of 64
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Product Standards
AN32058A
PIN CONFIGURATION
34
35
36
37
38
39
40
41
42
43
44
22
21
20
19
18
17
16
15
14
13
12
N.C.
LEDCTL
Y0
Y1
VLED1
Y2
Y3
Y4
Y5
VLED2
N.C.
N.C.
VB
LDO1
RSTB
IREF
LDOCNT
VREFD
AGND
Y6
N.C.
N.C.
1
2
3
4
5
6
7
8
9
10
11
R
RGBGND
G
B
DO
DI
CLK
CE
INT
LDO2
N.C.
33
32
31
30
29
28
27
26
25
24
23
N.C.
N.C.
X6
X5
X4
PGND
X3
X2
X1
X0
N.C.
Top View
Page 13 of 64
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Product Standards
AN32058A
PIN FUNCTIONS
Pin No.
Pin name
Type
Description
1
10
11
12
22
23
32
33
44
N.C.
—
2
VB
3
LDO1
Output
LDO1 ( 1.85 V ) output terminal.
4
RSTB
Input
Reset input terminal ("L" active )
5
IREF
Output
6
LDOCNT
Input
7
VREFD
Output
BGR circuit output terminal.
8
AGND
Ground
The GND terminal for Analog circuitry.
9
Y6
Output
The output terminal of matrix switching control.
It connects with the G Column of matrix LED.
13
18
VLED2
VLED1
Power supply
14
Y5
Output
The output terminal of matrix switching control.
It connects with the F Column of matrix LED.
15
Y4
Output
The output terminal of matrix switching control.
It connects with the E Column of matrix LED.
16
Y3
Output
The output terminal of matrix switching control.
It connects with the D Column of matrix LED.
17
Y2
Output
The output terminal of matrix switching control.
It connects with the C Column of matrix LED.
19
Y1
Output
The output terminal of matrix switching control.
It connects with the B Column of matrix LED.
20
Y0
Output
The output terminal of matrix switching control.
It connects with the A Column of matrix LED.
21
LEDCTL
Input
No Connection
Power supply The power supply's connect terminal for BGR circuit and LDO circuit.
The resistance connect terminal for constant current value setup.
ON/OFF control terminal of LDO1 and LDO2.
The power supply's connect terminal for matrix LED.
Connect with the output of battery or step-up DC/DC converter
LED's lighting ON/OFF control terminal. ( It is based on register 0Ah.)
Page 14 of 64
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Revision. 3
Product Standards
AN32058A
PIN FUNCTIONS (continued)
Pin No.
Pin name
Type
Description
24
X0
Output
Constant current circuit. The output terminal of PWM control.
It connects with the 1st Row of matrix LED.
25
X1
Output
Constant current circuit. The output terminal of PWM control.
It connects with the 2nd Row of matrix LED.
26
X2
Output
Constant current circuit. The output terminal of PWM control.
It connects with the 3rd Row of matrix LED.
27
X3
Output
Constant current circuit. The output terminal of PWM control.
It connects with the 4th Row of matrix LED.
28
PGND
Ground
The GND terminal for matrix LED
29
X4
Output
Constant current circuit. The output terminal of PWM control.
It connects with the 5th Row of matrix LED.
30
X5
Output
Constant current circuit. The output terminal of PWM control.
It connects with the 6th Row of matrix LED.
31
X6
Output
Constant current circuit. The output terminal of PWM control.
It connects with the 7th Row of matrix LED.
34
R
Output
LED contact terminal.
35
RGBGND
Ground
The GND terminal for RGB terminal.
36
G
Output
LED contact terminal.
37
B
Output
LED contact terminal.
38
DO
Output
Data output terminal for SPI interface.
39
DI
Input
Data input terminal for SPI interface.
40
CLK
Input
Clock input terminal for SPI interface.
41
CE
Input
Chip-enable terminal for SPI1 interface. ("H" active )
42
INT
Output
Interrupt output terminal.
43
LDO2
Output
LDO2 ( 2.85 V ) output terminal.
Page 15 of 64
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Revision. 3
Product Standards
AN32058A
23 N.C.
24 XO
25 X1
26 X2
27 X3
28 PGND
29 X4
30 X5
31 X6
32 N.C.
33 N.C.
FUNCTIONAL BLOCK DIAGRAM
Constant current control
(7-ch)
22 N.C.
R 34
RGBGND 35
G 36
20 Y0
19 Y1
B 37
Fixed
pattern
ROM
Register
DO 38
DI 39
Level
shift
CLK 40
21 LEDCTL
PWM control
(7-ch)
RGB
Color
Unit
control
SPI
18 VLED1
Pattern
register
RAM
SCAN
switch
(7-ch)
Command decoding
17 Y2
16 Y3
15 Y4
CE 41
14 Y5
Level shift
ON/OFF
STANDBY
ON/OFF
N.C. 44
12 N.C.
BGR
TSD
1
2
3
4
5
6
7
8
9
10
11
VB
LDO1
RSTB
IREF
LDOCNT
VREFD
AGND
Y6
N.C.
N.C.
IREF
N.C.
LDO1
1.85 V/30 mA
13 VLED2
ON/OFF
HTSD
ON/OFF
1
LDO2 43
LDO2
2.85 V/30 mA
INT 42
Notes: This block diagram is for explaining functions. Part of the block diagram may be omitted, or it may be simplified.
Page 16 of 64
Established : 2007-05-24
Revised
: 2013-04-15
Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
OPERATION
1. Explanation in each mode (Power supply starting sequence)
Mode
LDOCNT
REG18
REG28
OFF
Low
0
0
"L" → "H"
0/1
0/1
"H"
0/1
0/1
OFF
→
Normal mode
Normal mode
→
OFF
0
0
0
1
"H" → "L"
Normal mode
→
Standby
mode
Note
• It is necessary to make it LDOCNT = High for the
return from OFF-mode.
• The signal from serial interface is not received in
LDOCNT = Low and the state of REG28 = Low or
REG18 = Low.
• It shifts to standby mode with LDOCNT = Low and
REG28 = High.
• The signal from serial interface is not received at
Standby-mode. (Power supply for Logic is LDO1 and
LDO2.) Therefore, standby release by the signal from
serial interface cannot be performed.
• In Standby-mode, if LDOCNT is switched to High from
Low, it will return to the normal mode.
• It cannot shift to OFF-mode from Standby-mode.
Once returning to the normal mode, please shift to
OFF-mode.
• Regardless of the value of REG18, LDO1 turns on at
LDOCNT = High.
• Regardless of the value of REG28, LDO2 turns on at
LDOCNT = High.
• Serial interface signal is not received at RSTB = Low
• 5 ms after being set to LDOCNT = High, the
receptionist of serial interface signal is attained.
• RSTB terminal prohibits the input signal of those other
than a rectangle wave.
• All register setting become default setting if RSTB =
Low
• (The default setting of REG18 and REG28 are [1]
• If RSTB = Low before LDOCNT = Low, LDO1 and
LDO2 can’t turn off. )
• All register setting become default setting when LDO2
turn off.
• The setting order to change off mode is as following.
• REG18, 28 = [0] → LDOCNT = "L" → RSTB = "L"
Page 17 of 64
Established : 2007-05-24
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: 2013-04-15
Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
OPERATION (continued)
1. Explanation in each mode (Power supply starting sequence) (continued)
• Shift to the Normal mode from OFF-mode
LDOCNT
REG18
[Address : 02h]
REG28
[Address : 02h]
LDO1
LDO2
RSTB
Over 3 ms
Over 5 ms
A register input is possible.
• Shift to the Normal mode from Standby mode
LDOCNT
REG18
[Address : 02h]
REG28
[Address : 02h]
LDO1
LDO2
Low power mode
RSTB*
over 3 ms
Over 5 ms
A register input is possible.
* It is a waveform in the case of applying reset to register setup at Standby mode.
* Maintain the state of RSTB = High to hold the register setup.
Page 18 of 64
Established : 2007-05-24
Revised
: 2013-04-15
Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
OPERATION (continued)
1. Explanation in each mode (Power supply starting sequence) (continued)
• Shift to the OFF-mode from Normal mode
Over 1 ms
LDOCNT
REG18
[Address : 02h]
REG28
[Address : 02h]
Set REG18 and REG28 to Low before LDOCNT.
LDO1
LDO2
RSTB
Over 3ms
A register input is possible.
• Shift to the Standby mode from Normal mode
Over 1 ms
LDOCNT
REG18
[Address : 02h]
Set REG18 to Low before LDOCNT.
REG28
[Address : 02h]
LDO1
LDO2
Low power mode
RSTB
A register input is possible.
Page 19 of 64
Established : 2007-05-24
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: 2013-04-15
Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
OPERATION (continued)
1. Explanation in each mode (Power supply starting sequence) (continued)
• Shift to the OFF-mode from Normal mode
VBAT
LDOCNT
MODE
"L"
"L"
OFF
"L"
"H"
Prohibition
"H"
"L"
OFF
"H"
"H"
ON
Note) "L" in column of VBAT and LDOCNT means 0 V, "H" means 3.1 to 4.6 V ( operating supply voltage range ).
• Logic pin condition
The following setting is common for OFF, Standby and Normal mode.
The pin setting when RSTB = Low, under Normal mode is as follows.
Pin name
Pin state
Logic*
INT
Output
"L"
CE
Input
"L"
CLK
Input
"L"
DI
Input
"L"
DO
Output
"L"
LEDCTL
Input
"L"
LDOCNT
Input
Depends on each mode
Note)*: Logic state for pins indicated as “Output” under Pin state shows the output level.
Logic state for pins indicated as “Input” under Pin state shows the input level to be set to the pins.
Page 20 of 64
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: 2013-04-15
Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
OPERATION (continued)
2. Explanation of operation
• Matrix part operation waveform
• The following waveform is an internal signal. In following Yx = Xx = Low, the waveform of actual Yx terminal is set
to Hi-Z.
• It is controlled by internal 1.2 MHz clock in default condition.
• Y side switches from Y0 to Y6 in that order. The turning on term of each pin is constant 945clock (787.5 s) and
each turning on term includes 8clock (6.67 s) interval.
• "*" mark shows the turning on term and D3, D6 is the turning off term in the following figure.
• 77 matrix display is controlled by X0 to X6 with Yx switching timing.
945clk
(787.5 s)
8clk
(6.67 s)
Y0
Y1
Y2
Y3
Y4
Y5
Y6
X0 to X6
*
*
D0
*
*
D1
D2
D3
*
*
D4
D5
D6
D0
PWM Minimum
width 63clk
(52.5 s)
6671clk
(About 180.83 Hz)
Page 21 of 64
Established : 2007-05-24
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: 2013-04-15
Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
OPERATION (continued)
3. Block configuration
• RESET part block configuration
VB
VBATT
VREFD
ON/OFF
BGR
TSD
HTSD
1 F
LDOCNT
LDO2
LDO2
2.85 V
1 F
LDO1
LDO1
1.85 V
ON/OFF
STANDBY
ON/OFF
ON/OFF
1 F
LDO1
LDO2
CE
CLK
DI
LEVEL
SHIFT
LDO2 VB
Register
REG18
DO
RST
REG28
LEVEL
SHIFT
LDO1 LDO2
RSTB
LEVEL
SHIFT
LDO2
All the logic portions to which the power supply is not connected are connected to VB as power supplies.
Page 22 of 64
Established : 2007-05-24
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: 2013-04-15
Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
OPERATION (continued)
3. Block configuration (continued)
• Explanation of matrix LED part, matrix LED’s number
•
•
•
•
LED matrix driver circuit can display character and pattern by controlling the 77 matrix LED individually.
In this specification, LED’s number controlled by each terminal can be matched off against the following figure.
It is controlled by internal 1.2 MHz clock in default condition.
In the scroll mode, LED matrix can move the display of character from right to left as the following arrangement.
The connected
terminal name
X0
1
X1
2
X2
3
X3
4
X4
5
X5
6
X6
7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
A
B
C
D
E
F
G
LED’s number
LED‘s number
Page 23 of 64
Established : 2007-05-24
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: 2013-04-15
Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
OPERATION (continued)
3. Block configuration (continued)
• Equivalent circuit of matrix LED driver
X0 terminal case
LDO2
VLED
VB
20 A
1.24 V
BGR
Ibl1
245 k
187 k
IREF
X0
V(IREF)
= 0.54 V
R(IREF)
= 27 k
Control
Logic
DAC
Q1
Q2
Panasonic
ERJ2RHD273X
• The reference current for constant current driver is calculated by the following formula.
V(IREF) / R(IREF) = 0.54 V / 27 k = 20 A
• The LED driver current can be set from 0 mA to 30 mA by register setting via serial interface.
• The constant current value can be changed by the external resistor value of IREF terminal, but the accuracy in
case of that setting is not guaranteed.
• ERJ2RHD273X is recommended for the external resistor of IREF terminal to keep the constant current accuracy.
Page 24 of 64
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: 2013-04-15
Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
OPERATION (continued)
4. Register and Address
• Register Map
Sub
address
R/W
Data name
01h
W
02h
W
Data
D7
D6
D5
D4
D3
D2
D1
D0
POWERCNT
—
—
—
—
—
OSCEN
—
—
LDOCNT
—
—
—
—
—
—
REG18
REG28
—
DISMTX
DISRGB
—
03h
For test
04h
For test
05h
For test
06h
For test
07h
For test
08h
For test
09h
For test
0Ah
W
LEDCTL
LEDACT
—
—
—
10h
For test
11h
For test
12h
For test
13h
For test
14h
R
IOFACTOR
FACGD1
—
—
—
15h
For test
16h
For test
17h
For test
18h
For test
19h
For test
1Ah
W/R
VDDSEL
INTVSEL
—
—
—
RAM
ACT
—
FRMINT CPUWRER
—
—
TSD
—
Page 25 of 64
Established : 2007-05-24
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: 2013-04-15
Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
OPERATION (continued)
4. Register and Address (continued)
• Register Map (continued)
DATA
Sub
Address
R/W
Data Name
20h
R/W
MTXON
21h
R/W
MTXDATA
22h
R/W
FFROM
23h
R/W
ROMSEL
24h
R/W
RAMCOPY
25h
R/W
SETFROM
SETFROM[7:0]
26h
R/W
SETTO
SETTO[7:0]
27h
R/W
REPON
28h
R/W
SETTIME
29h
R/W
RAMRST
RAM1
RAM2
2Ah
R/W
SCROLL
SCLON
RGBON
RAMNUM
D7
D6
D5
D4
D3
D2
D1
D0
MTXON
MTXDATA[7:0]
ROM77[1:0]
SELROM[7:0]
2Bh
SELRAM
COPYSTART
REPON
SETTIME[1:0]
For test
2Ch
R/W
RGBON
2Dh
R/W
RGBDATA
RGBDATA[5:0]
2Eh
30h
For test
R/W
RAMNUM
6Bh
For test
6Dh
For test
6Fh
For test
70h
For test
71h
For test
72h
For test
73h
For test
74h
For test
75h
For test
76h
For test
77h
For test
* Access the address from 6Bh to 77h is prohibited.
Page 26 of 64
Established : 2007-05-24
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: 2013-04-15
Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
OPERATION (continued)
4. Register and Address (continued)
RAM address map
DATA
Sub
Address
Data Name
31h
A1
BLA1[3:0]
FRA1[1:0]
DLA1[1:0]
32h
A2
BLA2[3:0]
FRA2[1:0]
DLA2[1:0]
33h
A3
BLA3[3:0]
FRA3[1:0]
DLA3[1:0]
34h
A4
BLA4[3:0]
FRA4[1:0]
DLA4[1:0]
35h
A5
BLA5[3:0]
FRA5[1:0]
DLA5[1:0]
36h
A6
BLA6[3:0]
FRA6[1:0]
DLA6[1:0]
37h
A7
BLA7[3:0]
FRA7[1:0]
DLA7[1:0]
38h
B1
BLB1[3:0]
FRB1[1:0]
DLB1[1:0]
39h
B2
BLB2[3:0]
FRB2[1:0]
DLB2[1:0]
3Ah
B3
BLB3[3:0]
FRB3[1:0]
DLB3[1:0]
3Bh
B4
BLB4[3:0]
FRB4[1:0]
DLB4[1:0]
3Ch
B5
BLB5[3:0]
FRB5[1:0]
DLB5[1:0]
3Dh
B6
BLB6[3:0]
FRB6[1:0]
DLB6[1:0]
3Eh
B7
BLB7[3:0]
FRB7[1:0]
DLB7[1:0]
3Fh
C1
BLC1[3:0]
FRC1[1:0]
DLC1[1:0]
40h
C2
BLC2[3:0]
FRC2[1:0]
DLC2[1:0]
41h
C3
BLC3[3:0]
FRC3[1:0]
DLC3[1:0]
42h
C4
BLC4[3:0]
FRC4[1:0]
DLC4[1:0]
43h
C5
BLC5[3:0]
FRC5[1:0]
DLC5[1:0]
44h
C6
BLC6[3:0]
FRC6[1:0]
DLC6[1:0]
45h
C7
BLC7[3:0]
FRC7[1:0]
DLC7[1:0]
46h
D1
BLD1[3:0]
FRD1[1:0]
DLD1[1:0]
47h
D2
BLD2[3:0]
FRD2[1:0]
DLD2[1:0]
48h
D3
BLD3[3:0]
FRD3[1:0]
DLD3[1:0]
49h
D4
BLD4[3:0]
FRD4[1:0]
DLD4[1:0]
4Ah
D5
BLD5[3:0]
FRD5[1:0]
DLD5[1:0]
4Bh
D6
BLD6[3:0]
FRD6[1:0]
DLD6[1:0]
4Ch
D7
BLD7[3:0]
FRD7[1:0]
DLD7[1:0]
D7
D6
D5
D4
D3
D2
D1
D0
Page 27 of 64
Established : 2007-05-24
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: 2013-04-15
Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
OPERATION (continued)
4. Register and Address (continued)
RAM address map (continued)
DATA
Sub
Address
Data Name
4Dh
E1
BLE1[3:0]
FRE1[1:0]
DLE1[1:0]
4Eh
E2
BLE2[3:0]
FRE2[1:0]
DLE2[1:0]
4Fh
E3
BLE3[3:0]
FRE3[1:0]
DLE3[1:0]
50h
E4
BLE4[3:0]
FRE4[1:0]
DLE4[1:0]
51h
E5
BLE5[3:0]
FRE5[1:0]
DLE5[1:0]
52h
E6
BLE6[3:0]
FRE6[1:0]
DLE6[1:0]
53h
E7
BLE7[3:0]
FRE7[1:0]
DLE7[1:0]
54h
F1
BLF1[3:0]
FRF1[1:0]
DLF1[1:0]
55h
F2
BLF2[3:0]
FRF2[1:0]
DLF2[1:0]
56h
F3
BLF3[3:0]
FRF3[1:0]
DLF3[1:0]
57h
F4
BLF4[3:0]
FRF4[1:0]
DLF4[1:0]
58h
F5
BLF5[3:0]
FRF5[1:0]
DLF5[1:0]
59h
F6
BLF6[3:0]
FRF6[1:0]
DLF6[1:0]
5Ah
F7
BLF7[3:0]
FRF7[1:0]
DLF7[1:0]
5Bh
G1
BLG1[3:0]
FRG1[1:0]
DLG1[1:0]
5Ch
G2
BLG2[3:0]
FRG2[1:0]
DLG2[1:0]
5Dh
G3
BLG3[3:0]
FRG3[1:0]
DLG3[1:0]
5Eh
G4
BLG4[3:0]
FRG4[1:0]
DLG4[1:0]
5Fh
G5
BLG5[3:0]
FRG5[1:0]
DLG5[1:0]
60h
G6
BLG6[3:0]
FRG6[1:0]
DLG6[1:0]
61h
G7
BLG7[3:0]
FRG7[1:0]
DLG7[1:0]
62h
LEDR
BLLEDR[3:0]
FRLEDR[1:0]
DLLEDR[1:0]
63h
LEDG
BLLEDG[3:0]
FRLEDG[1:0]
DLLEDG[1:0]
64h
LEDB
BLLEDB[3:0]
FRLEDB[1:0]
DLLEDB[1:0]
D7
D6
D5
D4
D3
D2
D1
D0
Page 28 of 64
Established : 2007-05-24
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: 2013-04-15
Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
OPERATION (continued)
4. Register and Address (continued)
• ROM Address Map
[00000000] - [10010101] : ROM(Only luminosity) 7 7 Pattern No.0 (default) to Pattern No.149
Pattern No.
Contents of the pattern
Display
Pattern No.
Contents of the pattern
Display
0
All putting out lights
Nothing
31
Alphabetic character
U
1
Number
0
32
Alphabetic character
V
2
Number
1
33
Alphabetic character
W
3
Number
2
34
Alphabetic character
X
4
Number
3
35
Alphabetic character
Y
5
Number
4
36
Alphabetic character
Z
6
Number
5
37
Alphabetic character
a
7
Number
6
38
Alphabetic character
b
8
Number
7
39
Alphabetic character
c
9
Number
8
40
Alphabetic character
d
10
Number
9
41
Alphabetic character
e
11
Alphabetic character
A
42
Alphabetic character
f
12
Alphabetic character
B
43
Alphabetic character
g
13
Alphabetic character
C
44
Alphabetic character
h
14
Alphabetic character
D
45
Alphabetic character
i
15
Alphabetic character
E
46
Alphabetic character
j
16
Alphabetic character
F
47
Alphabetic character
k
17
Alphabetic character
G
48
Alphabetic character
l
18
Alphabetic character
H
49
Alphabetic character
m
19
Alphabetic character
I
50
Alphabetic character
n
20
Alphabetic character
J
51
Alphabetic character
o
21
Alphabetic character
K
52
Alphabetic character
p
22
Alphabetic character
L
53
Alphabetic character
q
23
Alphabetic character
M
54
Alphabetic character
r
24
Alphabetic character
N
55
Alphabetic character
s
25
Alphabetic character
O
56
Alphabetic character
t
26
Alphabetic character
P
57
Alphabetic character
u
27
Alphabetic character
Q
58
Alphabetic character
v
28
Alphabetic character
R
59
Alphabetic character
w
29
Alphabetic character
S
60
Alphabetic character
x
30
Alphabetic character
T
61
Alphabetic character
y
Page 29 of 64
Established : 2007-05-24
Revised
: 2013-04-15
Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
OPERATION (continued)
4. Register and Address (continued)
• ROM Address Map (continued)
[00000000] - [10010101] : ROM(Only luminosity) 77 Pattern No.0 (default) to Pattern No.149
Pattern No.
Contents of the pattern
Display
Pattern No.
Contents of the pattern
Display
62
Alphabetic character
z
93
Number
30
63
Number
00
94
Number
31
64
Number
01
95
Number
32
65
Number
02
96
Number
33
66
Number
03
97
Number
34
67
Number
04
98
Number
35
68
Number
05
99
Number
36
69
Number
06
100
Number
37
70
Number
07
101
Number
38
71
Number
08
102
Number
39
72
Number
09
103
Number
40
73
Number
10
104
Number
41
74
Number
11
105
Number
42
75
Number
12
106
Number
43
76
Number
13
107
Number
44
77
Number
14
108
Number
45
78
Number
15
109
Number
46
79
Number
16
110
Number
47
80
Number
17
111
Number
48
81
Number
18
112
Number
49
82
Number
19
113
Number
50
83
Number
20
114
Number
51
84
Number
21
115
Number
52
85
Number
22
116
Number
53
86
Number
23
117
Number
54
87
Number
24
118
Number
55
88
Number
25
119
Number
56
89
Number
26
120
Number
57
90
Number
27
121
Number
58
91
Number
28
122
Number
59
92
Number
29
123
Number
60
Page 30 of 64
Established : 2007-05-24
Revised
: 2013-04-15
Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
OPERATION (continued)
4. Register and Address (continued)
• ROM Address Map (continued)
[00000000] - [10010101] : ROM(Only luminosity) 77 Pattern No.0 (default) to Pattern No.149
Pattern No.
Contents of the pattern
Display
Pattern No.
Contents of the pattern
124
Symbol
Zero
antenna
144
Symbol
125
Symbol
One
antenna
126
Symbol
Two
antenna
145
Symbol
127
Symbol
Three
antenna
128
Symbol
146
Symbol
129
Symbol
130
Symbol
||
147
Symbol
131
Symbol
>>
132
Symbol
<<
133
Symbol
:
148
Symbol
134
Symbol
!
135
Symbol
?
149
Symbol
136
Symbol
137
Symbol
138
Symbol
←
139
Symbol
→
140
Symbol
+
141
Symbol
-
142
Symbol
/
143
Symbol
Display
Page 31 of 64
Established : 2007-05-24
Revised
: 2013-04-15
Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
OPERATION (continued)
4. Register and Address (continued)
• ROM Address Map (continued)
[10010110] - [11010000] : ROM(Luminosity + Cycle + Delay) 7 7 Pattern No.150 to Pattern No.208
Pattern No.
Contents of the pattern
150
Display
Pattern No.
Contents of the pattern
Gradation
159
Gradation
151
Gradation
160
Gradation
152
Gradation
161
Gradation
153
Gradation
162
Gradation
154
Gradation
163
Gradation
155
Gradation
164
Gradation
156
Gradation
165
Gradation
157
Gradation
166
Gradation
158
Gradation
167
Gradation
Display
Page 32 of 64
Established : 2007-05-24
Revised
: 2013-04-15
Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
OPERATION (continued)
4. Register and Address (continued)
• ROM Address Map (continued)
[10010110] - [11010000] : ROM(Luminosity + Cycle + Delay) 7 7 Pattern No.150 to Pattern No.208
Pattern No.
Contents of the pattern
168
Display
Pattern No.
Contents of the pattern
Gradation
177
Gradation
169
Gradation
178
Gradation
170
Gradation
179
Gradation
171
Gradation
180
Gradation
172
Gradation
181
Gradation
173
Gradation
182
Gradation
174
Gradation
183
Gradation
175
Gradation
184
Gradation
176
Gradation
185
Gradation
Display
Page 33 of 64
Established : 2007-05-24
Revised
: 2013-04-15
Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
OPERATION (continued)
4. Register and Address (continued)
• ROM Address Map (continued)
[10010110] - [11010000] : ROM(Luminosity + Cycle + Delay) 7 7 Pattern No.150 to Pattern No.208
Pattern No.
Contents of the pattern
Gradation
195
Gradation
187
Gradation
196
Gradation
188
Gradation
197
Gradation
189
Gradation
198
Gradation
190
Gradation
199
Gradation
191
Gradation
200
Gradation
192
Gradation
201
Gradation
193
Gradation
202
Gradation
194
Gradation
203
Gradation
Pattern No.
Contents of the pattern
186
Display
Display
Page 34 of 64
Established : 2007-05-24
Revised
: 2013-04-15
Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
OPERATION (continued)
4. Register and Address (continued)
• ROM Address Map (continued)
[10010110] - [11010000] : ROM(Luminosity + Cycle + Delay) 7 7 Pattern No.150 to Pattern No.208
Pattern No.
Contents of the pattern
204
Gradation
205
Gradation
206
Gradation
207
Gradation
208
Gradation
Display
Page 35 of 64
Established : 2007-05-24
Revised
: 2013-04-15
Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
OPERATION (continued)
4. Register and Address (continued)
• Register table which needs a clock
About the following addresses, even if an internal clock or an external clock does not exist,
Read / Write is possible in the data to register. However, it cannot be given to operation finally needed.
Sub
Address
R/W
Data Name
01h
W
14h
DATA
D7
D6
D5
D4
D3
D2
D1
D0
POWERCNT
—
—
—
—
—
OSCEN
—
—
R
IOFACTOR
FACG
D1
—
—
—
RAM
ACT
FRMINT
CPU
WRER
TSD
20h
R/W
MTXON
—
—
—
—
—
—
—
MTXON
21h
R/W
MTXDATA
22h
R/W
FFROM
23h
R/W
ROMSEL
24h
R/W
RAMCOPY
25h
R/W
SETFROM
SETFROM[7:0]
26h
R/W
SETTO
SETTO[7:0]
27h
R/W
REPON
—
—
—
—
—
—
28h
R/W
SETTIME
—
—
—
—
—
—
29h
R/W
RAMRST
—
—
—
—
—
—
RAM1
RAM2
2Ah
R/W
SCROLL
—
—
—
—
—
—
—
SCLON
2Bh
R/W
SCLTIME
—
—
—
—
—
—
2Ch
R/W
RGBON
—
—
—
—
—
—
2Dh
R/W
RGBDATA
—
—
30h
R/W
RAMNUM
—
—
MTXDATA[7:0]
—
—
—
—
—
—
ROM77[1:0]
SELROM[7:0]
—
—
—
—
—
—
SELRAM
COPY
START
—
REPON
SETTIME[1:0]
SCLTIME[1:0]
—
RGBON
—
RAMNUM
RGBDATA[5:0]
—
—
—
—
Page 36 of 64
Established : 2007-05-24
Revised
: 2013-04-15
Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
OPERATION (continued)
4. Register and Address (continued)
• Register table which needs a clock (continued)
About the following addresses, when an internal clock or an external clock does not exist,
data cannot be Read / Write in at register.
DATA
Sub Address
Data Name
31h
A1
BLA1[3:0]
FRA1[1:0]
DLA1[1:0]
32h
A2
BLA2[3:0]
FRA2[1:0]
DLA2[1:0]
33h
A3
BLA3[3:0]
FRA3[1:0]
DLA3[1:0]
34h
A4
BLA4[3:0]
FRA4[1:0]
DLA4[1:0]
35h
A5
BLA5[3:0]
FRA5[1:0]
DLA5[1:0]
36h
A6
BLA6[3:0]
FRA6[1:0]
DLA6[1:0]
37h
A7
BLA7[3:0]
FRA7[1:0]
DLA7[1:0]
38h
B1
BLB1[3:0]
FRB1[1:0]
DLB1[1:0]
39h
B2
BLB2[3:0]
FRB2[1:0]
DLB2[1:0]
3Ah
B3
BLB3[3:0]
FRB3[1:0]
DLB3[1:0]
3Bh
B4
BLB4[3:0]
FRB4[1:0]
DLB4[1:0]
3Ch
B5
BLB5[3:0]
FRB5[1:0]
DLB5[1:0]
3Dh
B6
BLB6[3:0]
FRB6[1:0]
DLB6[1:0]
3Eh
B7
BLB7[3:0]
FRB7[1:0]
DLB7[1:0]
3Fh
C1
BLC1[3:0]
FRC1[1:0]
DLC1[1:0]
40h
C2
BLC2[3:0]
FRC2[1:0]
DLC2[1:0]
41h
C3
BLC3[3:0]
FRC3[1:0]
DLC3[1:0]
42h
C4
BLC4[3:0]
FRC4[1:0]
DLC4[1:0]
43h
C5
BLC5[3:0]
FRC5[1:0]
DLC5[1:0]
44h
C6
BLC6[3:0]
FRC6[1:0]
DLC6[1:0]
45h
C7
BLC7[3:0]
FRC7[1:0]
DLC7[1:0]
46h
D1
BLD1[3:0]
FRD1[1:0]
DLD1[1:0]
47h
D2
BLD2[3:0]
FRD2[1:0]
DLD2[1:0]
48h
D3
BLD3[3:0]
FRD3[1:0]
DLD3[1:0]
49h
D4
BLD4[3:0]
FRD4[1:0]
DLD4[1:0]
4Ah
D5
BLD5[3:0]
FRD5[1:0]
DLD5[1:0]
4Bh
D6
BLD6[3:0]
FRD6[1:0]
DLD6[1:0]
4Ch
D7
BLD7[3:0]
FRD7[1:0]
DLD7[1:0]
D7
D6
D5
D4
D3
D2
D1
D0
Page 37 of 64
Established : 2007-05-24
Revised
: 2013-04-15
Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
OPERATION (continued)
4. Register and Address (continued)
• Register table which needs a clock (continued)
About the following addresses, when an internal clock or an external clock does not exist,
data cannot be Read / Write in at register.
DATA
Sub Address
Data Name
4Dh
E1
BLE1[3:0]
FRE1[1:0]
DLE1[1:0]
4Eh
E2
BLE2[3:0]
FRE2[1:0]
DLE2[1:0]
4Fh
E3
BLE3[3:0]
FRE3[1:0]
DLE3[1:0]
50h
E4
BLE4[3:0]
FRE4[1:0]
DLE4[1:0]
51h
E5
BLE5[3:0]
FRE5[1:0]
DLE5[1:0]
52h
E6
BLE6[3:0]
FRE6[1:0]
DLE6[1:0]
53h
E7
BLE7[3:0]
FRE7[1:0]
DLE7[1:0]
54h
F1
BLF1[3:0]
FRF1[1:0]
DLF1[1:0]
55h
F2
BLF2[3:0]
FRF2[1:0]
DLF2[1:0]
56h
F3
BLF3[3:0]
FRF3[1:0]
DLF3[1:0]
57h
F4
BLF4[3:0]
FRF4[1:0]
DLF4[1:0]
58h
F5
BLF5[3:0]
FRF5[1:0]
DLF5[1:0]
59h
F6
BLF6[3:0]
FRF6[1:0]
DLF6[1:0]
5Ah
F7
BLF7[3:0]
FRF7[1:0]
DLF7[1:0]
5Bh
G1
BLG1[3:0]
FRG1[1:0]
DLG1[1:0]
5Ch
G2
BLG2[3:0]
FRG2[1:0]
DLG2[1:0]
5Dh
G3
BLG3[3:0]
FRG3[1:0]
DLG3[1:0]
5Eh
G4
BLG4[3:0]
FRG4[1:0]
DLG4[1:0]
5Fh
G5
BLG5[3:0]
FRG5[1:0]
DLG5[1:0]
60h
G6
BLG6[3:0]
FRG6[1:0]
DLG6[1:0]
61h
G7
BLG7[3:0]
FRG7[1:0]
DLG7[1:0]
62h
LEDR
BLLEDR[3:0]
FRLEDR[1:0]
DLLEDR[1:0]
63h
LEDG
BLLEDG[3:0]
FRLEDG[1:0]
DLLEDG[1:0]
64h
LEDB
BLLEDB[3:0]
FRLEDB[1:0]
DLLEDB[1:0]
D7
D6
D5
D4
D3
D2
D1
D0
Page 38 of 64
Established : 2007-05-24
Revised
: 2013-04-15
Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
OPERATION (continued)
4. Register and Address (continued)
• Register map detailed explanation
Sub Address
01h
DATA
D7
D6
D5
D4
D3
D2
D1
D0
Data Name
—
—
—
—
—
OSCEN
—
—
Default
0
0
0
0
0
0
0
0
mode
W
W
W
W
W
W
W
W
D2 : OSCEN ON/OFF bit for internal oscillators
[0] : Internal oscillating circuit is OFF (default)
[1] : Internal oscillating circuit is ON
The variation width of an internal oscillator is set to 0.96MHz - 1.44 MHz.
The variation width of an internal clock is set to 694.4 ns - 1042 ns.
Sub Address
02h
DATA
D7
D6
D5
D4
D3
D2
D1
D0
Data Name
—
—
—
—
—
—
REG18
REG28
Default
0
0
0
0
0
0
1
1
mode
W
W
W
W
W
W
W
W
D1 : REG18 The ON/OFF control for LDO1(When LDOCNT terminal is Low)
[0] : LDO1 OFF
[1] : LDO1 ON (default)
D0 : REG28 The ON/OFF control for LDO2( When LDOCNT terminal is Low )
[0] : LDO2 OFF
[1] : LDO2 ON (default)
When LDOCNT terminal is High, regardless of the state of REG18, LDO1 will be activated.
When LDOCNT terminal is High, regardless of the state of REG28, LDO2 will be activated.
Set LDOCNT to Low after setting REG28 to Low to put into OFF mode.
Page 39 of 64
Established : 2007-05-24
Revised
: 2013-04-15
Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
OPERATION (continued)
4. Register and Address (continued)
• Register map detailed explanation (continued)
Sub Address
DATA
D7
D6
D5
D4
0
0
0
0
0
0
0
mode
W
W
W
W
W
W
W
W
D3
D2
D1
D0
DATA
D7
D6
D5
D4
For test
Default
0
0
0
0
0
0
0
0
mode
R
R
R
R
R
R
R
R
D3
D2
D1
D0
Sub Address
DATA
D7
D6
D5
D4
For test
Data Name
Default
0
0
0
0
0
0
0
0
mode
W
W
W
W
W
W
W
W
D3
D2
D1
D0
Sub Address
DATA
D7
D6
D5
D4
For test
Data Name
06h
Default
0
0
0
0
0
0
0
0
mode
W
W
W
W
W
W
W
W
D3
D2
D1
D0
Sub Address
DATA
D7
D6
D5
D4
For test
Data Name
07h
D0
0
Data Name
05h
D1
Default
Sub Address
04h
D2
For test
Data Name
03h
D3
Default
0
0
0
0
0
0
0
0
mode
W
W
W
W
W
W
W
W
*Don’t access to address from 03h to 07h.
Page 40 of 64
Established : 2007-05-24
Revised
: 2013-04-15
Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
OPERATION (continued)
4. Register and Address (continued)
• Register map detailed explanation (continued)
Sub Address
DATA
D7
D6
D5
D4
Data Name
08h
D2
D1
D0
For test
Default
0
0
0
0
0
0
0
0
mode
W
W
W
W
W
W
W
W
D3
D2
D1
D0
Sub Address
DATA
D7
D6
D5
D4
Data Name
09h
D3
For test
Default
0
0
0
0
0
0
0
0
mode
W
W
W
W
W
W
W
W
*Don’t access to address from 08h to 09h.
Sub Address
0Ah
DATA
D7
D6
D5
D4
D3
D2
D1
D0
Data Name
LEDACT
—
—
—
—
DISMTX
DISRGB
—
Default
0
0
0
0
0
0
0
0
mode
W
W
W
W
W
W
W
W
D7 : LEDACT A putting-out-lights setup of LED by LEDCTL terminal.
[0] : The light is switched on at LEDCTL = Low(default)
[1] : The light is switched on at LEDCTL = High
D2 : DISMTX A putting-out-lights ON/OFF setup of 7 7 dots matrix LED by LEDCTL terminal.
[0] : Putting-out-lights control OFF by LEDCTL terminal. (default)
[1] : Putting-out-lights control ON by LEDCTL terminal.
D1 : DISRGB A putting-out-lights ON/OFF setup of R, G and B terminal by LEDCTL terminal.
[0] : Putting-out-lights control OFF by LEDCTL terminal. (default)
[1] : Putting-out-lights control ON by LEDCTL terminal.
Page 41 of 64
Established : 2007-05-24
Revised
: 2013-04-15
Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
OPERATION (continued)
4. Register and Address (continued)
• Register map detailed explanation (continued)
Sub Address
DATA
D7
D6
D5
D4
Data Name
10h
D0
0
0
0
0
0
0
0
0
mode
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
D3
D2
D1
D0
DATA
D7
D6
D5
D4
For test
Default
0
0
0
0
0
0
0
0
mode
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
D3
D2
D1
D0
Sub Address
DATA
D7
D6
D5
D4
Data Name
For test
Default
0
0
0
0
0
0
0
0
mode
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
D3
D2
D1
D0
Sub Address
DATA
D7
D6
D5
D4
For test
Data Name
13h
D1
For test
Data Name
12h
D2
Default
Sub Address
11h
D3
Default
0
0
0
0
0
0
0
0
mode
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
*Don’t access to address from 10h to 13h.
Page 42 of 64
Established : 2007-05-24
Revised
: 2013-04-15
Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
OPERATION (continued)
4. Register and Address (continued)
• Register map detailed explanation (continued)
DATA
Sub Address
14h
D7
D6
D5
D4
D3
D2
D1
D0
Data Name
FACGD1
—
—
—
RAMACT
FRMINT
CPUWRER
TSD
Default
0
0
0
0
0
0
0
0
mode
R
R
R
R
R
R
R
R
D7 : FACGD1
[0] : Normal operation (default)
[1] : No read clearance
D3 : RAMACT
Internal RAM access judgment
[0] : RAM is not accessed. (default)
[1] : RAM is accessed.
D2 : FRMINT
Frame display end judgment during scroll display
[0] : Under frame display (default)
[1] : Frame display end
D1 : CPUWRER CPU access error judgment
[0] : CPU access error does not occur. (default)
[1] : CPU access error occurs.
D0 : TSD Abnormal detection of TSD error
[0] : TSD abnormal detection does not occur. (default)
[1] : TSD abnormal detection occurs.
•
•
•
•
•
•
•
•
•
CPUWRER indicates the error when CPU writes the data to 31h to 64h during copying from ROM to RAM1 or RAM2.
The WRITE contents from CPU are not reflected in this LSI at CPUWRER = High. Write from CPU again.
The interval of FACGD1 = "1" is maximum 1.93 s (at the internal clock operation) from the renewal time of data.
At FACGD1 = "1", if address 14h data is read, data of D0 to D6 are cleared.
RAM access from CPU cannot be performed at RAMACT = "1" .
When each address 14h register is set to High, the pulse in a cycle of 4 ms is output from INT.
The pulse output from INT continues an output until address 14h is read.
RSTB terminal = Low can reset to stop the INT pulse signal in case of that the serial read function is not used.
The states for RAMACT = "1" are shown below.
1. While copying to RAM from ROM.
2. While clearing RAM
Page 43 of 64
Established : 2007-05-24
Revised
: 2013-04-15
Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
OPERATION (continued)
4. Register and Address (continued)
• Register map detailed explanation (continued)
DATA
Sub Address
D7
D6
D5
D4
Data Name
15h
0
0
0
0
0
0
0
mode
R
R
R
R
R
R
R
R
D3
D2
D1
D0
DATA
D7
D6
D5
D4
For test
Default
0
0
0
0
0
0
0
0
mode
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
D3
D2
D1
D0
DATA
D7
D6
D5
D4
Data Name
For test
Default
0
0
0
0
0
0
0
0
mode
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
D3
D2
D1
D0
DATA
Sub Address
D7
D6
D5
D4
Data Name
For test
Default
0
0
0
0
0
0
0
0
mode
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
D3
D2
D1
D0
DATA
Sub Address
D7
D6
D5
D4
Data Name
19h
D0
0
Sub Address
18h
D1
Default
Data Name
17h
D2
For test
Sub Address
16h
D3
For test
Default
0
0
0
0
0
0
0
0
mode
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
*Don’t access to address from 15h to 19h.
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OPERATION (continued)
4. Register and Address (continued)
• Register map detailed explanation (continued)
Sub Address
1Ah
DATA
D7
D6
D5
D4
D3
D2
D1
D0
Data Name
INTVSEL
—
—
—
—
—
—
—
Default
0
0
0
0
0
0
0
0
mode
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
D7 : INTVSEL The voltage setup of INT terminal
[0] : 1.85 V (default)
[1] : 2.85 V
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AN32058A
OPERATION (continued)
4. Register and Address (continued)
• Register map detailed explanation (continued)
Sub Address
20h
DATA
D7
D6
D5
D4
D3
D2
D1
D0
Data Name
—
—
—
—
—
—
—
MTXON
Default
0
0
0
0
0
0
0
0
mode
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
D0 : MTXON ON/OFF setup of matrix LED
[0] : OFF (default)
[1] : ON
• During MTXON = "1", subsequent ROM, RAM, and the control contents to a register are sequentially
processed and lit up.
• Wait 5 ms when MTXON is set to "1" after address 01h OSCEN is set to "1".
• Set MTXON to "1", and then set up other addresses to display the matrix part.
Sub Address
DATA
D7
D6
D5
Data Name
21h
D4
D3
D2
D1
D0
MTXDATA[7:0]
Default
0
0
0
0
0
0
0
0
mode
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
D7-0 : MTXDATA[7:0] Address setup of ROM/RAM of the data to read
[00000000] - [10010101] : ROM ( Only luminosity )
77 pattern No.0 (default) to No.149
[10010110] - [11010000] : ROM ( Luminosity + Cycle + Delay )
77 pattern No. 150 to No.208
[11010001] : RAM ( Luminosity + Cycle + Delay )
77 pattern RAM No.1
[11010010] : RAM ( Luminosity + Cycle + Delay )
77 pattern RAM No.2
The pattern No.0 of ROM is all "0" data of matrix LED.
Accessing to 21h is disabled while copying from ROM to RAM (COPYSTART 24h = "1").
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Product Standards
AN32058A
OPERATION (continued)
4. Register and Address (continued)
• Register map detailed explanation (continued)
Sub Address
22h
DATA
D7
D6
D5
D4
D3
D2
D1
D0
Data Name
—
—
—
—
—
—
ROM77[1:0]
Default
0
0
0
0
0
0
0
0
mode
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
D1-0 : ROM77[1:0] Lighting control of the 77 (LED No.A1-G7) fixed pattern of ROM
[00] : ROM data is displayed.
[01] : ROM data is displayed by firefly lighting in 1 s.
[10] : ROM data is displayed by firefly lighting in 2 s.
[11] : ROM data is displayed by firefly lighting in 3 s
During display of repetition (REPON = "1"), ROM77 must not be changed.
The peak value of luminosity is
a value set up by ROM.
Luminosity
t1 = t2 = t4 = 249.2 ms
t3 = 265.8 ms
Firefly lighting cycle : T
t2
t1
t4
t3
t
A
B
C
D
E
F
G
LED’s number
1
2
3
4
5
6
7
LED’s number
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Product Standards
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OPERATION (continued)
4. Register and Address (continued)
• Register map detailed explanation (continued)
Sub Address
DATA
D7
D6
D5
D4
D2
D1
D0
SELROM[7:0]
Data Name
23h
D3
Default
0
0
0
0
0
0
0
0
mode
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
D7-0 : SELROM[7:0] Address setup of ROM copied to RAM
[00000000] - [10010101] : ROM (Only luminosity) 77 pattern No.0 (default) to No.149
[10010110] - [11010000] : ROM (Luminosity + Cycle + Delay) 77 pattern No.150 to No.208
Accessing to 23h is disabled while copying from ROM to RAM (COPYSTART 24h = "1").
Sub Address
24h
DATA
D7
D6
D5
D4
D3
D2
D1
D0
Data Name
—
—
—
—
—
—
SELRAM
COPYSTART
Default
0
0
0
0
0
0
0
0
mode
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
D1 : SELRAM RAM number setup of a copy place.
[0] : RAM No.1
[1] : RAM No.2
D0 : COPYSTART Copy start ON/OFF control to RAM from ROM
[0] : OFF
[1] : The copy set up by SELROM and SELRAM is started. (It returns to 0 by internal 51 CLK.)
Address 24h is only for copying data to RAM and never start LED display.
(However, if this RAM is copied when LED display is showing, LED display is updated.)
Writing in address 21h-MTXDATA, 2Ah-SCLON, and 27h-REPON is disabled while copying.
(RAMACT flag is raised.)
Accessing to SELRAM is disabled while copying from ROM to RAM (COPYSTART 24h = "1")
Don’t write address 29h (RAM-clear ) while copying.
(The waiting time for over 1 ms is required after COPYSTART.)
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Product Standards
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OPERATION (continued)
4. Register and Address (continued)
• Register map detailed explanation (continued)
Sub Address
DATA
D7
D6
D5
D3
D2
D1
D0
SETFROM[7:0]
Data Name
25h
D4
Default
0
0
0
0
0
0
0
0
mode
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
D2
D1
D0
D7-0 : SETFROM[7:0] An address setup of the ROM frame data at the repetition display start.
[00000000] - [10010101] : ROM (Only luminosity) 77 pattern No.0 (default) to No.149
[10010110] - [11010000] : ROM (Luminosity + Cycle + Delay) 77 pattern No.150 to No.208
During display of repetition (REPON = "1"), Don’t change the setting of SETFROM.
Sub Address
DATA
D7
D6
D5
Data Name
26h
D4
D3
SETTO[7:0]
Default
0
0
0
0
0
0
0
0
mode
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
D7-0 : SETTO[7:0] Address setup of the ROM frame data at the repetition display end
[00000000] - [10010101] : ROM (Only luminosity) 77 pattern No.0 (default) to No.149
[10010110] - [11010000] : ROM (Luminosity + Cycle + Delay) 77 pattern No.150 to No.208
During display of repetition (REPON = "1"), don’t change the setting of SETTO.
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OPERATION (continued)
4. Register and Address (continued)
• Register map detailed explanation (continued)
Sub Address
27h
DATA
D7
D6
D5
D4
D3
D2
D1
D0
Data Name
—
—
—
—
—
—
—
REPON
Default
0
0
0
0
0
0
0
0
mode
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
D0 : REPON Repetition display ON/OFF control
[0] : Repetition display OFF (default)
[1] : Repetition display ON
During display of repetition, display of set-up ROM is continued.
A repetition display is started in the state of MTXON = "1" and REPON = "1".
Accessing to 27h is disabled while copying from ROM to RAM (COPYSTART 24h = "1").
When the setting of SCLON is changed from Low to High while REPON = "1", REPON becomes "0" and it shifts
to scroll function.
During display of repetition (REPON = "1"), don’t change the setting of SETFROM and SETTO.
Sub Address
28h
DATA
D7
D6
D5
D4
D3
D2
D1
D0
Data Name
—
—
—
—
—
—
SETTIME[1:0]
Default
0
0
0
0
0
0
0
0
mode
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
D1-0 : SETTIME[1:0] A frame display time setup of repetition display
[00] : 1 s (default)
[01] : 2 s
[10] : 3 s
[11] : 4 s
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OPERATION (continued)
4. Register and Address (continued)
• Register map detailed explanation (continued)
Sub Address
29h
DATA
D7
D6
D5
D4
D3
D2
D1
D0
Data Name
—
—
—
—
—
—
RAM1
RAM2
Default
0
0
0
0
0
0
0
0
mode
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
D1 : RAM1 The data in 77 RAM1 is cleared.
0 : Overwrite is possible. (default)
1 : The data in 77 RAM1 is cleared. (It returns to 0 by internal 2 CLK.)
D0 : RAM2 The data in 77 RAM2 is cleared.
0 : Overwrite is possible. (default)
1 : The data in 77 RAM2 is cleared. (It returns to 0 by internal 2 CLK.)
Don’t set the RAM-clear operation for RAM1 or RAM2 during display of repetition (SCLON = "1").
Don’t set the RAM-clear operation (29h) during the COPY operation (24h).
(The waiting time for over 1 ms is required after COPYSTART.)
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OPERATION (continued)
4. Register and Address (continued)
• Register map detailed explanation (continued)
Sub Address
2Ah
DATA
D7
D6
D5
D4
D3
D2
D1
D0
Data Name
—
—
—
—
—
—
—
SCLON
Default
0
0
0
0
0
0
0
0
mode
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
D0 : SCLON ON/OFF setup of scroll display
[0] : OFF (default)
[1] : ON
• The scroll display displays the data which exists in the RAM No.1-2 of 77 in order of A-G column. The display
travel time of a column is the preset value of SCLTIME.
• During display of scroll, data can be written to RAM without specifying RAM number.
(Writing is performed to empty RAM.)
• The scroll display is started in the state of MTXON = "1" and SCLON.
• Accessing to 2Ah is disabled while copying from ROM to RAM (COPYSTART 24h = "1").
• When the setting of REPON is changed from "0" to "1" while SCLON = "1", SCLON becomes "0" and it shifts to
repetition display function.
• During display of scroll (SCLON = "1"), don’t change the setting of RAM1 and RAM2.
• Once the scroll function was set, then the SCLON = "0" or MTXON = "0", RSTB terminal must be "L" to reset
before the scroll function is set again.
Sub Address
2Bh
DATA
D7
D6
D5
D4
D3
D2
D1
D0
Data Name
—
—
—
—
—
—
SCLTIME[1:0]
Default
0
0
0
0
0
0
0
0
mode
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
D1-0 : SCLTIME[1:0] Frame display time setup of scroll display
[00] : 0.1 s (default)
[01] : 0.2 s
[10] : 0.4 s
[11] : 0.8 s
The display travel time of the column is the preset value of SCLTIME.
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OPERATION (continued)
4. Register and Address (continued)
• Register map detailed explanation (continued)
Sub Address
2Ch
DATA
D7
D6
D5
D4
D3
D2
D1
D0
Data Name
—
—
—
—
—
—
—
RGBON
Default
0
0
0
0
0
0
0
0
mode
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
D2
D1
D0
D0 : RGBON ON/OFF setup of RGB lighting
[0] : OFF (default)
[1] : ON
Wait 5 ms when RGBON is set to "1" after address 01h OSCEN is set to "1".
Sub Address
2Dh
DATA
D7
D6
D5
D4
D3
Data Name
—
—
Default
0
0
0
0
0
0
0
0
mode
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
D2
D1
D0
RGBDATA[5:0]
D7-0 : RGBDATA[5:0] Address setup of ROM and register which read RGB data
[000000] : Register is displayed.
[000001] - [101010] : ROM (RGB pattern, Luminosity + Cycle + Delay) pattern No.1 to No.42
Sub Address
DATA
D7
D6
D5
D4
For test
Data Name
2Eh
D3
Default
0
0
0
0
0
0
0
0
mode
R
R
R
R
R
R
R
R
*Don’t access to address 2Eh.
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AN32058A
OPERATION (continued)
4. Register and Address (continued)
• Register map detailed explanation (continued)
Sub Address
30h
DATA
D7
D6
D5
D4
D3
D2
D1
D0
Data
Name
—
—
—
—
—
—
—
RAMNUM
Default
0
0
0
0
0
0
0
0
mode
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
D1-0 : RAMNUM[1:0] RAM number setup at the CPU access (READ and WRITE).
[0] : RAM No.1
[1] : RAM No.2
Accessing to 30h is disabled during display of scroll (2Ah SCLON = "1").
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Product Standards
AN32058A
OPERATION (continued)
4. Register and Address (continued)
• Register map detailed explanation (continued)
Sub Address
DATA
D7
D6
D4
D3
BLA1[3:0]
Data Name
31h
D5
D2
D1
FRA1[1:0]
D0
DLA1[1:0]
Default
0
0
0
0
0
0
0
0
mode
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
A
B
C
D
E
F
G
LED‘s number
1
2
3
4
5
6
7
LED‘s number
D7-4 : BLA1[1:0] Luminosity setup of LED No.A1
[0000] : 0 mA (default)
[0001] : 1 mA
[0010] : 2 mA
[0011] : 3 mA
[0100] : 4 mA
[0101] : 5 mA
[0110] : 8 mA
[0111] : 11 mA
[1000] : 15 mA
[1001] : 17 mA
[1010] : 19 mA
[1011] : 21 mA
[1100] : 24 mA
[1101] : 26 mA
[1110] : 28 mA
[1111] : 30 mA
D3-2 : FRA1[1:0] Firefly operation and cycle setup of the LED No.A1
[00] : Lighting mode (default)
[01] : Firefly lighting cycle 1 s
[10] : Firefly lighting cycle 2 s
[11] : Firefly lighting cycle 3 s
D1-0 : DLA1[1:0] Firefly operation delay setup of the LED No.A1
[00] : No delay (default)
[01] : Delay 25%
[10] : Delay 50%
[11] : Delay 75%
• The operation is the same as above for the addresses to 61h corresponding to each LED number.
• The waiting time for 2 or more internal clocks (2 s or more) is required after the data from address 31h to 61h
is written in. Please input other serial commands after that.
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Product Standards
AN32058A
OPERATION (continued)
4. Register and Address (continued)
• Register map detailed explanation (continued)
Sub Address
DATA
D7
D5
D4
BLLEDR[3:0]
Data Name
62h
D6
D3
D2
D1
D0
FRLEDR[1:0]
DLLEDR[1:0]
Default
0
0
0
0
0
0
0
0
mode
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
D7-4 : BLLEDR1[1:0] Luminosity setup of R1 terminal
[0000] : 0 mA (default)
[0001] : 1 mA
[0010] : 2 mA
:
:
[1110] : 14 mA
[1111] : 15 mA
D3-2 : FRLEDR1[1:0] Firefly operation and cycle setup of R1 terminal
[00] : Lighting mode (default)
[01] : Firefly lighting cycle 1 s
[10] : Firefly lighting cycle 2 s
[11] : Firefly lighting cycle 3 s
D1-0 : DLLEDR1[1:0] Firefly operation delay setup of R1 terminal
[00] : No delay (default)
[01] : Delay 25%
[10] : Delay 50%
[11] : Delay 75%
The operation is the same as above for the addresses to 64h corresponding to G and B terminal.
The waiting time for 2 or more internal clocks (2 s or more) is required after the data from address 62h to 64h is
written in. Please input other serial commands after that.
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Product Standards
AN32058A
OPERATION (continued)
4. Register and Address (continued)
• Register map detailed explanation (continued)
Sub Address
DATA
D7
D6
D5
D4
Data Name
6Bh
D3
D2
D1
D0
For test
Default
0
0
0
0
0
0
0
0
mode
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
*Address from 6Bh onwards are registers for test. Don't write into these addresses.
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Product Standards
AN32058A
OPERATION (continued)
5. Serial interface format
• SPI format
• The interface with microcomputer consists of 16 bit-serial register (8-bit of command, 8-bit of address), and
address decoder and transmitting register (8-bit).
• Serial interface consists of four terminals of serial clock terminal (CLK), serial-data input terminal (DI), serial-data
output terminal (DO), and chip enable input terminal (CE).
(1) Write operation
• Data is taken into internal shift register by the rising edge of CLK. (Maximum 13 MHz of frequency of CLK can
be used)
• Serial interface consists of four terminals of serial clock terminal (CLK), serial-data input terminal (DI), serialdata output terminal (DO), and chip enable input terminal (CE).
• Data is transmitted at MSB first in order of a control register address (8-bit) and control command (8-bit).
Write access Timing
CE
CLK
A6
W
DI
A5
A4
A3
A2
A1
A0
DO
D7
D6
D5
D4
D3
D2
D1
D0
0
(2) Transmission operation
• Data is taken into internal shift register by the rising edge of CLK. (A maximum of 6 MHz of frequency of CLK
can be used)
• It is not possible to read RAM data.
• In High interval of CE, reception of data becomes ENABLE. (active : High)
• Data is transmitted at MSB first in order of a control register address (8-bit) and control command (max 8-bit).
Read access Timing
CE
CLK
DI
R
A6
A5
DO
A4
A3
0
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
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OPERATION (continued)
6. Signal distribution diagram
• Power supply distribution diagram
VB
VLED1
VLED2
LDO1
LDO2
BGR
TSD
LDO1
LDO2
OSC
I/O*
LOGIC
MTX
RGB
SCAN
AGND
PGND
RGBGND
*CLK, CE, DI, DO, LEDCTL
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AN32058A
OPERATION (continued)
6. Signal distribution diagram (continued)
• Control / Clock distribution diagram
Oscillator
1.2 MHz
(PAD) CLK
REGMAP
Matrix
RGB
* Matrix, RGB operation
PWM control
Read / Write of memory data (ROM and RAM)
14h RAMACT, FRMINT, CPUWRER
SPI
* Serial Parallel conversion
SCLK Serial Parallel conversion (input)
SCLK_N Parallel Serial conversion (output)
REGCLK Serial Parallel conversion output
is latched in a standup.
SCLK
SCLK_N
(PAD) CE
(PAD) DI
REGCLK
(PAD) DO
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Product Standards
AN32058A
OPERATION (continued)
7. Example of firefly lighting
• Example of firefly lighting 1
BLA1[3:0]
Example of initial
setting for lighting
1
0
FRA1[1:0]
0
0
0
DLA1[1:0]
0
0
0
Current value
15 mA
A1
BLA1 = [1000]
Serial ON
t
BLA1[3:0]
Firefly lighting
setup 1 s
1
1
FRA1[1:0]
1
1
0
DLA1[1:0]
1
0
0
Firefly lighting cycle T = 1.0134 s
FRA1 = [01]
Current value
30 mA
A1
Serial ON
t
BLA1 = [1111]
BLA1[3:0]
Change to cycle
1 s to 2 s
1
1
FRA1[1:0]
1
1
1
DLA1[1:0]
0
0
0
Firefly lighting cycle T2 = 2.0268 s
FRA1 = [10]
Current value
30 mA
A1
Serial ON
t
BLA1 = [1111]
BLA1[3:0]
Change to delay
0 25 %
1
DLA1 = [01]
Current value
1
FRA1[1:0]
1
1
Firefly lighting cycle T2 = 2.0268 s
FRA1 = [10]
t5
1
t6
DLA1[1:0]
0
t7
0
t8
1
t5 = t6 = t8 = 498.4 ms
t7 = 531.6 ms
30 mA
A1
Serial ON
BLA1 = [1111]
t
Page 61 of 64
Established : 2007-05-24
Revised
: 2013-04-15
Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
OPERATION (continued)
7. Example of firefly lighting (continued)
• Example of firefly lighting 2
Firefly lighting cycle T1 = 3.040 2 s
FRA1 = [11]
t1 = t2 = t4 = 747.6 ms
t3 = 797.4 ms
t1
t2
t3
t4
Luminance
A1
BLA1
t
t1 = t2 = t4 = 747.6 ms
Firefly lighting cycle T1 = 3.040 2 s t3 = 797.4 ms
FRE7 = [11]
DLE7 = [11]
t1
t2
t3
t4
Luminance
E7
BLE7
t
DLC5 = [01]
t5 = t6 = t8 = 498.4 ms
t7 = 531.6 ms
Firefly lighting cycle T2 = 2.026 8 s
FRC5 = [10]
t5
t6
t7
t8
Luminance
C5
BLC5
t
t9 = t10 = t12 = 249.2 ms
t11 = 265.8 ms
DLF3 = [10]
Firefly lighting cycle T3 = 1.013 4 s
t10
t11
FRF3 = [01]
t12
t9
Luminance
F3
t
BLF3
1. Normally, it is not possible to control data when RGBGND pin voltage is undefined. Therefore, please keep the RGBGND
pin voltage at the lowest voltage.
2. Please check the input waveform to the CLK pin. When inputting clock into the CLK pin, if the input clock is ringing with
input voltage between 0.4 V to LDO1 0.8 V (input voltage indefinite range), it will result in serial data not able to be
written to or be read out from a register. (It is recommended to smooth the rising and falling edge of the input clock by
connecting input capacitance (a capacitor, etc.) to the CLK pin.)
Page 62 of 64
Established : 2007-05-24
Revised
: 2013-04-15
Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
PACKAGE INFORMATION ( Reference Data )
Page 63 of 64
Established : 2007-05-24
Revised
: 2013-04-15
Doc No. TA4-EA-04725
Revision. 3
Product Standards
AN32058A
IMPORTANT NOTICE
1. When using the LSI for new models, verify the safety including the long-term reliability for each product.
2. When the application system is designed by using this LSI, please confirm the notes in this book.
Please read the notes to descriptions and the usage notes in the book.
3. This LSI is intended to be used for general electronic equipment.
Consult our sales staff in advance for information on the following applications: Special applications in which exceptional
quality and reliability are required, or if the failure or malfunction of this LSI may directly jeopardize life or harm the human
body.
Any applications other than the standard applications intended.
(1) Space appliance (such as artificial satellite, and rocket)
(2) Traffic control equipment (such as for automobile, airplane, train, and ship)
(3) Medical equipment for life support
(4) Submarine transponder
(5) Control equipment for power plant
(6) Disaster prevention and security device
(7) Weapon
(8) Others : Applications of which reliability equivalent to (1) to (7) is required
Our company shall not be held responsible for any damage incurred as a result of or in connection with the LSI being used for
any special application, unless our company agrees to the use of such special application.
4. This LSI is neither designed nor intended for use in automotive applications or environments unless the specific product is
designated by our company as compliant with the ISO/TS 16949 requirements.
Our company shall not be held responsible for any damage incurred by customers or any third party as a result of or in
connection with the LSI being used in automotive application, unless our company agrees to such application in this book.
5. Please use this product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled
substances, including without limitation, the EU RoHS Directive. Our company shall not be held responsible for any damage
incurred as a result of our LSI being used by our customers, not complying with the applicable laws and regulations.
6. Pay attention to the direction of LSI. When mounting it in the wrong direction onto the PCB (printed-circuit-board), it might emit
smoke or ignite.
7. Pay attention in the PCB (printed-circuit-board) pattern layout in order to prevent damage due to short circuit between pins. In
addition, refer to the Pin Description for the pin configuration.
8. Perform visual inspection on the PCB before applying power, otherwise damage might happen due to problems such as
solder-bridge between the pins of the semiconductor device. Also, perform full technical verification on the assembly quality,
because the same damage possibly can happen due to conductive substances, such as solder ball, that adhere to the LSI
during transportation.
9. Take notice in the use of this product that it might be damaged or occasionally emit smoke when an abnormal state occurs
such as output pin-VCC short (Power supply fault), output pin-GND short (Ground fault), or output-to-output-pin short (load
short). Safety measures such as installation of fuses are recommended because the extent of the above-mentioned damage
and smoke emission will depend on the current capability of the power supply.
10. The protection circuit is for maintaining safety against abnormal operation. Therefore, the protection circuit should not work
during normal operation.
Especially for the thermal protection circuit, if the area of safe operation or the absolute maximum rating is momentarily
exceeded due to output pin to VCC short (Power supply fault), or output pin to GND short (Ground fault), the LSI might be
damaged before the thermal protection circuit could operate.
11. Unless specified in the product specifications, make sure that negative voltage or excessive voltage are not applied to the
pins because the device might be damaged, which could happen due to negative voltage or excessive voltage generated
during the ON and OFF timing when the inductive load of a motor coil or actuator coils of optical pick-up is being driven.
12. Verify the risks which might be caused by the malfunctions of external components.
Page 64 of 64
Established : 2007-05-24
Revised
: 2013-04-15
Request for your special attention and precautions in using the technical information and
semiconductors described in this book
(1) If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and
regulations of the exporting country, especially, those with regard to security export control, must be observed.
(2) The technical information described in this book is intended only to show the main characteristics and application circuit examples
of the products. No license is granted in and to any intellectual property right or other right owned by Panasonic Corporation or any
other company. Therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any
other company which may arise as a result of the use of technical information described in this book.
(3) The products described in this book are intended to be used for general applications (such as office equipment, communications
equipment, measuring instruments and household appliances), or for specific applications as expressly stated in this book.
Consult our sales staff in advance for information on the following applications:
– Special applications (such as for airplanes, aerospace, automotive equipment, traffic signaling equipment, combustion equipment,
life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of
the products may directly jeopardize life or harm the human body.
It is to be understood that our company shall not be held responsible for any damage incurred as a result of or in connection with
your using the products described in this book for any special application, unless our company agrees to your using the products in
this book for any special application.
(4) The products and product specifications described in this book are subject to change without notice for modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product
Standards in advance to make sure that the latest specifications satisfy your requirements.
(5) When designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions
(operating power supply voltage and operating environment etc.). Especially, please be careful not to exceed the range of absolute
maximum rating on the transient state, such as power-on, power-off and mode-switching. Otherwise, we will not be liable for any
defect which may arise later in your equipment.
Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure
mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire
or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products.
(6) Comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (ESD, EOS,
thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. When using products for which
damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages.
(7) This book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of our company.
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