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TSZ121, TSZ122, TSZ124
Very high accuracy (5 µV) zero drift micropower 5 V operational
amplifiers
Datasheet - production data
Benefits
Higher accuracy without calibration
Accuracy virtually unaffected by temperature
change
Related products
See TSV711 or TSV731 for continuous-time
precision amplifiers
Applications
Battery-powered applications
Portable devices
Signal conditioning
Medical instrumentation
Description
The TSZ12x series of high precision operational
amplifiers offer very low input offset voltages with
virtually zero drift.
Features
Very high accuracy and stability: offset
voltage 5 µV max at 25 °C, 8 µV over full
temperature range (-40 °C to 125 °C)
Rail-to-rail input and output
Low supply voltage: 1.8 - 5.5 V
Low power consumption: 40 µA max. at 5 V
Gain bandwidth product: 400 kHz
High tolerance to ESD: 4 kV HBM
Extended temperature range: -40 to 125 °C
Micro-packages: SC70-5, DFN8 2x2, and
QFN16 3x3
May 2016
TSZ121 is the single version, TSZ122 the dual
version, and TSZ124 the quad version, with
pinouts compatible with industry standards.
The TSZ12x series offers rail-to-rail input and
output, excellent speed/power consumption ratio,
and 400 kHz gain bandwidth product, while
consuming less than 40 µA at 5 V. The devices
also feature an ultra-low input bias current.
These features make the TSZ12x family ideal for
sensor interfaces, battery-powered applications
and portable applications.
DocID023563 Rev 5
This is information on a product in full production.
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www.st.com
Contents
TSZ121, TSZ122, TSZ124
Contents
1
Package pin connections................................................................ 3
2
Absolute maximum ratings and operating conditions ................. 4
3
Electrical characteristics ................................................................ 5
4
5
Electrical characteristic curves .................................................... 11
Application information ................................................................ 17
5.1
6
Operation theory ............................................................................. 17
5.1.1
Time domain ..................................................................................... 17
5.1.2
Frequency domain ............................................................................ 18
5.2
Operating voltages .......................................................................... 19
5.3
Input pin voltage ranges .................................................................. 19
5.4
Rail-to-rail input ............................................................................... 19
5.5
Input offset voltage drift over temperature ....................................... 20
5.6
Rail-to-rail output ............................................................................. 20
5.7
Capacitive load................................................................................ 20
5.8
PCB layout recommendations ......................................................... 21
5.9
Optimized application recommendation .......................................... 21
5.10
EMI rejection ration (EMIRR) .......................................................... 22
5.11
Application examples ...................................................................... 22
5.11.1
Oxygen sensor ................................................................................. 22
5.11.2
Precision instrumentation amplifier .................................................. 23
5.11.3
Low-side current sensing.................................................................. 24
Package information ..................................................................... 25
6.1
SC70-5 (or SOT323-5) package information ................................... 26
6.2
SOT23-5 package information ........................................................ 27
6.3
DFN8 2x2 package information ....................................................... 29
6.4
MiniSO8 package information ......................................................... 31
6.5
SO8 package information ................................................................ 32
6.6
QFN16 3x3 package information..................................................... 33
6.7
TSSOP14 package information ....................................................... 35
7
Ordering information..................................................................... 36
8
Revision history ............................................................................ 37
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DocID023563 Rev 5
TSZ121, TSZ122, TSZ124
1
Package pin connections
Package pin connections
Figure 1: Pin connections for each package (top view)
1.
The exposed pads of the DFN8 2x2 and the QFN16 3x3 can be connected to VCC- or left floating.
DocID023563 Rev 5
3/38
Absolute maximum ratings and operating
conditions
2
TSZ121, TSZ122, TSZ124
Absolute maximum ratings and operating conditions
Table 1: Absolute maximum ratings (AMR)
Symbol
VCC
Vid
Vin
Iin
Tstg
Tj
Rthja
Parameter
Supply voltage
Unit
6
Differential input voltage
(2)
±VCC
Input voltage
(3)
(VCC-) - 0.2 to (VCC+) + 0.2
Input current
(4)
10
Storage temperature
V
mA
-65 to 150
°C
Maximum junction temperature
Thermal resistance junction to
(5) (6)
ambient
HBM: human body model
ESD
Value
(1)
MM: machine model
150
SC70-5
205
SOT23-5
250
DFN8 2x2
57
MiniSO8
190
SO8
125
QFN16 3x3
39
TSSOP14
100
(7)
(8)
CDM: charged device model
(9)
Latch-up immunity
°C/W
4
kV
300
V
1.5
kV
200
mA
Notes:
(1)
(2)
(3)
(4)
(5)
(6)
All voltage values, except the differential voltage are with respect to the network ground terminal.
The differential voltage is the non-inverting input terminal with respect to the inverting input terminal.
Vcc - Vin must not exceed 6 V, Vin must not exceed 6 V
Input current must be limited by a resistor in series with the inputs.
Rth are typical values.
Short-circuits can cause excessive heating and destructive dissipation.
(7)
Human body model: 100 pF discharged through a 1.5 kΩ resistor between two pins of the device, done for all
couples of pin combinations with other pins floating.
(8)
Machine model: a 200 pF cap is charged to the specified voltage, then discharged directly between two pins of
the device with no external series resistor (internal resistor < 5 Ω), done for all couples of pin combinations with
other pins floating.
(9)
Charged device model: all pins plus package are charged together to the specified voltage and then discharged
directly to ground.
Table 2: Operating conditions
Symbol
4/38
Parameter
VCC
Supply voltage
Vicm
Common mode input voltage range
Toper
Operating free air temperature range
Value
1.8 to 5.5
DocID023563 Rev 5
(VCC-) - 0.1 to (VCC+) + 0.1
-40 to 125
Unit
V
°C
TSZ121, TSZ122, TSZ124
3
Electrical characteristics
Electrical characteristics
Table 3: Electrical characteristics at VCC+ = 1.8 V with VCC- = 0 V, Vicm = VCC/2, T = 25 ° C,
and RL = 10 kΩ connected to VCC/2 (unless otherwise specified)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
1
5
Unit
DC performance
Vio
ΔVio/ΔT
T = 25 °C
Input offset voltage
Input offset voltage drift
-40 °C < T < 125 °C
(1)
Iib
Input bias current
(Vout = VCC/2)
Iio
Input offset current
(Vout = VCC/2)
CMR
Common mode rejection
ratio, 20 log (ΔVicm/ΔVio),
Vic = 0 V to VCC,
Vout = VCC/2, RL > 1 MΩ
Avd
VOH
VOL
Large signal voltage gain,
Vout = 0.5 V to (VCC - 0.5 V)
High-level output voltage
Low-level output voltage
Isink (Vout = VCC)
Iout
Isource (Vout = 0 V)
ICC
Supply current
(per amplifier, Vout = VCC/2,
RL > 1 MΩ)
-40 °C < T < 125 °C
10
T = 25 °C
50
-40 °C < T < 125 °C
T = 25 °C
100
-40 °C < T < 125 °C
T = 25 °C
110
-40 °C < T < 125 °C
110
T = 25 °C
118
-40 °C < T < 125 °C
110
30
200
300
(2)
400
(2)
600
(2)
dB
135
-40 °C < T < 125 °C
70
T = 25 °C
30
-40 °C < T < 125 °C
70
7
-40 °C < T < 125 °C
6
T = 25 °C
5
-40 °C < T < 125 °C
4
pA
122
30
T = 25 °C
nV/°C
(2)
T = 25 °C
T = 25 °C
μV
8
mV
8
mA
7
28
-40 °C < T < 125 °C
40
40
μA
AC performance
GBP
Gain bandwidth product
400
Fu
Unity gain frequency
300
ɸm
Phase margin
Gm
Gain margin
SR
(3)
Slew rate
RL = 10 kΩ, CL = 100 pF
kHz
55
Degrees
17
dB
0.17
V/μs
To 0.1 %, Vin = 1 Vp-p,
RL = 10 kΩ, CL = 100 pF
50
μs
ts
Setting time
en
Equivalent input noise
voltage
f = 1 kHz
60
f = 10 kHz
60
Cs
Channel separation
f = 100 Hz
120
DocID023563 Rev 5
nV/√Hz
dB
5/38
Electrical characteristics
Symbol
Parameter
tinit
Initialization time
TSZ121, TSZ122, TSZ124
Conditions
Min.
Typ.
T = 25 °C
50
-40 °C < T < 125 °C
100
Max.
Notes:
(1)
See Section 5.5: "Input offset voltage drift over temperature". Input offset measurements are performed on x100 gain
configuration. The amplifiers and the gain setting resistors are at the same temperature.
(2)
(3)
Guaranteed by design
Slew rate value is calculated as the average between positive and negative slew rates.
6/38
DocID023563 Rev 5
Unit
μs
TSZ121, TSZ122, TSZ124
Electrical characteristics
Table 4: Electrical characteristics at VCC+ = 3.3 V with VCC- = 0 V, Vicm = VCC/2, T = 25 ° C,
and RL = 10 kΩ connected to VCC/2 (unless otherwise specified)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
1
5
Unit
DC performance
Vio
ΔVio/ΔT
T = 25 °C
Input offset voltage
Input offset voltage drift
-40 °C < T < 125 °C
(1)
Iib
Input bias current
(Vout = VCC/2)
Iio
Input offset current
(Vout = VCC/2)
CMR
Common mode rejection
ratio, 20 log (ΔVicm/ΔVio),
Vic = 0 V to VCC,
Vout = VCC/2, RL > 1 MΩ
Avd
Large signal voltage gain,
Vout = 0.5 V to (VCC - 0.5 V)
VOH
High-level output voltage
VOL
Low-level output voltage
Isink (Vout = VCC)
Iout
Isource (Vout = 0 V)
ICC
Supply current
(per amplifier, Vout = VCC/2,
RL > 1 MΩ)
-40 °C < T < 125 °C
10
T = 25 °C
60
-40 °C < T < 125 °C
T = 25 °C
120
-40 °C < T < 125 °C
T = 25 °C
115
-40 °C < T < 125 °C
115
T = 25 °C
118
-40 °C < T < 125 °C
110
30
200
300
(2)
400
(2)
600
(2)
dB
135
30
70
T = 25 °C
30
-40 °C < T < 125 °C
70
15
-40 °C < T < 125 °C
12
T = 25 °C
14
-40 °C < T < 125 °C
10
pA
128
T = 25 °C
T = 25 °C
nV/°C
(2)
-40 °C < T < 125 °C
T = 25 °C
μV
8
mV
18
mA
16
29
-40 °C < T < 125 °C
40
40
μA
AC performance
GBP
Gain bandwidth product
400
Fu
Unity gain frequency
300
ɸm
Phase margin
Gm
Gain margin
SR
(3)
Slew rate
RL = 10 kΩ, CL = 100 pF
56
Degrees
19
dB
0.19
V/μs
To 0.1 %, Vin = 1 Vp-p,
RL = 10 kΩ, CL = 100 pF
50
μs
ts
Setting time
en
Equivalent input noise
voltage
f = 1 kHz
40
f = 10 kHz
40
Cs
Channel separation
f = 100 Hz
120
T = 25 °C
50
-40 °C < T < 125 °C
100
tinit
Initialization time
kHz
DocID023563 Rev 5
nV/√Hz
dB
μs
7/38
Electrical characteristics
TSZ121, TSZ122, TSZ124
Notes:
(1)
See Section 5.5: "Input offset voltage drift over temperature". Input offset measurements are performed on x100 gain
configuration. The amplifiers and the gain setting resistors are at the same temperature.
(2)
(3)
Guaranteed by design
Slew rate value is calculated as the average between positive and negative slew rates.
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DocID023563 Rev 5
TSZ121, TSZ122, TSZ124
Electrical characteristics
Table 5: Electrical characteristics at VCC+ = 5 V with VCC- = 0 V, Vicm = VCC/2, T = 25 ° C, and
RL = 10 kΩ connected to VCC/2 (unless otherwise specified)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
1
5
Unit
DC performance
Vio
T = 25 °C
Input offset voltage
ΔVio/ΔT
Input offset voltage drift
-40 °C < T < 125 °C
(1)
Iib
Input bias current
(Vout = VCC/2)
Iio
Input offset current
(Vout = VCC/2)
CMR
Common mode rejection
ratio, 20 log (ΔVicm/ΔVio),
Vic = 0 V to VCC,
Vout = VCC/2, RL > 1 MΩ
SVR
Supply voltage rejection
ratio, 20 log (ΔVCC/ΔVio),
VCC = 1.8 V to 5.5 V,
Vout = VCC/2, RL > 1 MΩ
Avd
Large signal voltage gain,
Vout = 0.5 V to (VCC - 0.5 V)
EMIRR
VOH
VOL
(3)
EMI rejection rate = -20 log
(VRFpeak/ΔVio)
High-level output voltage
Low-level output voltage
Isink (Vout = VCC)
Iout
Isource (Vout = 0 V)
ICC
Supply current
(per amplifier, Vout = VCC/2,
RL > 1 MΩ)
μV
8
-40 °C < T < 125 °C
10
T = 25 °C
70
-40 °C < T < 125 °C
T = 25 °C
140
-40 °C < T < 125 °C
T = 25 °C
115
-40 °C < T < 125 °C
115
T = 25 °C
120
-40 °C < T < 125 °C
120
T = 25 °C
120
-40 °C < T < 125 °C
110
30
nV/°C
200
(2)
300
(2)
400
(2)
600
(2)
pA
136
140
dB
135
VRF = 100 mVp, f = 400 MHz
84
VRF = 100 mVp, f = 900 MHz
87
VRF = 100 mVp, f = 1800 MHz
90
VRF = 100 mVp, f = 2400 MHz
91
T = 25 °C
30
-40 °C < T < 125 °C
70
T = 25 °C
30
-40 °C < T < 125 °C
70
T = 25 °C
15
-40 °C < T < 125 °C
14
T = 25 °C
14
-40 °C < T < 125 °C
12
T = 25 °C
mV
18
mA
17
31
-40 °C < T < 125 °C
40
40
μA
AC performance
GBP
Gain bandwidth product
400
Fu
Unity gain frequency
300
ɸm
Phase margin
Gm
Gain margin
SR
(4)
Slew rate
RL = 10 kΩ, CL = 100 pF
DocID023563 Rev 5
kHz
53
Degrees
19
dB
0.19
V/μs
9/38
Electrical characteristics
TSZ121, TSZ122, TSZ124
Symbol
Parameter
Conditions
Min.
Typ.
ts
Setting time
To 0.1 %, Vin = 100 mVp-p,
RL = 10 kΩ, CL = 100 pF
10
en
Equivalent input noise
voltage
f = 1 kHz
37
f = 10 kHz
37
Cs
Channel separation
f = 100 Hz
120
tinit
Initialization time
T = 25 °C
50
-40 °C < T < 125 °C
100
Max.
Notes:
(1)
See Section 5.5: "Input offset voltage drift over temperature". Input offset measurements are performed on x100 gain
configuration. The amplifiers and the gain setting resistors are at the same temperature.
(2)
(3)
(4)
Guaranteed by design
Tested on SC70-5 package
Slew rate value is calculated as the average between positive and negative slew rates.
10/38
DocID023563 Rev 5
Unit
μs
nV/√Hz
dB
μs
TSZ121, TSZ122, TSZ124
4
Electrical characteristic curves
Electrical characteristic curves
Figure 2: Supply current vs. supply voltage
Figure 3: Input offset voltage distribution at VCC = 5 V
Figure 4: Input offset voltage distribution at VCC = 3.3 V
Figure 5: Input offset voltage distribution at VCC = 1.8 V
Figure 6: Vio temperature co-efficient distribution
(-40 °C to 25 °C)
Figure 7: Vio temperature co-efficient distribution
(25 °C to 125 °C)
DocID023563 Rev 5
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Electrical characteristic curves
TSZ121, TSZ122, TSZ124
Figure 8: Input offset voltage vs. supply voltage
Figure 9: Input offset voltage vs. input common-mode at
VCC = 1.8 V
Figure 10: Input offset voltage vs. input common-mode
at VCC = 2.7 V
Figure 11: Input offset voltage vs. input common-mode
at VCC = 5.5 V
Figure 12: Input offset voltage vs. temperature
Figure 13: VOH vs. supply voltage
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TSZ121, TSZ122, TSZ124
Electrical characteristic curves
Figure 14: VOL vs. supply voltage
Figure 15: Output current vs. output voltage
at VCC = 1.8 V
Figure 16: Output current vs. output voltage
at VCC = 5.5 V
Figure 17: Input bias current vs. common mode
at VCC = 5 V
Figure 18: Input bias current vs. common mode
at VCC = 1.8 V
Figure 19: Input bias current vs. temperature
at VCC = 5 V
DocID023563 Rev 5
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Electrical characteristic curves
TSZ121, TSZ122, TSZ124
Figure 20: Bode diagram at VCC = 1.8 V
Figure 21: Bode diagram at VCC = 2.7 V
Figure 22: Bode diagram at VCC = 5.5 V
Figure 23: Open loop gain vs. frequency
Figure 24: Positive slew rate vs. supply voltage
Figure 25: Negative slew rate vs. supply voltage
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TSZ121, TSZ122, TSZ124
Electrical characteristic curves
Figure 26: 0.1 Hz to 10 Hz noise
Figure 27: Noise vs. frequency
Figure 28: Noise vs. frequency and temperature
Figure 29: Output overshoot vs. load capacitance
Figure 30: Small signal
Figure 31: Large signal
DocID023563 Rev 5
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Electrical characteristic curves
TSZ121, TSZ122, TSZ124
Figure 32: Positive overvoltage recovery at VCC = 1.8 V
Figure 33: Positive overvoltage recovery at VCC = 5 V
Figure 34: Negative overvoltage recovery
at VCC = 1.8 V
Figure 35: Negative overvoltage recovery
at VCC = 5 V
Figure 36: PSRR vs. frequency
Figure 37: Output impedance vs. frequency
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TSZ121, TSZ122, TSZ124
Application information
5
Application information
5.1
Operation theory
The TSZ121, TSZ122, and TSZ124 are high precision CMOS devices. They achieve a low
offset drift and no 1/f noise thanks to their chopper architecture. Chopper-stabilized amps
constantly correct low-frequency errors across the inputs of the amplifier.
Chopper-stabilized amplifiers can be explained with respect to:
Time domain
Frequency domain
5.1.1
Time domain
The basis of the chopper amplifier is realized in two steps. These steps are synchronized
thanks to a clock running at 400 kHz.
Figure 38: Block diagram in the time domain (step 1)
Figure 39: Block diagram in the time domain (step 2)
Figure 38: "Block diagram in the time domain (step 1)" shows step 1, the first clock cycle,
where Vio is amplified in the normal way.
Figure 39: "Block diagram in the time domain (step 2)" shows step 2, the second clock
cycle, where Chop1 and Chop2 swap paths. At this time, the Vio is amplified in a reverse
way as compared to step 1.
At the end of these two steps, the average Vio is close to zero.
The A2(f) amplifier has a small impact on the Vio because the Vio is expressed as the input
offset and is consequently divided by A1(f).
In the time domain, the offset part of the output signal before filtering is shown in Figure 40:
"Vio cancellation principle".
DocID023563 Rev 5
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Application information
TSZ121, TSZ122, TSZ124
Figure 40: Vio cancellation principle
The low pass filter averages the output value resulting in the cancellation of the V io offset.
The 1/f noise can be considered as an offset in low frequency and it is canceled like the V io,
thanks to the chopper technique.
5.1.2
Frequency domain
The frequency domain gives a more accurate vision of chopper-stabilized amplifier
architecture.
Figure 41: Block diagram in the frequency domain
The modulation technique transposes the signal to a higher frequency where there is no 1/f
noise, and demodulate it back after amplification.
1.
2.
3.
4.
According to Figure 41: "Block diagram in the frequency domain", the input signal Vin
is modulated once (Chop1) so all the input signal is transposed to the high frequency
domain.
The amplifier adds its own error (Vio (output offset voltage) + the noise Vn (1/f noise))
to this modulated signal.
This signal is then demodulated (Chop2), but since the noise and the offset are
modulated only once, they are transposed to the high frequency, leaving the output
signal of the amplifier without any offset and low frequency noise. Consequently, the
input signal is amplified with a very low offset and 1/f noise.
To get rid of the high frequency part of the output signal (which is useless) a low pass
filter is implemented.
To further suppress the remaining ripple down to a desired level, another low pass filter
may be added externally on the output of the TSZ121, TSZ122, or TSZ124 device.
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TSZ121, TSZ122, TSZ124
5.2
Application information
Operating voltages
TSZ121, TSZ122, and TSZ124 devices can operate from 1.8 to 5.5 V. The parameters are
fully specified for 1.8 V, 3.3 V, and 5 V power supplies. However, the parameters are very
stable in the full VCC range and several characterization curves show the TSZ121, TSZ122,
and TSZ124 device characteristics at 1.8 V and 5.5 V. Additionally, the main specifications
are guaranteed in extended temperature ranges from -40 to 125 ° C.
5.3
Input pin voltage ranges
TSZ121, TSZ122, and TSZ124 devices have internal ESD diode protection on the inputs.
These diodes are connected between the input and each supply rail to protect the input
MOSFETs from electrical discharge.
If the input pin voltage exceeds the power supply by 0.5 V, the ESD diodes become
conductive and excessive current can flow through them. Without limitation this over
current can damage the device.
In this case, it is important to limit the current to 10 mA, by adding resistance on the input
pin, as described in Figure 42: "Input current limitation".
Figure 42: Input current limitation
5.4
Rail-to-rail input
TSZ121, TSZ122, and TSZ124 devices have a rail-to-rail input, and the input common
mode range is extended from (VCC-) - 0.1 V to (VCC+) + 0.1 V.
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Application information
5.5
TSZ121, TSZ122, TSZ124
Input offset voltage drift over temperature
The maximum input voltage drift variation over temperature is defined as the offset
variation related to the offset value measured at 25 °C. The operational amplifier is one of
the main circuits of the signal conditioning chain, and the amplifier input offset is a major
contributor to the chain accuracy. The signal chain accuracy at 25 °C can be compensated
during production at application level. The maximum input voltage drift over temperature
enables the system designer to anticipate the effect of temperature variations.
The maximum input voltage drift over temperature is computed using Equation 1.
Equation 1
∆Vio
V T – Vio 25 °C
= max io
∆T
T – 25 °C
Where T = -40 °C and 125 °C.
The TSZ121, TSZ122, and TSZ124 datasheet maximum value is guaranteed by
measurements on a representative sample size ensuring a Cpk (process capability index)
greater than 1.3.
5.6
Rail-to-rail output
The operational amplifier output levels can go close to the rails: to a maximum of 30 mV
above and below the rail when connected to a 10 kΩ resistive load to VCC/2.
5.7
Capacitive load
Driving large capacitive loads can cause stability problems. Increasing the load
capacitance produces gain peaking in the frequency response, with overshoot and ringing
in the step response. It is usually considered that with a gain peaking higher than 2.3 dB an
op amp might become unstable.
Generally, the unity gain configuration is the worst case for stability and the ability to drive
large capacitive loads.
Figure 43: "Stability criteria with a serial resistor at VDD = 5 V" and Figure 44: "Stability
criteria with a serial resistor at VDD = 1.8 V" show the serial resistor that must be added to
the output, to make a system stable. Figure 45: "Test configuration for Riso" shows the test
configuration using an isolation resistor, Riso.
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TSZ121, TSZ122, TSZ124
Application information
Figure 43: Stability criteria with a serial resistor at VDD
=5V
Figure 44: Stability criteria with a serial resistor at VDD
= 1.8 V
Figure 45: Test configuration for Riso
5.8
PCB layout recommendations
Particular attention must be paid to the layout of the PCB, tracks connected to the amplifier,
load, and power supply. The power and ground traces are critical as they must provide
adequate energy and grounding for all circuits. Good practice is to use short and wide PCB
traces to minimize voltage drops and parasitic inductance.
In addition, to minimize parasitic impedance over the entire surface, a multi-via technique
that connects the bottom and top layer ground planes together in many locations is often
used.
The copper traces that connect the output pins to the load and supply pins should be as
wide as possible to minimize trace resistance.
5.9
Optimized application recommendation
TSZ121, TSZ122, and TSZ124 devices are based on chopper architecture. As they are
switched devices, it is strongly recommended to place a 0.1 µF capacitor as close as
possible to the supply pins.
A good decoupling has several advantages for an application. First, it helps to reduce
electromagnetic interference. Due to the modulation of the chopper, the decoupling
capacitance also helps to reject the small ripple that may appear on the output.
TSZ121, TSZ122, and TSZ124 devices have been optimized for use with 10 kΩ in the
feedback loop. With this, or a higher value of resistance, these devices offer the best
performance.
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Application information
5.10
TSZ121, TSZ122, TSZ124
EMI rejection ration (EMIRR)
The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI
immunity of operational amplifiers. An adverse effect that is common to many op amps is a
change in the offset voltage as a result of RF signal rectification.
The TSZ121, TSZ122, and TSZ124 have been specially designed to minimize susceptibility
to EMIRR and show an extremely good sensitivity. Figure 46: "EMIRR on IN+ pin" shows
the EMIRR IN+ of the TSZ121, TSZ122, and TSZ124 measured from 10 MHz up to
2.4 GHz.
Figure 46: EMIRR on IN+ pin
5.11
Application examples
5.11.1
Oxygen sensor
The electrochemical sensor creates a current proportional to the concentration of the gas
being measured. This current is converted into voltage thanks to R resistance. This voltage
is then amplified by TSZ121, TSZ122, and TSZ124 devices (see Figure 47: "Oxygen
sensor principle schematic").
Figure 47: Oxygen sensor principle schematic
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TSZ121, TSZ122, TSZ124
Application information
The output voltage is calculated using Equation 2:
Equation 2
Vou t = I × R – Vio ×
R2
+1
R1
As the current delivered by the O2 sensor is extremely low, the impact of the V io can
become significant with a traditional operational amplifier. The use of the chopper amplifier
of the TSZ121, TSZ122, or TSZ124 is perfect for this application.
In addition, using TSZ121, TSZ122, or TSZ124 devices for the O2 sensor application
ensures that the measurement of O2 concentration is stable even at different temperature
thanks to a very good ΔVio/ΔT.
5.11.2
Precision instrumentation amplifier
The instrumentation amplifier uses three op amps. The circuit, shown in Figure 48:
"Precision instrumentation amplifier schematic", exhibits high input impedance, so that the
source impedance of the connected sensor has no impact on the amplification.
Figure 48: Precision instrumentation amplifier schematic
The gain is set by tuning the Rg resistor. With R1 = R2 and R3 = R4, the output is given by
Equation 3.
Equation 3
The matching of R1, R2 and R3, R4 is important to ensure a good common mode rejection
ratio (CMR).
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Application information
5.11.3
TSZ121, TSZ122, TSZ124
Low-side current sensing
Power management mechanisms are found in most electronic systems. Current sensing is
useful for protecting applications. The low-side current sensing method consists of placing
a sense resistor between the load and the circuit ground. The resulting voltage drop is
amplified using TSZ121, TSZ122, and TSZ124 devices (see Figure 49: "Low-side current
sensing schematic").
Figure 49: Low-side current sensing schematic
Vout can be expressed as follows:
Equation 4
Vou t = Rshun t × I 1 –
Rg2
Rg2 + Rf2
1+
Rg2 × Rf2
Rf1
Rf1
Rf1
+ Ip
– l n × Rf1 – Vio 1 +
× 1+
Rg2 + Rf2
Rg1
Rg1
Rg1
Assuming that Rf2 = Rf1 = Rf and Rg2 = Rg1 = Rg, Equation 4 can be simplified as follows:
Equation 5
Vout = Rshunt × I
Rf
Rf
– Vio 1 +
+ Rf × I io
Rg
Rg
The main advantage of using the chopper of the TSZ121, TSZ122, and TSZ124, for a
low-side current sensing, is that the errors due to Vio and Iio are extremely low and may be
neglected.
Therefore, for the same accuracy, the shunt resistor can be chosen with a lower value,
resulting in lower power dissipation, lower drop in the ground path, and lower cost.
Particular attention must be paid on the matching and precision of Rg1, Rg2, Rf1, and Rf2, to
maximize the accuracy of the measurement.
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TSZ121, TSZ122, TSZ124
6
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
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Package information
6.1
TSZ121, TSZ122, TSZ124
SC70-5 (or SOT323-5) package information
Figure 50: SC70-5 (or SOT323-5) package outline
SIDE VIEW
DIMENSIONS IN MM
GAUGE PLANE
COPLANAR LEADS
SEATING PLANE
TOP VIEW
Table 6: SC70-5 (or SOT323-5) mechanical data
Dimensions
Ref.
Millimeters
Min.
A
Typ.
0.80
A1
26/38
Inches
Max.
Min.
1.10
0.032
Typ.
0.043
0.10
A2
0.80
b
0.90
Max.
0.004
1.00
0.032
0.035
0.15
0.30
0.006
0.012
c
0.10
0.22
0.004
0.009
D
1.80
2.00
2.20
0.071
0.079
0.087
E
1.80
2.10
2.40
0.071
0.083
0.094
E1
1.15
1.25
1.35
0.045
0.049
0.053
e
0.65
0.025
e1
1.30
0.051
L
0.26
<
0°
0.36
0.46
0.010
8°
0°
DocID023563 Rev 5
0.014
0.039
0.018
8°
TSZ121, TSZ122, TSZ124
6.2
Package information
SOT23-5 package information
Figure 51: SOT23-5 package outline
Table 7: SOT23-5 mechanical data
Dimensions
Ref.
Millimeters
Min.
Typ.
A
Inches
Max.
Typ.
1.45
A1
0.00
0.15
0.90
1.30
b
0.30
c
0.08
A2
Min.
1.15
Max.
0.057
0.000
0.006
0.035
0.051
0.50
0.012
0.020
0.22
0.003
0.009
0.045
D
2.90
0.114
E
2.80
0.110
E1
1.60
0.063
e
0.95
0.037
e1
1.90
0.075
L
0.45
0.30
0.60
0.018
0.012
0.024
s
4
0
8
4
0
8
DocID023563 Rev 5
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Package information
TSZ121, TSZ122, TSZ124
Figure 52: SOT23-5 recommended footprint
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TSZ121, TSZ122, TSZ124
6.3
Package information
DFN8 2x2 package information
Figure 53: DFN8 2x2 package outline
Table 8: DFN8 2x2 mechanical data
Dimensions
Ref.
A
Millimeters
Inches
Min.
Typ.
Max.
Min.
Typ.
Max.
0.51
0.55
0.60
0.020
0.022
0.024
A1
0.05
A3
0.002
0.15
0.006
b
0.18
0.25
0.30
0.007
0.010
0.012
D
1.85
2.00
2.15
0.073
0.079
0.085
D2
1.45
1.60
1.70
0.057
0.063
0.067
E
1.85
2.00
2.15
0.073
0.079
0.085
E2
0.75
0.90
1.00
0.030
0.035
0.039
e
0.50
0.020
L
0.425
0.017
ddd
0.08
0.003
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Package information
TSZ121, TSZ122, TSZ124
Figure 54: DFN8 2x2 recommended footprint
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TSZ121, TSZ122, TSZ124
6.4
Package information
MiniSO8 package information
Figure 55: MiniSO8 package outline
Table 9: MiniSO8 mechanical data
Dimensions
Ref.
Millimeters
Min.
Typ.
A
Max.
Min.
Typ.
1.1
A1
0
A2
0.75
b
0.22
c
0.08
D
2.80
E
E1
0.043
0
0.95
0.030
0.40
0.009
0.016
0.23
0.003
0.009
3.00
3.20
0.11
0.118
0.126
4.65
4.90
5.15
0.183
0.193
0.203
2.80
3.00
3.10
0.11
0.118
0.122
0.85
0.65
0.40
0.60
0.006
0.033
0.80
0.016
0.024
0.95
0.037
L2
0.25
0.010
ccc
0°
0.037
0.026
L1
k
Max.
0.15
e
L
Inches
8°
0.10
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0°
0.031
8°
0.004
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Package information
6.5
TSZ121, TSZ122, TSZ124
SO8 package information
Figure 56: SO8 package outline
Table 10: SO8 mechanical data
Dimensions
Ref.
Millimeters
Min.
Typ.
A
Max.
Min.
Typ.
1.75
0.25
Max
0.069
A1
0.10
A2
1.25
b
0.28
0.48
0.011
0.019
c
0.17
0.23
0.007
0.010
D
4.80
4.90
5.00
0.189
0.193
0.197
E
5.80
6.00
6.20
0.228
0.236
0.244
E1
3.80
3.90
4.00
0.150
0.154
0.157
e
0.004
0.010
0.049
1.27
0.050
h
0.25
0.50
0.010
0.020
L
0.40
1.27
0.016
0.050
L1
k
ccc
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Inches
1.04
1°
0.040
8°
0.10
DocID023563 Rev 5
1°
8°
0.004
TSZ121, TSZ122, TSZ124
6.6
Package information
QFN16 3x3 package information
Figure 57: QFN16 3x3 package outline
DocID023563 Rev 5
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Package information
TSZ121, TSZ122, TSZ124
Table 11: QFN16 3x3 mechanical data
Dimensios
Ref.
Millimeters
Inches
Min.
Typ.
Max.
Min.
Typ.
Max.
A
0.80
0.90
1.00
0.031
0.035
0.039
A1
0
0.05
0
A3
0.20
b
0.18
D
2.90
D2
1.50
E
2.90
E2
1.50
e
L
3.00
3.00
0.008
0.30
0.007
3.10
0.114
1.80
0.059
3.10
0.114
1.80
0.059
0.50
0.30
0.012
0.118
0.122
0.071
0.118
0.122
0.071
0.020
0.50
0.012
Figure 58: QFN16 3x3 recommended footprint
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0.002
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0.020
TSZ121, TSZ122, TSZ124
6.7
Package information
TSSOP14 package information
Figure 59: TSSOP14 package outline
aaa
Table 12: TSSOP14 mechanical data
Dimensions
Ref.
Millimeters
Min.
Typ.
A
Inches
Max.
Min.
Typ.
1.20
A1
0.05
A2
0.80
b
Max.
0.047
0.15
0.002
0.004
0.006
1.05
0.031
0.039
0.041
0.19
0.30
0.007
0.012
c
0.09
0.20
0.004
0.0089
D
4.90
5.00
5.10
0.193
0.197
0.201
E
6.20
6.40
6.60
0.244
0.252
0.260
E1
4.30
4.40
4.50
0.169
0.173
0.176
e
L
0.65
0.45
L1
k
aaa
1.00
0.60
0.0256
0.75
0.018
1.00
0°
0.024
0.030
0.039
8°
0.10
DocID023563 Rev 5
0°
8°
0.004
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Ordering information
7
TSZ121, TSZ122, TSZ124
Ordering information
Table 13: Order codes
Order code
Temperature range
Package
Packaging
Marking
TSZ121ICT
SC70-5
K44
TSZ121ILT
SΟΤ23-5
K143
TSZ122IQ2T
DFN8 2x2
K33
MiniSO8
K208
SO8
TSZ122I
TSZ122IST
-40 to 125 °C
TSZ122IDT
TSZ124IQ4T
QFN16 3x3
TSZ124IPT
TSZ121IYLT
(1)
TSZ122IYDT
(2)
TSZ122IYST
(1)
TSZ124IYPT
(1)
-40 to 125 °C automotive grade
Tape and reel
K193
TSSOP14
TSZ124I
SΟΤ23-5
K192
SO8
K192D
MiniSO8
K192
TSSOP14
TSZ124IY
Notes:
(1)
Qualified and characterized according to AEC Q100 and Q003 or equivalent, advanced screening according to
AEC Q001 & Q 002 or equivalent.
(2)
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Automotive qualification ongoing
DocID023563 Rev 5
TSZ121, TSZ122, TSZ124
8
Revision history
Revision history
Date
16-Aug-2012
25-Apr-2013
11-Sep-2013
23-May-2014
09-May-2016
Revision
Changes
1
Initial release.
2
Added dual and quad products (TSZ122 and TSZ124 respectively)
Updated title
Added following packages: DFN8 2x2, MiniSO8, QFN16 3x3,
TSSOP14.
Updated Features
Added Benefits and Related products
Updated Description
Updated Table 1 (Rthja, ESD)
Updated Table 3 (Vio, ∆Vio/∆T, CMR, Avd, ICC, en, and Cs)
Updated Table 4 (Vio, ∆Vio/∆T, CMR, ICC, en, and Cs)
Updated Table 5 (Vio, ∆Vio/∆T, CMR, SVR, EMIRR, ICC, ts, en, and Cs).
Updated curves of Section 3: Electrical characteristics
Added Section 4.7: Capacitive load
Small update Section 4.9: Optimized application recommendation
(capacitor).
Added Section 4.10: EMI rejection ration (EMIRR)
Updated Table 10: Order codes
3
Added SO8 package for commercial part number TSZ122IDT
Related products: added hyperlinks for TSV71x and TSV73x
products.
Table 1: updated CDM information
Figure 6, Figure 7: updated X-axes titles
Figure 12: updated X-axis and Y-axis titles
Figure 19: updated title
Figure 26: updated X-axis (logarithmic scale)
Figure 27 and Figure 28: updated Y-axis titles
4
Table 1: updated ESD information
Table 5: added footnote 3
Table 10: Order codes: added automotive qualification footnotes 1
and 2; updated marking of TSZ122IST.
Updated disclaimer
5
Updated document layout
Table 13: "Order codes": added new automotive grade order code
TSZ122IYD, updated footnotes of other automotive grade order
codes.
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TSZ121, TSZ122, TSZ124
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