DN124 - New Battery Charger ICs Need No Heat Sinks

Fused Lead Battery Charger ICs Need No Heat Sinks
Design Note 124
Carl Nelson
The LT ®1510 and LT1511 are high efficiency batterycharging chips capable of output powers up to 25W and
50W, respectively. These chips are intended for fastcharging batteries in modern portable equipment where
space is at a premium. They are therefore packaged in
low profile surface mount packages and run at a fairly
high frequency (200kHz) to minimize the height and
footprint of the complete battery charger. To minimize
thermal resistance, these packages are specially constructed with the die-attach paddle connected (fused)
directly to multiple package leads.
When operating these chips near their maximum
power levels, extra care should be taken to minimize
chip power dissipation and to keep the overall thermal
resistance of the package-board combination as low as
possible. Figure 1 shows a simple way to reduce power
dissipation with no loss in performance. The LT1510
and LT1511 use an external diode (D2) and capacitor
(CX) to generate a voltage that is higher than the input
voltage. This voltage is used to supply the base drive
to the internal NPN power switch to allow it to saturate
with a forced hFE of about 50. Switching speed and onresistance losses are minimized with this technique. The
required boost voltage is only 3V, but with the normal
connection of D2, the resulting boost voltage is equal
to the battery voltage. Unnecessarily high base drive
losses result with high battery voltages. Connecting D2
to a 3.3V or 5V supply (V X) instead of to the battery
reduces chip dissipation by approximately:
Power reduction = (VBAT – VX)(ICHRG)(VBAT)/(50)(VIN)
With a 20V adapter charging a 12.6V battery at 3A, and
V X = 3.3V, chip power is reduced by 0.35W.
Fused-lead packages conduct most of their heat out the
leads. This makes it very important to provide as much
PC board copper around the leads as is practical. Total
thermal resistance of the package-board combination
is dominated by the characteristics of the board in
the immediate area of the package. This means both
lateral thermal resistance across the board and vertical
03/96/124_conv
FLOATING BOOST VOLTAGE
EQUAL TO D2 ANODE VOLTAGE
APPEARS ACROSS THIS CAPACITOR
SW
D1
L1
10μH
CX
0.47μF
D3
CLP
RS4
0.033Ω
LT1511
BOOST
VCC
D2
SPIN
SENSE
BREAK CONNECTION
TO OUTPUT NODE AND
CONNECT D2 TO 3.3V
OR 5V SUPPLY. USE
LOCAL 1μF CERAMIC
BYPASS CAPACITOR
RS3
200Ω
w
+
TO
SYSTEM
POWER
RS4 AND D3 CARRY
FULL ADAPTER CURRENT
BAT
RS1
0.033Ω
ADAPTER
IN
RS2
200Ω
COUT
22μF
TO
SYSTEM
BATTERY
3.3V
NOTE: TECHNIQUE ALSO APPLIES TO LT1510. SOME COMPONENTS
NOT SHOWN TO SIMPLIFY SCHEMATIC
DN124 F01
Figure 1
thermal resistance through the board to other copper
layers. Each layer acts as a thermal heat spreader that
increases the heat sinking effectiveness of extended
areas of the board.
Total board area becomes an important factor when
the area of the board drops below about 20 square
inches. The graphs in Figures 2 and 3 show thermal
resistance versus board area for 2-layer and 4-layer
boards. Note that 4-layer boards have significantly
lower thermal resistance, but both types show a rapid
increase for reduced board areas. Figures 4 and 5 show
actual measured lead temperatures for chargers operating at full current. Battery voltage and input voltage
will affect device power dissipation, so the data sheet
power calculations must be used to extrapolate these
readings to other situations.
Vias should be used to connect board layers together.
Planes under the charger area can be cut away from
the rest of the board and connected with vias to form
both a low thermal resistance system and to act as a
ground plane for reduced EMI.
Glue-on, chip-mounted heat sinks are effective only in
moderate power applications where the PC board copper cannot be used, or where the board size is small.
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respective owners.
60
40
55
35
THERMAL RESISTANCE (°C/W)
THERMAL RESISTANCE (°C/W)
45
2-LAYER BOARD
30
4-LAYER BOARD
25
20
MEASURED FROM AIR AMBIENT
TO DIE USING COPPER LANDS
AS SHOWN ON DATA SHEET
15
2-LAYER BOARD
45
4-LAYER BOARD
40
35
MEASURED FROM AIR AMBIENT
TO DIE USING COPPER LANDS
AS SHOWN ON DATA SHEET
30
10
25
0
5
20
15
25
10
BOARD AREA (IN2)
30
35
0
5
DN124 F02
Figure 2. LT1511 Thermal Resistance
20
15
25
10
BOARD AREA (IN2)
30
35
DN124 F03
Figure 3. LT1510 Thermal Resistance
110
90
NOTE: PEAK DIE TEMPERATURE WILL BE
ABOUT 10°C HIGHER THAN LEAD TEMPERATURE AT 3A CHARGING CURRENT
90
2-LAYER BOARD
80
4-LAYER BOARD
70
60
VIN = 16V
VBAT = 8.4V
ICHRG = 3A
TA = 25°C
50
40
0
5
4-LAYER BOARD
WITH VBOOST = 3.3V
20
15
25
10
BOARD AREA (IN2)
NOTE: PEAK DIE TEMPERATURE WILL BE
ABOUT 10°C HIGHER THAN LEAD TEMPERATURE AT 1.3A CHARGING CURRENT
80
LEAD TEMPERATURE (°C)
100
LEAD TEMPERATURE (°C)
50
70
2-LAYER BOARD
60
4-LAYER BOARD
50
VIN = 16V
VBAT = 8.4V
ICHRG = 1.3A
VBOOST = VBAT
TA = 25°C
40
30
20
30
35
DN124 F04
0
5
20
15
25
10
BOARD AREA (IN2)
30
35
DN124 F05
Figure 4. LT1511 Lead Temperature
Figure 5. LT1510 Lead Temperature
They offer very little improvement in a properly laid out
multilayer board of reasonable size.
dissipate significant power but it can be located away
from the charger. The current sense resistors used with
the LT1511 dissipate power equal to:
The suggested methods for a final check on chip operating temperature are to solder a small thermocouple on
top of one of the IC ground leads or to use an IR sensor
on top of the package. Using either method, the temperature measured either way will be about 10°C lower
than actual peak die temperature when the charger is
delivering full current. The 125°C rating of these charger
chips means that lead temperature readings as high as
100°C (with maximum ambient temperature) are still
comfortably within the device ratings.
Another consideration is the power dissipation of other
parts of the charger and the surrounding circuitry used for
other purposes. The catch diode (D1) will dissipate a
power equal to:
PDIODE = (ICHRG)(VF )(VIN – VBAT )/ VIN
With the VIN = 16V, VBAT = 8.4V, VF = 0.45V, and ICHRG
= 3A, the diode dissipates 0.64W. Unfortunately, it must
be located very close to the charger chip to prevent
inductive spikes on the Switch pin. Increase in charger
chip temperature due to power dissipation in D1 is about
12°C/W. D3 is used for input protection and can also
Data Sheet Download
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P(RS1) = RS1(ICHRG)2
P(RS4) = RS4 (IADPT )2
RS4 power depends only on charger output current, but
RS1 carries full adapter current. These resistors, which
typically dissipate a total of about 0.5W, will also increase
chip temperature at about 12°C/W, assuming that they
are close to the charger chip.
It is assumed that L1 contributes only slightly to chip
temperature rise because its power dissipation is normally fairly low compared to its heat sinking ability. This
will be true if a low loss core is used (Kool Mμ, etc.),
and the winding resistance is less than 0.2V/ICHRG. If
the charger is located near other high power dissipation circuitry, direct temperature testing may be the
only accurate way to ensure safe device temperatures.
Finally, don’t forget about losses in PC board trace
resistance. A 100mil wide trace is huge by modern
standards, but a pair of these traces six inches long,
in 1/2oz copper, delivering 3A, would have a resistance
of ≈ 0.12Ω, and a power loss of 1.1W!
For applications help,
call (408) 432-1900
dn124f_conv LT/GP 0396 185K • PRINTED IN THE USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
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© LINEAR TECHNOLOGY CORPORATION 1996
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